Searched refs:FNEG (Results 1 - 25 of 27) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp426 setOperationAction(ISD::FNEG, VT, Expand);
499 setTargetDAGCombine(ISD::FNEG);
1585 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
2477 SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R);
3523 (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) {
3529 if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) {
3536 if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS) {
3548 if (LHS.getOpcode() == ISD::FNEG && fnegFoldsIntoOp(Opc))
3555 if (LHS.getOpcode() == ISD::FNEG)
[all...]
H A DAMDGPUISelDAGToDAG.cpp2401 if (Src.getOpcode() == ISD::FNEG) {
2441 if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG)
2474 if (Src.getOpcode() == ISD::FNEG) {
2485 if (Lo.getOpcode() == ISD::FNEG) {
2490 if (Hi.getOpcode() == ISD::FNEG) {
H A DSIISelLowering.cpp596 setOperationAction(ISD::FNEG, MVT::v2f16, Legal);
668 setOperationAction(ISD::FNEG, MVT::v4f16, Custom);
681 setOperationAction(ISD::FNEG, MVT::v2f16, Custom);
4081 case ISD::FNEG:
4364 case ISD::FNEG: {
7579 SDValue FNegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
7723 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f32,
7821 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f64, DivScale0);
8796 case ISD::FNEG:
9286 if ((Vec.getOpcode() == ISD::FNEG ||
[all...]
H A DR600ISelLowering.cpp1865 if (FNeg.getOpcode() != ISD::FNEG) {
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h640 FNEG, FABS, FSQRT, FCBRT, FSIN, FCOS, FPOWI, FPOW, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1592 case ISD::FNEG: return visitFNEG(N);
11116 FPOpcode = ISD::FNEG;
11139 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, FPOp);
11229 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
11242 if (N0.getOpcode() == ISD::FNEG) {
11261 if (N0.getOpcode() == ISD::FNEG)
11786 DAG.getNode(ISD::FNEG, SL, VT, N1), Flags);
11793 DAG.getNode(ISD::FNEG, SL, VT,
11799 if (N0.getOpcode() == ISD::FNEG && isContractableFMUL(N0.getOperand(0)) &&
11804 DAG.getNode(ISD::FNEG, S
[all...]
H A DSelectionDAGBuilder.h690 void visitFNeg(const User &I) { visitUnary(I, ISD::FNEG); }
H A DLegalizeFloatTypes.cpp100 case ISD::FNEG: R = SoftenFloatRes_FNEG(N); break;
458 // Expand Y = FNEG(X) -> Y = X ^ sign mask
1162 case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break;
1248 DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo),
1413 Lo = DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo);
1414 Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi);
2117 case ISD::FNEG:
H A DLegalizeVectorOps.cpp410 case ISD::FNEG:
875 case ISD::FNEG:
1412 // TODO: If FNEG had fast-math-flags, they'd get propagated to this FSUB.
1421 // For floating-point values, (a-b) is the same as a+(-b). If FNEG is legal,
1425 if (TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
H A DSelectionDAGDumper.cpp192 case ISD::FNEG: return "fneg";
H A DLegalizeDAG.cpp1524 TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) {
1526 SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue);
3156 case ISD::FNEG:
3157 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3159 // TODO: If FNEG has fast-math-flags, propagate them to the FSUB.
3255 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3257 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
4507 case ISD::FNEG:
H A DLegalizeVectorTypes.cpp90 case ISD::FNEG:
883 case ISD::FNEG:
2844 case ISD::FNEG:
H A DTargetLowering.cpp3775 if (N0.getOpcode() == ISD::FNEG) {
3779 SDValue NegN1 = DAG.getNode(ISD::FNEG, dl, N0.getValueType(), N1);
5486 if (Op.getOpcode() == ISD::FNEG)
5614 if (Op.getOpcode() == ISD::FNEG)
H A DFastISel.cpp1731 // If the target has ISD::FNEG, use it.
1733 unsigned ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG,
H A DSelectionDAG.cpp4119 case ISD::FNEG:
4454 case ISD::FNEG:
4524 case ISD::FNEG:
4744 case ISD::FNEG:
4749 if (OpOpcode == ISD::FNEG) // --X -> X
4753 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1612 setOperationAction(ISD::FNEG, MVT::f64, Custom);
1719 setOperationAction(ISD::FNEG, MVT::f128, Legal);
1722 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1741 setOperationAction(ISD::FNEG, MVT::f128, Custom);
2694 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2839 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
3049 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp999 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) ||
1008 if (Op0.getOpcode() == ISD::FNEG) {
1047 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) ||
1053 if (Op0.getOpcode() == ISD::FNEG) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1594 case FNeg: return ISD::FNEG;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp543 setOperationAction(ISD::FNEG, MVT::f16, Expand);
544 setOperationAction(ISD::FNEG, MVT::v2f16, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp659 setOperationAction(ISD::FNEG, VT, Expand);
898 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
899 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
1020 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
1065 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
7639 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
7658 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
7675 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp265 setOperationAction(ISD::FNEG, MVT::f128, Expand);
443 setOperationAction(ISD::FNEG, MVT::f16, Promote);
468 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
492 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
715 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
5138 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp498 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
530 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
2198 // This optimization is invalid for strict comparisons, since FNEG
2206 if (N->getOpcode() == ISD::FNEG) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp525 // Use XORP to simulate FNEG.
526 setOperationAction(ISD::FNEG, VT, Custom);
555 // Use XORP to simulate FNEG.
556 setOperationAction(ISD::FNEG , MVT::f32, Custom);
700 setOperationAction(ISD::FNEG, MVT::f128, Custom);
842 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
898 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
1173 setOperationAction(ISD::FNEG, VT, Custom);
1460 setOperationAction(ISD::FNEG, VT, Custom);
2001 setTargetDAGCombine(ISD::FNEG);
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1482 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp138 setOperationAction(ISD::FNEG, MVT::f16, Promote);

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