Searched refs:FMINNUM (Results 1 - 25 of 26) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h645 /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
651 /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0.
652 FMINNUM, FMAXNUM, enumerator in enum:llvm::ISD::NodeType
656 /// FMINNUM/FMAXNUM in the handling of signaling NaNs. If one input is a
H A DBasicTTIImpl.h1250 ISDs.push_back(ISD::FMINNUM);
H A DTargetLowering.h2259 case ISD::FMINNUM:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2771 ISD = ISD::FMINNUM;
2778 {ISD::FMINNUM, MVT::v4f32, 4},
2782 {ISD::FMINNUM, MVT::v2f64, 3},
2794 {ISD::FMINNUM, MVT::v4f32, 2},
2811 {ISD::FMINNUM, MVT::v4f32, 1},
2812 {ISD::FMINNUM, MVT::v4f64, 1},
2813 {ISD::FMINNUM, MVT::v8f32, 2},
2844 {ISD::FMINNUM, MVT::v8f64, 1},
2845 {ISD::FMINNUM, MVT::v16f32, 2},
2853 {ISD::FMINNUM, MV
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp323 case Intrinsic::minnum: Opcode = ISD::FMINNUM; break;
389 Opcode = ISD::FMINNUM; break;
H A DPPCISelLowering.cpp611 setOperationAction(ISD::FMINNUM, VT, Legal);
1031 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
1076 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp413 setOperationAction(ISD::FMINNUM, MVT::f32, Custom);
415 setOperationAction(ISD::FMINNUM, MVT::f64, Custom);
602 setOperationAction(ISD::FMINNUM, MVT::f16, Custom);
609 setOperationAction(ISD::FMINNUM, MVT::v4f16, Expand);
657 setOperationAction(ISD::FMINNUM, MVT::v2f16, Custom);
659 setOperationAction(ISD::FMINNUM, MVT::v4f16, Custom);
722 setTargetDAGCombine(ISD::FMINNUM);
4084 case ISD::FMINNUM:
5808 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
8622 case ISD::FMINNUM
[all...]
H A DAMDGPUISelLowering.cpp258 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
404 setOperationAction(ISD::FMINNUM, VT, Expand);
518 case ISD::FMINNUM:
3647 return ISD::FMINNUM;
3648 case ISD::FMINNUM:
3764 case ISD::FMINNUM:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp182 case ISD::FMINNUM: return "fminnum";
H A DLegalizeVectorOps.cpp412 case ISD::FMINNUM:
927 case ISD::FMINNUM:
H A DLegalizeFloatTypes.cpp69 case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break;
1131 case ISD::FMINNUM: ExpandFloatRes_FMINNUM(N, Lo, Hi); break;
2131 case ISD::FMINNUM:
H A DLegalizeVectorTypes.cpp114 case ISD::FMINNUM:
914 case ISD::FMINNUM:
2085 CombineOpc = NoNaN ? ISD::FMINNUM : ISD::FMINIMUM;
2719 case ISD::FMINNUM:
H A DSelectionDAGBuilder.cpp3334 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
3336 if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT))
3337 Opc = ISD::FMINNUM;
3341 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ?
3342 ISD::FMINNUM : ISD::FMINIMUM;
6220 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
7648 if (visitBinaryFloatCall(I, ISD::FMINNUM))
H A DLegalizeDAG.cpp3186 case ISD::FMINNUM:
3937 case ISD::FMINNUM:
4451 case ISD::FMINNUM:
H A DTargetLowering.cpp6318 unsigned NewOp = Node->getOpcode() == ISD::FMINNUM ?
6341 // If the target has FMINIMUM/FMAXIMUM but not FMINNUM/FMAXNUM use that
6345 Node->getOpcode() == ISD::FMINNUM ? ISD::FMINIMUM : ISD::FMAXIMUM;
6355 // FMINNUM/FMAXNUM node. If we were to fall through to the default
6360 Node->getOpcode() == ISD::FMINNUM ? ISD::SETLT : ISD::SETGT;
6365 // as this is implied by the FMINNUM/FMAXNUM semantics.
7630 BaseOpcode = NoNaN ? ISD::FMINNUM : ISD::FMINIMUM;
H A DDAGCombiner.cpp1595 case ISD::FMINNUM: return visitFMINNUM(N);
8341 unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM;
8356 unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM;
H A DSelectionDAG.cpp4154 case ISD::FMINNUM:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp168 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
185 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp546 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
551 setOperationAction(ISD::FMINNUM, MVT::v2f64, Legal);
556 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
561 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
566 setOperationAction(ISD::FMINNUM, MVT::f128, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp639 setOperationAction(ISD::FMINNUM, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1341 // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1486 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS,
1588 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp573 ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM}) {
579 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp341 setOperationAction(ISD::FMINNUM, VT, Legal);
724 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
1383 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1386 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1388 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1399 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1435 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
1437 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal);
3749 ? ISD::FMINNUM : ISD::FMAXNUM;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp452 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
513 setOperationAction(ISD::FMINNUM, Ty, Legal);
530 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
935 {ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FMINNUM, ISD::FMAXNUM})
11025 return DAG.getNode(ISD::FMINNUM, SDLoc(N), N->getValueType(0),
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp159 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);

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