| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 645 /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
652 FMINNUM, FMAXNUM, enumerator in enum:llvm::ISD::NodeType
656 /// FMINNUM/FMAXNUM in the handling of signaling NaNs. If one input is a
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| H A D | BasicTTIImpl.h | 1255 ISDs.push_back(ISD::FMAXNUM);
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| H A D | TargetLowering.h | 2260 case ISD::FMAXNUM:
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCTargetTransformInfo.cpp | 324 case Intrinsic::maxnum: Opcode = ISD::FMAXNUM; break;
393 Opcode = ISD::FMAXNUM; break;
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| H A D | PPCISelLowering.cpp | 610 setOperationAction(ISD::FMAXNUM, VT, Legal);
1032 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
1077 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 414 setOperationAction(ISD::FMAXNUM, MVT::f32, Custom);
416 setOperationAction(ISD::FMAXNUM, MVT::f64, Custom);
601 setOperationAction(ISD::FMAXNUM, MVT::f16, Custom);
610 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Expand);
656 setOperationAction(ISD::FMAXNUM, MVT::v2f16, Custom);
660 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Custom);
723 setTargetDAGCombine(ISD::FMAXNUM);
4085 case ISD::FMAXNUM:
5810 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
8623 case ISD::FMAXNUM
[all...] |
| H A D | AMDGPUISelLowering.cpp | 259 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
405 setOperationAction(ISD::FMAXNUM, VT, Expand);
519 case ISD::FMAXNUM:
3646 case ISD::FMAXNUM:
3649 return ISD::FMAXNUM;
3763 case ISD::FMAXNUM:
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 184 case ISD::FMAXNUM: return "fmaxnum";
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| H A D | LegalizeVectorOps.cpp | 413 case ISD::FMAXNUM:
928 case ISD::FMAXNUM:
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| H A D | LegalizeFloatTypes.cpp | 71 case ISD::FMAXNUM: R = SoftenFloatRes_FMAXNUM(N); break;
1133 case ISD::FMAXNUM: ExpandFloatRes_FMAXNUM(N, Lo, Hi); break;
2130 case ISD::FMAXNUM:
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| H A D | LegalizeVectorTypes.cpp | 115 case ISD::FMAXNUM:
915 case ISD::FMAXNUM:
2082 CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXIMUM;
2720 case ISD::FMAXNUM:
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| H A D | SelectionDAGBuilder.cpp | 3351 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
3354 if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT))
3355 Opc = ISD::FMAXNUM;
3359 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ?
3360 ISD::FMAXNUM : ISD::FMAXIMUM;
6226 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
7654 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
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| H A D | LegalizeDAG.cpp | 3187 case ISD::FMAXNUM: {
3943 case ISD::FMAXNUM:
4452 case ISD::FMAXNUM:
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| H A D | DAGCombiner.cpp | 1596 case ISD::FMAXNUM: return visitFMAXNUM(N);
8341 unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM;
8356 unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM;
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| H A D | TargetLowering.cpp | 6341 // If the target has FMINIMUM/FMAXIMUM but not FMINNUM/FMAXNUM use that
6355 // FMINNUM/FMAXNUM node. If we were to fall through to the default
6365 // as this is implied by the FMINNUM/FMAXNUM semantics.
7627 BaseOpcode = NoNaN ? ISD::FMAXNUM : ISD::FMAXIMUM;
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| H A D | SelectionDAG.cpp | 4155 case ISD::FMAXNUM: {
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 169 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
186 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 544 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
549 setOperationAction(ISD::FMAXNUM, MVT::v2f64, Legal);
554 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
559 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
564 setOperationAction(ISD::FMAXNUM, MVT::f128, Legal);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 640 setOperationAction(ISD::FMAXNUM, VT, Expand);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1341 // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1486 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS,
1589 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 573 ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM}) {
580 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 342 setOperationAction(ISD::FMAXNUM, VT, Legal);
725 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
1384 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1387 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1389 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1400 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1436 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal);
1438 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal);
3749 ? ISD::FMINNUM : ISD::FMAXNUM;
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 453 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
514 setOperationAction(ISD::FMAXNUM, Ty, Legal);
531 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
935 {ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FMINNUM, ISD::FMAXNUM})
11022 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), N->getValueType(0),
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 160 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 752 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
2004 setTargetDAGCombine(ISD::FMAXNUM);
[all...] |