Searched refs:FABS (Results 1 - 25 of 27) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h640 FNEG, FABS, FSQRT, FCBRT, FSIN, FCOS, FPOWI, FPOW, enumerator in enum:llvm::ISD::NodeType
H A DBasicTTIImpl.h1244 ISDs.push_back(ISD::FABS);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp254 setOperationAction(ISD::FABS, MVT::f32, Legal);
403 setOperationAction(ISD::FABS, VT, Expand);
500 setTargetDAGCombine(ISD::FABS);
1600 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1603 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
2143 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
2179 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff);
3522 if ((LHS.getOpcode() == ISD::FABS && RHS.getOpcode() == ISD::FABS) ||
3529 if (RHS.getOpcode() == ISD::FABS || RH
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H A DSIISelLowering.cpp599 setOperationAction(ISD::FABS, MVT::v2f16, Legal);
669 setOperationAction(ISD::FABS, MVT::v4f16, Custom);
682 setOperationAction(ISD::FABS, MVT::v2f16, Custom);
4080 case ISD::FABS:
4377 case ISD::FABS: {
7662 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
8326 if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X)
8603 case ISD::FABS:
8797 case ISD::FABS:
9287 Vec.getOpcode() == ISD::FABS)
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H A DAMDGPUISelDAGToDAG.cpp2406 if (Src.getOpcode() == ISD::FABS) {
2441 if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG)
/freebsd-11-stable/contrib/gcc/
H A Dlibgcc2.c1830 #define FABS CONCAT2(__builtin_fabs, CEXT)
1921 if (FABS (c) < FABS (d))
1802 #define FABS macro
H A Dconvert.c208 CASE_MATHFN (FABS)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1613 setOperationAction(ISD::FABS, MVT::f64, Custom);
1720 setOperationAction(ISD::FABS, MVT::f128, Legal);
1723 setOperationAction(ISD::FABS, MVT::f128, Custom);
1742 setOperationAction(ISD::FABS, MVT::f128, Custom);
2694 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2839 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
3048 case ISD::FABS:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp181 case ISD::FABS: return "fabs";
H A DLegalizeFloatTypes.cpp67 case ISD::FABS: R = SoftenFloatRes_FABS(N); break;
1129 case ISD::FABS: ExpandFloatRes_FABS(N, Lo, Hi); break;
1245 Hi = DAG.getNode(ISD::FABS, dl, Tmp.getValueType(), Tmp);
2106 case ISD::FABS:
H A DDAGCombiner.cpp1593 case ISD::FABS: return visitFABS(N);
11112 FPOpcode = ISD::FABS;
11120 FPOpcode = ISD::FABS;
11230 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
11246 assert(N0.getOpcode() == ISD::FABS);
11264 assert(N0.getOpcode() == ISD::FABS);
12486 TLI.isOperationLegal(ISD::FABS, VT)) {
12519 DAG.getNode(ISD::FABS, DL, VT, X));
12521 return DAG.getNode(ISD::FABS, DL, VT, X);
12902 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, V
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H A DLegalizeDAG.cpp1521 // If FABS is legal transform FCOPYSIGN(x, y) => sign(x) ? -FABS(x) : FABS(X)
1523 if (TLI.isOperationLegalOrCustom(ISD::FABS, FloatVT) &&
1525 SDValue AbsValue = DAG.getNode(ISD::FABS, DL, FloatVT, Mag);
1567 // Transform FABS(x) => FCOPYSIGN(x, 0.0) if FCOPYSIGN is legal.
3164 case ISD::FABS:
4514 case ISD::FABS:
H A DLegalizeVectorTypes.cpp80 case ISD::FABS:
873 case ISD::FABS:
2804 case ISD::FABS:
H A DLegalizeVectorOps.cpp411 case ISD::FABS:
H A DSelectionDAG.cpp4118 case ISD::FABS:
4457 case ISD::FABS:
4525 case ISD::FABS:
4752 case ISD::FABS:
4754 return getNode(ISD::FABS, DL, VT, Operand.getOperand(0));
H A DSelectionDAGBuilder.cpp6184 case Intrinsic::fabs: Opcode = ISD::FABS; break;
7642 if (visitUnaryFloatCall(I, ISD::FABS))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp999 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) ||
1013 assert(Op0.getOpcode() == ISD::FABS);
1047 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) ||
1058 assert(Op0.getOpcode() == ISD::FABS);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp573 ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM}) {
2103 SDValue AbsA = DAG.getNode(ISD::FABS, SL, VT, A);
2144 SDValue AbsA = DAG.getNode(ISD::FABS, SL, VT, A);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp362 setOperationAction(ISD::FABS, MVT::f32, Custom);
363 setOperationAction(ISD::FABS, MVT::f64, Custom);
1233 case ISD::FABS: return lowerFABS(Op, DAG);
H A DMipsSEISelLowering.cpp139 setOperationAction(ISD::FABS, MVT::f16, Promote);
387 setOperationAction(ISD::FABS, Ty, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp258 setOperationAction(ISD::FABS, MVT::f128, Expand);
444 setOperationAction(ISD::FABS, MVT::f16, Promote);
467 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
483 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
705 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp668 setOperationAction(ISD::FABS, VT, Expand);
900 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
901 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
1021 setOperationAction(ISD::FABS , MVT::v4f64, Legal);
1066 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp503 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
535 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1482 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp522 // Use ANDPD to simulate FABS.
523 setOperationAction(ISD::FABS, VT, Custom);
552 // Use ANDPS to simulate FABS.
553 setOperationAction(ISD::FABS , MVT::f32, Custom);
699 setOperationAction(ISD::FABS, MVT::f128, Custom);
843 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
899 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
1174 setOperationAction(ISD::FABS, VT, Custom);
1461 setOperationAction(ISD::FABS, VT, Custom);
20416 /// The only differences between FABS an
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