/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/Utils/ |
H A D | X86ShuffleDecode.h | 150 void DecodeEXTRQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx, 154 void DecodeINSERTQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx,
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H A D | X86ShuffleDecode.cpp | 415 void DecodeEXTRQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx, 425 if (0 != (Len % EltSize) || 0 != (Idx % EltSize)) 439 Len /= EltSize; 440 Idx /= EltSize; 452 void DecodeINSERTQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx, 462 if (0 != (Len % EltSize) || 0 != (Idx % EltSize)) 476 Len /= EltSize; 477 Idx /= EltSize; [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SILoadStoreOptimizer.cpp | 118 unsigned EltSize; member in struct:__anon2119::SILoadStoreOptimizer::CombineInfo 224 unsigned read2Opcode(unsigned EltSize) const; 225 unsigned read2ST64Opcode(unsigned EltSize) const; 228 unsigned write2Opcode(unsigned EltSize) const; 229 unsigned write2ST64Opcode(unsigned EltSize) const; 479 EltSize = 484 EltSize = 489 EltSize = AMDGPU::getSMRDEncodedOffset(STM, 4); 492 EltSize = 4; 732 if ((CI.Offset % CI.EltSize ! [all...] |
H A D | SIRegisterInfo.cpp | 636 const unsigned EltSize = 4; local 638 unsigned NumSubRegs = AMDGPU::getRegBitWidth(RC->getID()) / (EltSize * CHAR_BIT); 639 unsigned Size = NumSubRegs * EltSize; 650 assert((Offset % EltSize) == 0 && "unexpected VGPR spill offset"); 652 if (!isUInt<12>(Offset + Size - EltSize)) { 655 // We currently only support spilling VGPRs to EltSize boundaries, meaning 686 for (unsigned i = 0, e = NumSubRegs; i != e; ++i, Offset += EltSize) { 710 MachinePointerInfo PInfo = BasePtrInfo.getWithOffset(EltSize * i); 713 EltSize, MinAlign(Align, EltSize * 774 unsigned EltSize = 4; local 878 unsigned EltSize = 4; local [all...] |
H A D | AMDGPUTargetTransformInfo.cpp | 556 unsigned EltSize local 558 if (EltSize < 32) { 559 if (EltSize == 16 && Index == 0 && ST->has16BitInsts()) 951 unsigned EltSize local 953 if (EltSize < 32) {
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H A D | SIRegisterInfo.h | 234 unsigned EltSize) const;
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H A D | AMDGPULegalizerInfo.cpp | 102 const int EltSize = EltTy.getSizeInBits(); 105 assert(EltSize < 32); 107 const int NewNumElts = (32 * NextMul32 + EltSize - 1) / EltSize; 139 const int EltSize = Ty.getElementType().getSizeInBits(); 140 return EltSize == 32 || EltSize == 64 || 141 (EltSize == 16 && Ty.getNumElements() % 2 == 0) || 142 EltSize == 128 || EltSize [all...] |
H A D | SIInstrInfo.cpp | 301 unsigned EltSize; local 303 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16; 307 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8; 311 EltSize *= 64; 317 Offset = EltSize * Offset0; 688 unsigned EltSize = 4; local 694 EltSize = 8; 697 EltSize = 4; 711 ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RC, EltSize); 792 unsigned EltSize local [all...] |
H A D | AMDGPURegisterBankInfo.cpp | 1368 int EltSize = Ty.getScalarSizeInBits(); local 1372 if (EltSize != 32) 2672 unsigned EltSize = getSizeInBits(MI.getOperand(2).getReg(), MRI, *TRI); local 2675 OpdsMapping[2] = AMDGPU::getValueMapping(BankID, EltSize);
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/freebsd-11-stable/contrib/llvm-project/clang/lib/CodeGen/ |
H A D | CGBuilder.h | 202 CharUnits EltSize = local 208 Addr.getAlignment().alignmentAtOffset(Index * EltSize)); 220 CharUnits EltSize = CharUnits::fromQuantity(DL.getTypeAllocSize(ElTy)); local 224 Addr.getAlignment().alignmentAtOffset(Index * EltSize)); 235 CharUnits EltSize = local 240 Addr.getAlignment().alignmentAtOffset(Index * EltSize));
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H A D | CGNonTrivialStruct.cpp | 196 CharUnits EltSize = Ctx.getTypeSizeInChars(EltTy); local 198 llvm::to_string(EltSize.getQuantity()) + "n" + 385 CharUnits EltSize = Ctx.getTypeSizeInChars(EltQT); local 390 PHIs[I], StartAddrs[I].getAlignment().alignmentAtOffset(EltSize)); 401 NewAddrs[I] = getAddrWithOffset(NewAddrs[I], EltSize);
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H A D | CGDecl.cpp | 1694 CharUnits EltSize = getContext().getTypeSizeInChars(VlaSize.Type); local 1700 if (!EltSize.isOne()) 1701 SizeVal = Builder.CreateNUWMul(SizeVal, CGM.getSize(EltSize)); 1719 if (!EltSize.isOne()) 1720 SizeVal = Builder.CreateNUWMul(SizeVal, CGM.getSize(EltSize)); 1722 llvm::ConstantInt::get(IntPtrTy, EltSize.getQuantity()); 1730 CharUnits CurAlign = Loc.getAlignment().alignmentOfArrayElement(EltSize);
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H A D | TargetInfo.cpp | 2754 uint64_t EltSize = getContext().getTypeSize(AT->getElementType()); 2762 (Size != EltSize || Size > getNativeVectorSizeForAVXABI(AVXLevel))) 2765 for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) { 3044 unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType()); 3050 unsigned EltOffset = i*EltSize; 3132 unsigned EltSize = TD.getTypeAllocSize(EltTy); 3133 IROffset -= IROffset/EltSize*EltSize; 3221 unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy); 3222 unsigned EltOffset = IROffset/EltSize*EltSiz 9519 CharUnits EltSize = getContext().getTypeSizeInChars(EltTy); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | Loads.cpp | 203 APInt EltSize(DL.getIndexTypeSizeInBits(Ptr->getType()), 213 return isDereferenceableAndAlignedPointer(Ptr, Alignment, EltSize, DL, 225 if (Step->getAPInt() != EltSize) 234 const APInt AccessSize = TC * EltSize; 245 if (EltSize.urem(Alignment.value()) != 0)
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H A D | ConstantFolding.cpp | 433 uint64_t EltSize = DL.getTypeAllocSize(CS->getOperand(Index)->getType()); local 435 if (ByteOffset < EltSize && 464 uint64_t EltSize = DL.getTypeAllocSize(EltTy); local 465 uint64_t Index = ByteOffset / EltSize; 466 uint64_t Offset = ByteOffset - Index * EltSize; 478 uint64_t BytesWritten = EltSize - Offset; 479 assert(BytesWritten <= EltSize && "Not indexing into this element?");
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H A D | ModuleSummaryAnalysis.cpp | 520 uint64_t EltSize = DL.getTypeAllocSize(EltTy); local 523 StartingOffset + i * EltSize, M, Index, VTableFuncs); local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64InstructionSelector.cpp | 99 MachineInstr *emitScalarToVector(unsigned EltSize, 1566 unsigned EltSize = DstTy.getElementType().getSizeInBits(); local 1567 if (EltSize == 32) 1570 else if (EltSize == 64) 2779 unsigned EltSize, const TargetRegisterClass *DstRC, Register Scalar, 2793 switch (EltSize) { 2876 const unsigned EltSize) { 2879 switch (EltSize) { 2894 LLVM_DEBUG(dbgs() << "Elt size '" << EltSize << "' unsupported.\n"); 3208 getInsertVecEltOpInfo(const RegisterBank &RB, unsigned EltSize) { argument 2778 emitScalarToVector( unsigned EltSize, const TargetRegisterClass *DstRC, Register Scalar, MachineIRBuilder &MIRBuilder) const argument 2875 getLaneCopyOpcode(unsigned &CopyOpc, unsigned &ExtractSubReg, const unsigned EltSize) argument 3978 unsigned EltSize = EltTy.getSizeInBits(); local [all...] |
H A D | AArch64StackTagging.cpp | 258 uint32_t EltSize = DL->getTypeSizeInBits(EltTy); local 259 Type *NewTy = VectorType::get(IntegerType::get(Ctx, EltSize),
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H A D | AArch64ISelLowering.cpp | 977 unsigned EltSize = Size; local 994 ((InvertedImm << 1) | (InvertedImm >> (EltSize - 1) & 1)) & 997 bool Carry = NonDemandedBits & ~Sum & (1ULL << (EltSize - 1)); 1008 if (EltSize == 2) 1011 EltSize /= 2; 1012 Mask >>= EltSize; local 1013 uint64_t Hi = Imm >> EltSize, DemandedBitsHi = DemandedBits >> EltSize; 1027 while (EltSize < Size) { 1028 NewImm |= NewImm << EltSize; 2780 unsigned EltSize = VT.getScalarSizeInBits(); local 2807 unsigned EltSize = VT.getScalarSizeInBits() / 2; local 5199 unsigned EltSize = 8; local 8335 unsigned EltSize = VT.getScalarSizeInBits(); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | Analysis.cpp | 102 uint64_t EltSize = DL.getTypeAllocSize(EltTy); local 105 StartingOffset + i * EltSize); 142 uint64_t EltSize = DL.getTypeAllocSize(EltTy); local 145 StartingOffset + i * EltSize);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCTargetTransformInfo.cpp | 808 unsigned EltSize = Val->getScalarSizeInBits(); local 809 if (EltSize == 64) { 813 } else if (EltSize == 32) {
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H A D | PPCISelLowering.h | 367 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded 584 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 599 unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineLoadStoreAlloca.cpp | 727 auto EltSize = DL.getTypeAllocSize(ET); local 751 Offset += EltSize; 1254 auto EltSize = DL.getTypeAllocSize(AT->getElementType()); local 1282 Offset += EltSize;
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H A D | InstructionCombining.cpp | 1168 uint64_t EltSize = DL.getTypeAllocSize(AT->getElementType()); local 1169 assert(EltSize && "Cannot index into a zero-sized array"); 1170 NewIndices.push_back(ConstantInt::get(IndexTy,Offset/EltSize)); 1171 Offset %= EltSize;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | LegalizerHelper.cpp | 54 unsigned EltSize = OrigTy.getScalarSizeInBits(); local 55 if (LeftoverSize % EltSize != 0) 57 LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize); 150 unsigned EltSize = MainTy.getScalarSizeInBits(); local 151 if (LeftoverSize % EltSize != 0) 153 LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize); 2365 const unsigned EltSize = EltTy.getSizeInBits(); local 2370 if (BitsForNumParts != Size && BitsForNumParts + EltSize ! [all...] |