1202379Srdivacky//===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===// 2202379Srdivacky// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6202379Srdivacky// 7202379Srdivacky//===----------------------------------------------------------------------===// 8202379Srdivacky// 9202379Srdivacky// These classes wrap the information about a call or function 10202379Srdivacky// definition used to handle ABI compliancy. 11202379Srdivacky// 12202379Srdivacky//===----------------------------------------------------------------------===// 13202379Srdivacky 14202379Srdivacky#include "TargetInfo.h" 15202379Srdivacky#include "ABIInfo.h" 16327952Sdim#include "CGBlocks.h" 17251662Sdim#include "CGCXXABI.h" 18280031Sdim#include "CGValue.h" 19202379Srdivacky#include "CodeGenFunction.h" 20360784Sdim#include "clang/AST/Attr.h" 21202379Srdivacky#include "clang/AST/RecordLayout.h" 22344779Sdim#include "clang/Basic/CodeGenOptions.h" 23261991Sdim#include "clang/CodeGen/CGFunctionInfo.h" 24309124Sdim#include "clang/CodeGen/SwiftCallingConv.h" 25360784Sdim#include "llvm/ADT/SmallBitVector.h" 26280031Sdim#include "llvm/ADT/StringExtras.h" 27327952Sdim#include "llvm/ADT/StringSwitch.h" 28202379Srdivacky#include "llvm/ADT/Triple.h" 29327952Sdim#include "llvm/ADT/Twine.h" 30249423Sdim#include "llvm/IR/DataLayout.h" 31249423Sdim#include "llvm/IR/Type.h" 32202379Srdivacky#include "llvm/Support/raw_ostream.h" 33360784Sdim#include <algorithm> // std::sort 34276479Sdim 35202379Srdivackyusing namespace clang; 36202379Srdivackyusing namespace CodeGen; 37202379Srdivacky 38314564Sdim// Helper for coercing an aggregate argument or return value into an integer 39314564Sdim// array of the same size (including padding) and alignment. This alternate 40314564Sdim// coercion happens only for the RenderScript ABI and can be removed after 41314564Sdim// runtimes that rely on it are no longer supported. 42314564Sdim// 43314564Sdim// RenderScript assumes that the size of the argument / return value in the IR 44314564Sdim// is the same as the size of the corresponding qualified type. This helper 45314564Sdim// coerces the aggregate type into an array of the same size (including 46314564Sdim// padding). This coercion is used in lieu of expansion of struct members or 47314564Sdim// other canonical coercions that return a coerced-type of larger size. 48314564Sdim// 49314564Sdim// Ty - The argument / return value type 50314564Sdim// Context - The associated ASTContext 51314564Sdim// LLVMContext - The associated LLVMContext 52314564Sdimstatic ABIArgInfo coerceToIntArray(QualType Ty, 53314564Sdim ASTContext &Context, 54314564Sdim llvm::LLVMContext &LLVMContext) { 55314564Sdim // Alignment and Size are measured in bits. 56314564Sdim const uint64_t Size = Context.getTypeSize(Ty); 57314564Sdim const uint64_t Alignment = Context.getTypeAlign(Ty); 58314564Sdim llvm::Type *IntType = llvm::Type::getIntNTy(LLVMContext, Alignment); 59314564Sdim const uint64_t NumElements = (Size + Alignment - 1) / Alignment; 60314564Sdim return ABIArgInfo::getDirect(llvm::ArrayType::get(IntType, NumElements)); 61314564Sdim} 62314564Sdim 63208600Srdivackystatic void AssignToArrayRange(CodeGen::CGBuilderTy &Builder, 64208600Srdivacky llvm::Value *Array, 65208600Srdivacky llvm::Value *Value, 66208600Srdivacky unsigned FirstIndex, 67208600Srdivacky unsigned LastIndex) { 68208600Srdivacky // Alternatively, we could emit this as a loop in the source. 69208600Srdivacky for (unsigned I = FirstIndex; I <= LastIndex; ++I) { 70288943Sdim llvm::Value *Cell = 71288943Sdim Builder.CreateConstInBoundsGEP1_32(Builder.getInt8Ty(), Array, I); 72296417Sdim Builder.CreateAlignedStore(Value, Cell, CharUnits::One()); 73208600Srdivacky } 74208600Srdivacky} 75208600Srdivacky 76212904Sdimstatic bool isAggregateTypeForABI(QualType T) { 77249423Sdim return !CodeGenFunction::hasScalarEvaluationKind(T) || 78212904Sdim T->isMemberFunctionPointerType(); 79212904Sdim} 80212904Sdim 81296417SdimABIArgInfo 82296417SdimABIInfo::getNaturalAlignIndirect(QualType Ty, bool ByRef, bool Realign, 83296417Sdim llvm::Type *Padding) const { 84296417Sdim return ABIArgInfo::getIndirect(getContext().getTypeAlignInChars(Ty), 85296417Sdim ByRef, Realign, Padding); 86296417Sdim} 87296417Sdim 88296417SdimABIArgInfo 89296417SdimABIInfo::getNaturalAlignIndirectInReg(QualType Ty, bool Realign) const { 90296417Sdim return ABIArgInfo::getIndirectInReg(getContext().getTypeAlignInChars(Ty), 91296417Sdim /*ByRef*/ false, Realign); 92296417Sdim} 93296417Sdim 94296417SdimAddress ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr, 95296417Sdim QualType Ty) const { 96296417Sdim return Address::invalid(); 97296417Sdim} 98296417Sdim 99202379SrdivackyABIInfo::~ABIInfo() {} 100202379Srdivacky 101309124Sdim/// Does the given lowering require more than the given number of 102309124Sdim/// registers when expanded? 103309124Sdim/// 104309124Sdim/// This is intended to be the basis of a reasonable basic implementation 105309124Sdim/// of should{Pass,Return}IndirectlyForSwift. 106309124Sdim/// 107309124Sdim/// For most targets, a limit of four total registers is reasonable; this 108309124Sdim/// limits the amount of code required in order to move around the value 109309124Sdim/// in case it wasn't produced immediately prior to the call by the caller 110309124Sdim/// (or wasn't produced in exactly the right registers) or isn't used 111309124Sdim/// immediately within the callee. But some targets may need to further 112309124Sdim/// limit the register count due to an inability to support that many 113309124Sdim/// return registers. 114309124Sdimstatic bool occupiesMoreThan(CodeGenTypes &cgt, 115309124Sdim ArrayRef<llvm::Type*> scalarTypes, 116309124Sdim unsigned maxAllRegisters) { 117309124Sdim unsigned intCount = 0, fpCount = 0; 118309124Sdim for (llvm::Type *type : scalarTypes) { 119309124Sdim if (type->isPointerTy()) { 120309124Sdim intCount++; 121309124Sdim } else if (auto intTy = dyn_cast<llvm::IntegerType>(type)) { 122309124Sdim auto ptrWidth = cgt.getTarget().getPointerWidth(0); 123309124Sdim intCount += (intTy->getBitWidth() + ptrWidth - 1) / ptrWidth; 124309124Sdim } else { 125309124Sdim assert(type->isVectorTy() || type->isFloatingPointTy()); 126309124Sdim fpCount++; 127309124Sdim } 128309124Sdim } 129309124Sdim 130309124Sdim return (intCount + fpCount > maxAllRegisters); 131309124Sdim} 132309124Sdim 133309124Sdimbool SwiftABIInfo::isLegalVectorTypeForSwift(CharUnits vectorSize, 134309124Sdim llvm::Type *eltTy, 135309124Sdim unsigned numElts) const { 136309124Sdim // The default implementation of this assumes that the target guarantees 137309124Sdim // 128-bit SIMD support but nothing more. 138309124Sdim return (vectorSize.getQuantity() > 8 && vectorSize.getQuantity() <= 16); 139309124Sdim} 140309124Sdim 141251662Sdimstatic CGCXXABI::RecordArgABI getRecordArgABI(const RecordType *RT, 142261991Sdim CGCXXABI &CXXABI) { 143251662Sdim const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl()); 144341825Sdim if (!RD) { 145341825Sdim if (!RT->getDecl()->canPassInRegisters()) 146341825Sdim return CGCXXABI::RAA_Indirect; 147251662Sdim return CGCXXABI::RAA_Default; 148341825Sdim } 149261991Sdim return CXXABI.getRecordArgABI(RD); 150251662Sdim} 151251662Sdim 152251662Sdimstatic CGCXXABI::RecordArgABI getRecordArgABI(QualType T, 153261991Sdim CGCXXABI &CXXABI) { 154251662Sdim const RecordType *RT = T->getAs<RecordType>(); 155251662Sdim if (!RT) 156251662Sdim return CGCXXABI::RAA_Default; 157261991Sdim return getRecordArgABI(RT, CXXABI); 158251662Sdim} 159251662Sdim 160341825Sdimstatic bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI, 161341825Sdim const ABIInfo &Info) { 162341825Sdim QualType Ty = FI.getReturnType(); 163341825Sdim 164341825Sdim if (const auto *RT = Ty->getAs<RecordType>()) 165341825Sdim if (!isa<CXXRecordDecl>(RT->getDecl()) && 166341825Sdim !RT->getDecl()->canPassInRegisters()) { 167341825Sdim FI.getReturnInfo() = Info.getNaturalAlignIndirect(Ty); 168341825Sdim return true; 169341825Sdim } 170341825Sdim 171341825Sdim return CXXABI.classifyReturnType(FI); 172341825Sdim} 173341825Sdim 174280031Sdim/// Pass transparent unions as if they were the type of the first element. Sema 175280031Sdim/// should ensure that all elements of the union have the same "machine type". 176280031Sdimstatic QualType useFirstFieldIfTransparentUnion(QualType Ty) { 177280031Sdim if (const RecordType *UT = Ty->getAsUnionType()) { 178280031Sdim const RecordDecl *UD = UT->getDecl(); 179280031Sdim if (UD->hasAttr<TransparentUnionAttr>()) { 180280031Sdim assert(!UD->field_empty() && "sema created an empty transparent union"); 181280031Sdim return UD->field_begin()->getType(); 182280031Sdim } 183280031Sdim } 184280031Sdim return Ty; 185280031Sdim} 186280031Sdim 187261991SdimCGCXXABI &ABIInfo::getCXXABI() const { 188261991Sdim return CGT.getCXXABI(); 189261991Sdim} 190261991Sdim 191212904SdimASTContext &ABIInfo::getContext() const { 192212904Sdim return CGT.getContext(); 193212904Sdim} 194212904Sdim 195212904Sdimllvm::LLVMContext &ABIInfo::getVMContext() const { 196212904Sdim return CGT.getLLVMContext(); 197212904Sdim} 198212904Sdim 199243830Sdimconst llvm::DataLayout &ABIInfo::getDataLayout() const { 200243830Sdim return CGT.getDataLayout(); 201212904Sdim} 202212904Sdim 203251662Sdimconst TargetInfo &ABIInfo::getTarget() const { 204251662Sdim return CGT.getTarget(); 205251662Sdim} 206212904Sdim 207323112Sdimconst CodeGenOptions &ABIInfo::getCodeGenOpts() const { 208323112Sdim return CGT.getCodeGenOpts(); 209323112Sdim} 210309124Sdim 211323112Sdimbool ABIInfo::isAndroid() const { return getTarget().getTriple().isAndroid(); } 212323112Sdim 213280031Sdimbool ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const { 214280031Sdim return false; 215280031Sdim} 216280031Sdim 217280031Sdimbool ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base, 218280031Sdim uint64_t Members) const { 219280031Sdim return false; 220280031Sdim} 221280031Sdim 222309124SdimLLVM_DUMP_METHOD void ABIArgInfo::dump() const { 223226633Sdim raw_ostream &OS = llvm::errs(); 224202379Srdivacky OS << "(ABIArgInfo Kind="; 225202379Srdivacky switch (TheKind) { 226202379Srdivacky case Direct: 227212904Sdim OS << "Direct Type="; 228226633Sdim if (llvm::Type *Ty = getCoerceToType()) 229212904Sdim Ty->print(OS); 230212904Sdim else 231212904Sdim OS << "null"; 232202379Srdivacky break; 233202379Srdivacky case Extend: 234202379Srdivacky OS << "Extend"; 235202379Srdivacky break; 236202379Srdivacky case Ignore: 237202379Srdivacky OS << "Ignore"; 238202379Srdivacky break; 239276479Sdim case InAlloca: 240276479Sdim OS << "InAlloca Offset=" << getInAllocaFieldIndex(); 241276479Sdim break; 242202379Srdivacky case Indirect: 243296417Sdim OS << "Indirect Align=" << getIndirectAlign().getQuantity() 244224145Sdim << " ByVal=" << getIndirectByVal() 245218893Sdim << " Realign=" << getIndirectRealign(); 246202379Srdivacky break; 247202379Srdivacky case Expand: 248202379Srdivacky OS << "Expand"; 249202379Srdivacky break; 250309124Sdim case CoerceAndExpand: 251309124Sdim OS << "CoerceAndExpand Type="; 252309124Sdim getCoerceAndExpandType()->print(OS); 253309124Sdim break; 254202379Srdivacky } 255202379Srdivacky OS << ")\n"; 256202379Srdivacky} 257202379Srdivacky 258296417Sdim// Dynamically round a pointer up to a multiple of the given alignment. 259296417Sdimstatic llvm::Value *emitRoundPointerUpToAlignment(CodeGenFunction &CGF, 260296417Sdim llvm::Value *Ptr, 261296417Sdim CharUnits Align) { 262296417Sdim llvm::Value *PtrAsInt = Ptr; 263296417Sdim // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align; 264296417Sdim PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy); 265296417Sdim PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt, 266296417Sdim llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1)); 267296417Sdim PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt, 268296417Sdim llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity())); 269296417Sdim PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt, 270296417Sdim Ptr->getType(), 271296417Sdim Ptr->getName() + ".aligned"); 272296417Sdim return PtrAsInt; 273296417Sdim} 274296417Sdim 275296417Sdim/// Emit va_arg for a platform using the common void* representation, 276296417Sdim/// where arguments are simply emitted in an array of slots on the stack. 277296417Sdim/// 278296417Sdim/// This version implements the core direct-value passing rules. 279296417Sdim/// 280296417Sdim/// \param SlotSize - The size and alignment of a stack slot. 281296417Sdim/// Each argument will be allocated to a multiple of this number of 282296417Sdim/// slots, and all the slots will be aligned to this value. 283296417Sdim/// \param AllowHigherAlign - The slot alignment is not a cap; 284296417Sdim/// an argument type with an alignment greater than the slot size 285296417Sdim/// will be emitted on a higher-alignment address, potentially 286296417Sdim/// leaving one or more empty slots behind as padding. If this 287296417Sdim/// is false, the returned address might be less-aligned than 288296417Sdim/// DirectAlign. 289296417Sdimstatic Address emitVoidPtrDirectVAArg(CodeGenFunction &CGF, 290296417Sdim Address VAListAddr, 291296417Sdim llvm::Type *DirectTy, 292296417Sdim CharUnits DirectSize, 293296417Sdim CharUnits DirectAlign, 294296417Sdim CharUnits SlotSize, 295296417Sdim bool AllowHigherAlign) { 296296417Sdim // Cast the element type to i8* if necessary. Some platforms define 297296417Sdim // va_list as a struct containing an i8* instead of just an i8*. 298296417Sdim if (VAListAddr.getElementType() != CGF.Int8PtrTy) 299296417Sdim VAListAddr = CGF.Builder.CreateElementBitCast(VAListAddr, CGF.Int8PtrTy); 300296417Sdim 301296417Sdim llvm::Value *Ptr = CGF.Builder.CreateLoad(VAListAddr, "argp.cur"); 302296417Sdim 303296417Sdim // If the CC aligns values higher than the slot size, do so if needed. 304296417Sdim Address Addr = Address::invalid(); 305296417Sdim if (AllowHigherAlign && DirectAlign > SlotSize) { 306296417Sdim Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign), 307296417Sdim DirectAlign); 308296417Sdim } else { 309341825Sdim Addr = Address(Ptr, SlotSize); 310296417Sdim } 311296417Sdim 312296417Sdim // Advance the pointer past the argument, then store that back. 313309124Sdim CharUnits FullDirectSize = DirectSize.alignTo(SlotSize); 314353358Sdim Address NextPtr = 315353358Sdim CGF.Builder.CreateConstInBoundsByteGEP(Addr, FullDirectSize, "argp.next"); 316353358Sdim CGF.Builder.CreateStore(NextPtr.getPointer(), VAListAddr); 317296417Sdim 318296417Sdim // If the argument is smaller than a slot, and this is a big-endian 319296417Sdim // target, the argument will be right-adjusted in its slot. 320309124Sdim if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian() && 321309124Sdim !DirectTy->isStructTy()) { 322296417Sdim Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize); 323296417Sdim } 324296417Sdim 325296417Sdim Addr = CGF.Builder.CreateElementBitCast(Addr, DirectTy); 326296417Sdim return Addr; 327296417Sdim} 328296417Sdim 329296417Sdim/// Emit va_arg for a platform using the common void* representation, 330296417Sdim/// where arguments are simply emitted in an array of slots on the stack. 331296417Sdim/// 332296417Sdim/// \param IsIndirect - Values of this type are passed indirectly. 333296417Sdim/// \param ValueInfo - The size and alignment of this type, generally 334296417Sdim/// computed with getContext().getTypeInfoInChars(ValueTy). 335296417Sdim/// \param SlotSizeAndAlign - The size and alignment of a stack slot. 336296417Sdim/// Each argument will be allocated to a multiple of this number of 337296417Sdim/// slots, and all the slots will be aligned to this value. 338296417Sdim/// \param AllowHigherAlign - The slot alignment is not a cap; 339296417Sdim/// an argument type with an alignment greater than the slot size 340296417Sdim/// will be emitted on a higher-alignment address, potentially 341296417Sdim/// leaving one or more empty slots behind as padding. 342296417Sdimstatic Address emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr, 343296417Sdim QualType ValueTy, bool IsIndirect, 344296417Sdim std::pair<CharUnits, CharUnits> ValueInfo, 345296417Sdim CharUnits SlotSizeAndAlign, 346296417Sdim bool AllowHigherAlign) { 347296417Sdim // The size and alignment of the value that was passed directly. 348296417Sdim CharUnits DirectSize, DirectAlign; 349296417Sdim if (IsIndirect) { 350296417Sdim DirectSize = CGF.getPointerSize(); 351296417Sdim DirectAlign = CGF.getPointerAlign(); 352296417Sdim } else { 353296417Sdim DirectSize = ValueInfo.first; 354296417Sdim DirectAlign = ValueInfo.second; 355296417Sdim } 356296417Sdim 357296417Sdim // Cast the address we've calculated to the right type. 358296417Sdim llvm::Type *DirectTy = CGF.ConvertTypeForMem(ValueTy); 359296417Sdim if (IsIndirect) 360296417Sdim DirectTy = DirectTy->getPointerTo(0); 361296417Sdim 362296417Sdim Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy, 363296417Sdim DirectSize, DirectAlign, 364296417Sdim SlotSizeAndAlign, 365296417Sdim AllowHigherAlign); 366296417Sdim 367296417Sdim if (IsIndirect) { 368296417Sdim Addr = Address(CGF.Builder.CreateLoad(Addr), ValueInfo.second); 369296417Sdim } 370296417Sdim 371296417Sdim return Addr; 372341825Sdim 373296417Sdim} 374296417Sdim 375296417Sdimstatic Address emitMergePHI(CodeGenFunction &CGF, 376296417Sdim Address Addr1, llvm::BasicBlock *Block1, 377296417Sdim Address Addr2, llvm::BasicBlock *Block2, 378296417Sdim const llvm::Twine &Name = "") { 379296417Sdim assert(Addr1.getType() == Addr2.getType()); 380296417Sdim llvm::PHINode *PHI = CGF.Builder.CreatePHI(Addr1.getType(), 2, Name); 381296417Sdim PHI->addIncoming(Addr1.getPointer(), Block1); 382296417Sdim PHI->addIncoming(Addr2.getPointer(), Block2); 383296417Sdim CharUnits Align = std::min(Addr1.getAlignment(), Addr2.getAlignment()); 384296417Sdim return Address(PHI, Align); 385296417Sdim} 386296417Sdim 387202379SrdivackyTargetCodeGenInfo::~TargetCodeGenInfo() { delete Info; } 388202379Srdivacky 389226633Sdim// If someone can figure out a general rule for this, that would be great. 390226633Sdim// It's probably just doomed to be platform-dependent, though. 391226633Sdimunsigned TargetCodeGenInfo::getSizeOfUnwindException() const { 392226633Sdim // Verified for: 393226633Sdim // x86-64 FreeBSD, Linux, Darwin 394226633Sdim // x86-32 FreeBSD, Linux, Darwin 395226633Sdim // PowerPC Linux, Darwin 396226633Sdim // ARM Darwin (*not* EABI) 397249423Sdim // AArch64 Linux 398226633Sdim return 32; 399226633Sdim} 400226633Sdim 401234353Sdimbool TargetCodeGenInfo::isNoProtoCallVariadic(const CallArgList &args, 402234353Sdim const FunctionNoProtoType *fnType) const { 403226633Sdim // The following conventions are known to require this to be false: 404226633Sdim // x86_stdcall 405226633Sdim // MIPS 406226633Sdim // For everything else, we just prefer false unless we opt out. 407226633Sdim return false; 408226633Sdim} 409226633Sdim 410261991Sdimvoid 411261991SdimTargetCodeGenInfo::getDependentLibraryOption(llvm::StringRef Lib, 412261991Sdim llvm::SmallString<24> &Opt) const { 413261991Sdim // This assumes the user is passing a library name like "rt" instead of a 414261991Sdim // filename like "librt.a/so", and that they don't care whether it's static or 415261991Sdim // dynamic. 416261991Sdim Opt = "-l"; 417261991Sdim Opt += Lib; 418261991Sdim} 419261991Sdim 420309124Sdimunsigned TargetCodeGenInfo::getOpenCLKernelCallingConv() const { 421321369Sdim // OpenCL kernels are called via an explicit runtime API with arguments 422321369Sdim // set with clSetKernelArg(), not as normal sub-functions. 423321369Sdim // Return SPIR_KERNEL by default as the kernel calling convention to 424321369Sdim // ensure the fingerprint is fixed such way that each OpenCL argument 425321369Sdim // gets one matching argument in the produced kernel function argument 426321369Sdim // list to enable feasible implementation of clSetKernelArg() with 427321369Sdim // aggregates etc. In case we would use the default C calling conv here, 428321369Sdim // clSetKernelArg() might break depending on the target-specific 429321369Sdim // conventions; different targets might split structs passed as values 430321369Sdim // to multiple function arguments etc. 431321369Sdim return llvm::CallingConv::SPIR_KERNEL; 432309124Sdim} 433314564Sdim 434314564Sdimllvm::Constant *TargetCodeGenInfo::getNullPointer(const CodeGen::CodeGenModule &CGM, 435314564Sdim llvm::PointerType *T, QualType QT) const { 436314564Sdim return llvm::ConstantPointerNull::get(T); 437314564Sdim} 438314564Sdim 439327952SdimLangAS TargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM, 440327952Sdim const VarDecl *D) const { 441321369Sdim assert(!CGM.getLangOpts().OpenCL && 442321369Sdim !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) && 443321369Sdim "Address space agnostic languages only"); 444327952Sdim return D ? D->getType().getAddressSpace() : LangAS::Default; 445321369Sdim} 446321369Sdim 447314564Sdimllvm::Value *TargetCodeGenInfo::performAddrSpaceCast( 448327952Sdim CodeGen::CodeGenFunction &CGF, llvm::Value *Src, LangAS SrcAddr, 449327952Sdim LangAS DestAddr, llvm::Type *DestTy, bool isNonNull) const { 450314564Sdim // Since target may map different address spaces in AST to the same address 451314564Sdim // space, an address space conversion may end up as a bitcast. 452321369Sdim if (auto *C = dyn_cast<llvm::Constant>(Src)) 453321369Sdim return performAddrSpaceCast(CGF.CGM, C, SrcAddr, DestAddr, DestTy); 454353358Sdim // Try to preserve the source's name to make IR more readable. 455353358Sdim return CGF.Builder.CreatePointerBitCastOrAddrSpaceCast( 456353358Sdim Src, DestTy, Src->hasName() ? Src->getName() + ".ascast" : ""); 457314564Sdim} 458314564Sdim 459321369Sdimllvm::Constant * 460321369SdimTargetCodeGenInfo::performAddrSpaceCast(CodeGenModule &CGM, llvm::Constant *Src, 461327952Sdim LangAS SrcAddr, LangAS DestAddr, 462321369Sdim llvm::Type *DestTy) const { 463321369Sdim // Since target may map different address spaces in AST to the same address 464321369Sdim // space, an address space conversion may end up as a bitcast. 465321369Sdim return llvm::ConstantExpr::getPointerCast(Src, DestTy); 466321369Sdim} 467321369Sdim 468327952Sdimllvm::SyncScope::ID 469353358SdimTargetCodeGenInfo::getLLVMSyncScopeID(const LangOptions &LangOpts, 470353358Sdim SyncScope Scope, 471353358Sdim llvm::AtomicOrdering Ordering, 472353358Sdim llvm::LLVMContext &Ctx) const { 473353358Sdim return Ctx.getOrInsertSyncScopeID(""); /* default sync scope */ 474327952Sdim} 475327952Sdim 476202379Srdivackystatic bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays); 477202379Srdivacky 478202379Srdivacky/// isEmptyField - Return true iff a the field is "empty", that is it 479202379Srdivacky/// is an unnamed bit-field or an (array of) empty record(s). 480202379Srdivackystatic bool isEmptyField(ASTContext &Context, const FieldDecl *FD, 481202379Srdivacky bool AllowArrays) { 482202379Srdivacky if (FD->isUnnamedBitfield()) 483202379Srdivacky return true; 484202379Srdivacky 485202379Srdivacky QualType FT = FD->getType(); 486202379Srdivacky 487234353Sdim // Constant arrays of empty records count as empty, strip them off. 488234353Sdim // Constant arrays of zero length always count as empty. 489202379Srdivacky if (AllowArrays) 490234353Sdim while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) { 491234353Sdim if (AT->getSize() == 0) 492234353Sdim return true; 493202379Srdivacky FT = AT->getElementType(); 494234353Sdim } 495202379Srdivacky 496208600Srdivacky const RecordType *RT = FT->getAs<RecordType>(); 497208600Srdivacky if (!RT) 498208600Srdivacky return false; 499208600Srdivacky 500208600Srdivacky // C++ record fields are never empty, at least in the Itanium ABI. 501208600Srdivacky // 502208600Srdivacky // FIXME: We should use a predicate for whether this behavior is true in the 503208600Srdivacky // current ABI. 504208600Srdivacky if (isa<CXXRecordDecl>(RT->getDecl())) 505208600Srdivacky return false; 506208600Srdivacky 507202379Srdivacky return isEmptyRecord(Context, FT, AllowArrays); 508202379Srdivacky} 509202379Srdivacky 510202379Srdivacky/// isEmptyRecord - Return true iff a structure contains only empty 511202379Srdivacky/// fields. Note that a structure with a flexible array member is not 512202379Srdivacky/// considered empty. 513202379Srdivackystatic bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) { 514202379Srdivacky const RecordType *RT = T->getAs<RecordType>(); 515202379Srdivacky if (!RT) 516309124Sdim return false; 517202379Srdivacky const RecordDecl *RD = RT->getDecl(); 518202379Srdivacky if (RD->hasFlexibleArrayMember()) 519202379Srdivacky return false; 520208600Srdivacky 521208600Srdivacky // If this is a C++ record, check the bases first. 522208600Srdivacky if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) 523276479Sdim for (const auto &I : CXXRD->bases()) 524276479Sdim if (!isEmptyRecord(Context, I.getType(), true)) 525208600Srdivacky return false; 526208600Srdivacky 527276479Sdim for (const auto *I : RD->fields()) 528276479Sdim if (!isEmptyField(Context, I, AllowArrays)) 529202379Srdivacky return false; 530202379Srdivacky return true; 531202379Srdivacky} 532202379Srdivacky 533202379Srdivacky/// isSingleElementStruct - Determine if a structure is a "single 534202379Srdivacky/// element struct", i.e. it has exactly one non-empty field or 535202379Srdivacky/// exactly one field which is itself a single element 536202379Srdivacky/// struct. Structures with flexible array members are never 537202379Srdivacky/// considered single element structs. 538202379Srdivacky/// 539202379Srdivacky/// \return The field declaration for the single non-empty field, if 540202379Srdivacky/// it exists. 541202379Srdivackystatic const Type *isSingleElementStruct(QualType T, ASTContext &Context) { 542288943Sdim const RecordType *RT = T->getAs<RecordType>(); 543202379Srdivacky if (!RT) 544276479Sdim return nullptr; 545202379Srdivacky 546202379Srdivacky const RecordDecl *RD = RT->getDecl(); 547202379Srdivacky if (RD->hasFlexibleArrayMember()) 548276479Sdim return nullptr; 549202379Srdivacky 550276479Sdim const Type *Found = nullptr; 551212904Sdim 552208600Srdivacky // If this is a C++ record, check the bases first. 553208600Srdivacky if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) { 554276479Sdim for (const auto &I : CXXRD->bases()) { 555208600Srdivacky // Ignore empty records. 556276479Sdim if (isEmptyRecord(Context, I.getType(), true)) 557208600Srdivacky continue; 558208600Srdivacky 559208600Srdivacky // If we already found an element then this isn't a single-element struct. 560208600Srdivacky if (Found) 561276479Sdim return nullptr; 562208600Srdivacky 563208600Srdivacky // If this is non-empty and not a single element struct, the composite 564208600Srdivacky // cannot be a single element struct. 565276479Sdim Found = isSingleElementStruct(I.getType(), Context); 566208600Srdivacky if (!Found) 567276479Sdim return nullptr; 568208600Srdivacky } 569208600Srdivacky } 570208600Srdivacky 571208600Srdivacky // Check for single element. 572276479Sdim for (const auto *FD : RD->fields()) { 573202379Srdivacky QualType FT = FD->getType(); 574202379Srdivacky 575202379Srdivacky // Ignore empty fields. 576202379Srdivacky if (isEmptyField(Context, FD, true)) 577202379Srdivacky continue; 578202379Srdivacky 579202379Srdivacky // If we already found an element then this isn't a single-element 580202379Srdivacky // struct. 581202379Srdivacky if (Found) 582276479Sdim return nullptr; 583202379Srdivacky 584202379Srdivacky // Treat single element arrays as the element. 585202379Srdivacky while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) { 586202379Srdivacky if (AT->getSize().getZExtValue() != 1) 587202379Srdivacky break; 588202379Srdivacky FT = AT->getElementType(); 589202379Srdivacky } 590202379Srdivacky 591212904Sdim if (!isAggregateTypeForABI(FT)) { 592202379Srdivacky Found = FT.getTypePtr(); 593202379Srdivacky } else { 594202379Srdivacky Found = isSingleElementStruct(FT, Context); 595202379Srdivacky if (!Found) 596276479Sdim return nullptr; 597202379Srdivacky } 598202379Srdivacky } 599202379Srdivacky 600234353Sdim // We don't consider a struct a single-element struct if it has 601234353Sdim // padding beyond the element type. 602234353Sdim if (Found && Context.getTypeSize(Found) != Context.getTypeSize(T)) 603276479Sdim return nullptr; 604234353Sdim 605202379Srdivacky return Found; 606202379Srdivacky} 607202379Srdivacky 608309124Sdimnamespace { 609309124SdimAddress EmitVAArgInstr(CodeGenFunction &CGF, Address VAListAddr, QualType Ty, 610309124Sdim const ABIArgInfo &AI) { 611309124Sdim // This default implementation defers to the llvm backend's va_arg 612309124Sdim // instruction. It can handle only passing arguments directly 613309124Sdim // (typically only handled in the backend for primitive types), or 614309124Sdim // aggregates passed indirectly by pointer (NOTE: if the "byval" 615309124Sdim // flag has ABI impact in the callee, this implementation cannot 616309124Sdim // work.) 617249423Sdim 618309124Sdim // Only a few cases are covered here at the moment -- those needed 619309124Sdim // by the default abi. 620309124Sdim llvm::Value *Val; 621202379Srdivacky 622309124Sdim if (AI.isIndirect()) { 623309124Sdim assert(!AI.getPaddingType() && 624309124Sdim "Unexpected PaddingType seen in arginfo in generic VAArg emitter!"); 625309124Sdim assert( 626309124Sdim !AI.getIndirectRealign() && 627309124Sdim "Unexpected IndirectRealign seen in arginfo in generic VAArg emitter!"); 628202379Srdivacky 629309124Sdim auto TyInfo = CGF.getContext().getTypeInfoInChars(Ty); 630309124Sdim CharUnits TyAlignForABI = TyInfo.second; 631202379Srdivacky 632309124Sdim llvm::Type *BaseTy = 633309124Sdim llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty)); 634309124Sdim llvm::Value *Addr = 635309124Sdim CGF.Builder.CreateVAArg(VAListAddr.getPointer(), BaseTy); 636309124Sdim return Address(Addr, TyAlignForABI); 637309124Sdim } else { 638309124Sdim assert((AI.isDirect() || AI.isExtend()) && 639309124Sdim "Unexpected ArgInfo Kind in generic VAArg emitter!"); 640202379Srdivacky 641309124Sdim assert(!AI.getInReg() && 642309124Sdim "Unexpected InReg seen in arginfo in generic VAArg emitter!"); 643309124Sdim assert(!AI.getPaddingType() && 644309124Sdim "Unexpected PaddingType seen in arginfo in generic VAArg emitter!"); 645309124Sdim assert(!AI.getDirectOffset() && 646309124Sdim "Unexpected DirectOffset seen in arginfo in generic VAArg emitter!"); 647309124Sdim assert(!AI.getCoerceToType() && 648309124Sdim "Unexpected CoerceToType seen in arginfo in generic VAArg emitter!"); 649288943Sdim 650309124Sdim Address Temp = CGF.CreateMemTemp(Ty, "varet"); 651309124Sdim Val = CGF.Builder.CreateVAArg(VAListAddr.getPointer(), CGF.ConvertType(Ty)); 652309124Sdim CGF.Builder.CreateStore(Val, Temp); 653309124Sdim return Temp; 654202379Srdivacky } 655202379Srdivacky} 656202379Srdivacky 657202379Srdivacky/// DefaultABIInfo - The default implementation for ABI specific 658202379Srdivacky/// details. This implementation provides information which results in 659202379Srdivacky/// self-consistent and sensible LLVM IR generation, but does not 660202379Srdivacky/// conform to any particular ABI. 661202379Srdivackyclass DefaultABIInfo : public ABIInfo { 662212904Sdimpublic: 663212904Sdim DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {} 664202379Srdivacky 665212904Sdim ABIArgInfo classifyReturnType(QualType RetTy) const; 666212904Sdim ABIArgInfo classifyArgumentType(QualType RetTy) const; 667202379Srdivacky 668276479Sdim void computeInfo(CGFunctionInfo &FI) const override { 669276479Sdim if (!getCXXABI().classifyReturnType(FI)) 670276479Sdim FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 671276479Sdim for (auto &I : FI.arguments()) 672276479Sdim I.info = classifyArgumentType(I.type); 673202379Srdivacky } 674202379Srdivacky 675296417Sdim Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 676309124Sdim QualType Ty) const override { 677309124Sdim return EmitVAArgInstr(CGF, VAListAddr, Ty, classifyArgumentType(Ty)); 678309124Sdim } 679202379Srdivacky}; 680202379Srdivacky 681202379Srdivackyclass DefaultTargetCodeGenInfo : public TargetCodeGenInfo { 682202379Srdivackypublic: 683212904Sdim DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT) 684212904Sdim : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {} 685202379Srdivacky}; 686202379Srdivacky 687212904SdimABIArgInfo DefaultABIInfo::classifyArgumentType(QualType Ty) const { 688288943Sdim Ty = useFirstFieldIfTransparentUnion(Ty); 689288943Sdim 690288943Sdim if (isAggregateTypeForABI(Ty)) { 691288943Sdim // Records with non-trivial destructors/copy-constructors should not be 692288943Sdim // passed by value. 693288943Sdim if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) 694296417Sdim return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory); 695288943Sdim 696296417Sdim return getNaturalAlignIndirect(Ty); 697288943Sdim } 698207619Srdivacky 699205219Srdivacky // Treat an enum type as its underlying type. 700205219Srdivacky if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 701205219Srdivacky Ty = EnumTy->getDecl()->getIntegerType(); 702203955Srdivacky 703341825Sdim return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty) 704341825Sdim : ABIArgInfo::getDirect()); 705202379Srdivacky} 706202379Srdivacky 707218893SdimABIArgInfo DefaultABIInfo::classifyReturnType(QualType RetTy) const { 708218893Sdim if (RetTy->isVoidType()) 709218893Sdim return ABIArgInfo::getIgnore(); 710218893Sdim 711218893Sdim if (isAggregateTypeForABI(RetTy)) 712296417Sdim return getNaturalAlignIndirect(RetTy); 713218893Sdim 714218893Sdim // Treat an enum type as its underlying type. 715218893Sdim if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 716218893Sdim RetTy = EnumTy->getDecl()->getIntegerType(); 717218893Sdim 718341825Sdim return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy) 719341825Sdim : ABIArgInfo::getDirect()); 720218893Sdim} 721218893Sdim 722243830Sdim//===----------------------------------------------------------------------===// 723296417Sdim// WebAssembly ABI Implementation 724296417Sdim// 725296417Sdim// This is a very simple ABI that relies a lot on DefaultABIInfo. 726296417Sdim//===----------------------------------------------------------------------===// 727296417Sdim 728344779Sdimclass WebAssemblyABIInfo final : public SwiftABIInfo { 729344779Sdim DefaultABIInfo defaultInfo; 730344779Sdim 731296417Sdimpublic: 732296417Sdim explicit WebAssemblyABIInfo(CodeGen::CodeGenTypes &CGT) 733344779Sdim : SwiftABIInfo(CGT), defaultInfo(CGT) {} 734296417Sdim 735296417Sdimprivate: 736296417Sdim ABIArgInfo classifyReturnType(QualType RetTy) const; 737296417Sdim ABIArgInfo classifyArgumentType(QualType Ty) const; 738296417Sdim 739296417Sdim // DefaultABIInfo's classifyReturnType and classifyArgumentType are 740309124Sdim // non-virtual, but computeInfo and EmitVAArg are virtual, so we 741309124Sdim // overload them. 742296417Sdim void computeInfo(CGFunctionInfo &FI) const override { 743296417Sdim if (!getCXXABI().classifyReturnType(FI)) 744296417Sdim FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 745296417Sdim for (auto &Arg : FI.arguments()) 746296417Sdim Arg.info = classifyArgumentType(Arg.type); 747296417Sdim } 748309124Sdim 749309124Sdim Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 750309124Sdim QualType Ty) const override; 751344779Sdim 752344779Sdim bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars, 753344779Sdim bool asReturnValue) const override { 754344779Sdim return occupiesMoreThan(CGT, scalars, /*total*/ 4); 755344779Sdim } 756344779Sdim 757344779Sdim bool isSwiftErrorInRegister() const override { 758344779Sdim return false; 759344779Sdim } 760296417Sdim}; 761296417Sdim 762296417Sdimclass WebAssemblyTargetCodeGenInfo final : public TargetCodeGenInfo { 763296417Sdimpublic: 764296417Sdim explicit WebAssemblyTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT) 765296417Sdim : TargetCodeGenInfo(new WebAssemblyABIInfo(CGT)) {} 766341825Sdim 767341825Sdim void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 768341825Sdim CodeGen::CodeGenModule &CGM) const override { 769344779Sdim TargetCodeGenInfo::setTargetAttributes(D, GV, CGM); 770344779Sdim if (const auto *FD = dyn_cast_or_null<FunctionDecl>(D)) { 771344779Sdim if (const auto *Attr = FD->getAttr<WebAssemblyImportModuleAttr>()) { 772344779Sdim llvm::Function *Fn = cast<llvm::Function>(GV); 773344779Sdim llvm::AttrBuilder B; 774344779Sdim B.addAttribute("wasm-import-module", Attr->getImportModule()); 775344779Sdim Fn->addAttributes(llvm::AttributeList::FunctionIndex, B); 776344779Sdim } 777344779Sdim if (const auto *Attr = FD->getAttr<WebAssemblyImportNameAttr>()) { 778344779Sdim llvm::Function *Fn = cast<llvm::Function>(GV); 779344779Sdim llvm::AttrBuilder B; 780344779Sdim B.addAttribute("wasm-import-name", Attr->getImportName()); 781344779Sdim Fn->addAttributes(llvm::AttributeList::FunctionIndex, B); 782344779Sdim } 783360784Sdim if (const auto *Attr = FD->getAttr<WebAssemblyExportNameAttr>()) { 784360784Sdim llvm::Function *Fn = cast<llvm::Function>(GV); 785360784Sdim llvm::AttrBuilder B; 786360784Sdim B.addAttribute("wasm-export-name", Attr->getExportName()); 787360784Sdim Fn->addAttributes(llvm::AttributeList::FunctionIndex, B); 788360784Sdim } 789344779Sdim } 790344779Sdim 791341825Sdim if (auto *FD = dyn_cast_or_null<FunctionDecl>(D)) { 792341825Sdim llvm::Function *Fn = cast<llvm::Function>(GV); 793341825Sdim if (!FD->doesThisDeclarationHaveABody() && !FD->hasPrototype()) 794341825Sdim Fn->addFnAttr("no-prototype"); 795341825Sdim } 796341825Sdim } 797296417Sdim}; 798296417Sdim 799341825Sdim/// Classify argument of given type \p Ty. 800296417SdimABIArgInfo WebAssemblyABIInfo::classifyArgumentType(QualType Ty) const { 801296417Sdim Ty = useFirstFieldIfTransparentUnion(Ty); 802296417Sdim 803296417Sdim if (isAggregateTypeForABI(Ty)) { 804296417Sdim // Records with non-trivial destructors/copy-constructors should not be 805296417Sdim // passed by value. 806296417Sdim if (auto RAA = getRecordArgABI(Ty, getCXXABI())) 807296417Sdim return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory); 808296417Sdim // Ignore empty structs/unions. 809296417Sdim if (isEmptyRecord(getContext(), Ty, true)) 810296417Sdim return ABIArgInfo::getIgnore(); 811296417Sdim // Lower single-element structs to just pass a regular value. TODO: We 812296417Sdim // could do reasonable-size multiple-element structs too, using getExpand(), 813296417Sdim // though watch out for things like bitfields. 814296417Sdim if (const Type *SeltTy = isSingleElementStruct(Ty, getContext())) 815296417Sdim return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0))); 816296417Sdim } 817296417Sdim 818296417Sdim // Otherwise just do the default thing. 819344779Sdim return defaultInfo.classifyArgumentType(Ty); 820296417Sdim} 821296417Sdim 822296417SdimABIArgInfo WebAssemblyABIInfo::classifyReturnType(QualType RetTy) const { 823296417Sdim if (isAggregateTypeForABI(RetTy)) { 824296417Sdim // Records with non-trivial destructors/copy-constructors should not be 825296417Sdim // returned by value. 826296417Sdim if (!getRecordArgABI(RetTy, getCXXABI())) { 827296417Sdim // Ignore empty structs/unions. 828296417Sdim if (isEmptyRecord(getContext(), RetTy, true)) 829296417Sdim return ABIArgInfo::getIgnore(); 830296417Sdim // Lower single-element structs to just return a regular value. TODO: We 831296417Sdim // could do reasonable-size multiple-element structs too, using 832296417Sdim // ABIArgInfo::getDirect(). 833296417Sdim if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext())) 834296417Sdim return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0))); 835296417Sdim } 836296417Sdim } 837296417Sdim 838296417Sdim // Otherwise just do the default thing. 839344779Sdim return defaultInfo.classifyReturnType(RetTy); 840296417Sdim} 841296417Sdim 842309124SdimAddress WebAssemblyABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 843309124Sdim QualType Ty) const { 844360784Sdim bool IsIndirect = isAggregateTypeForABI(Ty) && 845360784Sdim !isEmptyRecord(getContext(), Ty, true) && 846360784Sdim !isSingleElementStruct(Ty, getContext()); 847360784Sdim return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, 848309124Sdim getContext().getTypeInfoInChars(Ty), 849309124Sdim CharUnits::fromQuantity(4), 850360784Sdim /*AllowHigherAlign=*/true); 851309124Sdim} 852309124Sdim 853296417Sdim//===----------------------------------------------------------------------===// 854243830Sdim// le32/PNaCl bitcode ABI Implementation 855251662Sdim// 856251662Sdim// This is a simplified version of the x86_32 ABI. Arguments and return values 857251662Sdim// are always passed on the stack. 858243830Sdim//===----------------------------------------------------------------------===// 859243830Sdim 860243830Sdimclass PNaClABIInfo : public ABIInfo { 861243830Sdim public: 862243830Sdim PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {} 863243830Sdim 864243830Sdim ABIArgInfo classifyReturnType(QualType RetTy) const; 865251662Sdim ABIArgInfo classifyArgumentType(QualType RetTy) const; 866243830Sdim 867276479Sdim void computeInfo(CGFunctionInfo &FI) const override; 868296417Sdim Address EmitVAArg(CodeGenFunction &CGF, 869296417Sdim Address VAListAddr, QualType Ty) const override; 870243830Sdim}; 871243830Sdim 872243830Sdimclass PNaClTargetCodeGenInfo : public TargetCodeGenInfo { 873243830Sdim public: 874243830Sdim PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT) 875243830Sdim : TargetCodeGenInfo(new PNaClABIInfo(CGT)) {} 876243830Sdim}; 877243830Sdim 878243830Sdimvoid PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const { 879276479Sdim if (!getCXXABI().classifyReturnType(FI)) 880243830Sdim FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 881243830Sdim 882276479Sdim for (auto &I : FI.arguments()) 883276479Sdim I.info = classifyArgumentType(I.type); 884276479Sdim} 885243830Sdim 886296417SdimAddress PNaClABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 887296417Sdim QualType Ty) const { 888309124Sdim // The PNaCL ABI is a bit odd, in that varargs don't use normal 889309124Sdim // function classification. Structs get passed directly for varargs 890309124Sdim // functions, through a rewriting transform in 891309124Sdim // pnacl-llvm/lib/Transforms/NaCl/ExpandVarArgs.cpp, which allows 892309124Sdim // this target to actually support a va_arg instructions with an 893309124Sdim // aggregate type, unlike other targets. 894309124Sdim return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect()); 895243830Sdim} 896243830Sdim 897341825Sdim/// Classify argument of given type \p Ty. 898251662SdimABIArgInfo PNaClABIInfo::classifyArgumentType(QualType Ty) const { 899243830Sdim if (isAggregateTypeForABI(Ty)) { 900261991Sdim if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) 901296417Sdim return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory); 902296417Sdim return getNaturalAlignIndirect(Ty); 903251662Sdim } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) { 904251662Sdim // Treat an enum type as its underlying type. 905251662Sdim Ty = EnumTy->getDecl()->getIntegerType(); 906251662Sdim } else if (Ty->isFloatingType()) { 907251662Sdim // Floating-point types don't go inreg. 908251662Sdim return ABIArgInfo::getDirect(); 909243830Sdim } 910243830Sdim 911341825Sdim return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty) 912341825Sdim : ABIArgInfo::getDirect()); 913243830Sdim} 914243830Sdim 915243830SdimABIArgInfo PNaClABIInfo::classifyReturnType(QualType RetTy) const { 916243830Sdim if (RetTy->isVoidType()) 917243830Sdim return ABIArgInfo::getIgnore(); 918243830Sdim 919249423Sdim // In the PNaCl ABI we always return records/structures on the stack. 920243830Sdim if (isAggregateTypeForABI(RetTy)) 921296417Sdim return getNaturalAlignIndirect(RetTy); 922243830Sdim 923243830Sdim // Treat an enum type as its underlying type. 924243830Sdim if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 925243830Sdim RetTy = EnumTy->getDecl()->getIntegerType(); 926243830Sdim 927341825Sdim return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy) 928341825Sdim : ABIArgInfo::getDirect()); 929243830Sdim} 930243830Sdim 931249423Sdim/// IsX86_MMXType - Return true if this is an MMX type. 932249423Sdimbool IsX86_MMXType(llvm::Type *IRType) { 933249423Sdim // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>. 934218893Sdim return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 && 935218893Sdim cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() && 936218893Sdim IRType->getScalarSizeInBits() != 64; 937218893Sdim} 938218893Sdim 939224145Sdimstatic llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF, 940226633Sdim StringRef Constraint, 941224145Sdim llvm::Type* Ty) { 942327952Sdim bool IsMMXCons = llvm::StringSwitch<bool>(Constraint) 943327952Sdim .Cases("y", "&y", "^Ym", true) 944327952Sdim .Default(false); 945327952Sdim if (IsMMXCons && Ty->isVectorTy()) { 946261991Sdim if (cast<llvm::VectorType>(Ty)->getBitWidth() != 64) { 947261991Sdim // Invalid MMX constraint 948276479Sdim return nullptr; 949261991Sdim } 950261991Sdim 951218893Sdim return llvm::Type::getX86_MMXTy(CGF.getLLVMContext()); 952261991Sdim } 953261991Sdim 954261991Sdim // No operation needed 955218893Sdim return Ty; 956218893Sdim} 957218893Sdim 958280031Sdim/// Returns true if this type can be passed in SSE registers with the 959280031Sdim/// X86_VectorCall calling convention. Shared between x86_32 and x86_64. 960280031Sdimstatic bool isX86VectorTypeForVectorCall(ASTContext &Context, QualType Ty) { 961280031Sdim if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) { 962327952Sdim if (BT->isFloatingPoint() && BT->getKind() != BuiltinType::Half) { 963327952Sdim if (BT->getKind() == BuiltinType::LongDouble) { 964327952Sdim if (&Context.getTargetInfo().getLongDoubleFormat() == 965327952Sdim &llvm::APFloat::x87DoubleExtended()) 966327952Sdim return false; 967327952Sdim } 968280031Sdim return true; 969327952Sdim } 970280031Sdim } else if (const VectorType *VT = Ty->getAs<VectorType>()) { 971280031Sdim // vectorcall can pass XMM, YMM, and ZMM vectors. We don't pass SSE1 MMX 972280031Sdim // registers specially. 973280031Sdim unsigned VecSize = Context.getTypeSize(VT); 974280031Sdim if (VecSize == 128 || VecSize == 256 || VecSize == 512) 975280031Sdim return true; 976280031Sdim } 977280031Sdim return false; 978280031Sdim} 979280031Sdim 980280031Sdim/// Returns true if this aggregate is small enough to be passed in SSE registers 981280031Sdim/// in the X86_VectorCall calling convention. Shared between x86_32 and x86_64. 982280031Sdimstatic bool isX86VectorCallAggregateSmallEnough(uint64_t NumMembers) { 983280031Sdim return NumMembers <= 4; 984280031Sdim} 985280031Sdim 986314564Sdim/// Returns a Homogeneous Vector Aggregate ABIArgInfo, used in X86. 987314564Sdimstatic ABIArgInfo getDirectX86Hva(llvm::Type* T = nullptr) { 988314564Sdim auto AI = ABIArgInfo::getDirect(T); 989314564Sdim AI.setInReg(true); 990314564Sdim AI.setCanBeFlattened(false); 991314564Sdim return AI; 992314564Sdim} 993314564Sdim 994210299Sed//===----------------------------------------------------------------------===// 995210299Sed// X86-32 ABI Implementation 996210299Sed//===----------------------------------------------------------------------===// 997212904Sdim 998341825Sdim/// Similar to llvm::CCState, but for Clang. 999276479Sdimstruct CCState { 1000360784Sdim CCState(CGFunctionInfo &FI) 1001360784Sdim : IsPreassigned(FI.arg_size()), CC(FI.getCallingConvention()) {} 1002276479Sdim 1003360784Sdim llvm::SmallBitVector IsPreassigned; 1004360784Sdim unsigned CC = CallingConv::CC_C; 1005360784Sdim unsigned FreeRegs = 0; 1006360784Sdim unsigned FreeSSERegs = 0; 1007276479Sdim}; 1008276479Sdim 1009314564Sdimenum { 1010314564Sdim // Vectorcall only allows the first 6 parameters to be passed in registers. 1011314564Sdim VectorcallMaxParamNumAsReg = 6 1012314564Sdim}; 1013314564Sdim 1014202379Srdivacky/// X86_32ABIInfo - The X86-32 ABI information. 1015309124Sdimclass X86_32ABIInfo : public SwiftABIInfo { 1016239462Sdim enum Class { 1017239462Sdim Integer, 1018239462Sdim Float 1019239462Sdim }; 1020239462Sdim 1021218893Sdim static const unsigned MinABIStackAlignInBytes = 4; 1022218893Sdim 1023202379Srdivacky bool IsDarwinVectorABI; 1024296417Sdim bool IsRetSmallStructInRegABI; 1025251662Sdim bool IsWin32StructABI; 1026296417Sdim bool IsSoftFloatABI; 1027296417Sdim bool IsMCUABI; 1028239462Sdim unsigned DefaultNumRegisterParameters; 1029202379Srdivacky 1030202379Srdivacky static bool isRegisterSize(unsigned Size) { 1031202379Srdivacky return (Size == 8 || Size == 16 || Size == 32 || Size == 64); 1032202379Srdivacky } 1033202379Srdivacky 1034280031Sdim bool isHomogeneousAggregateBaseType(QualType Ty) const override { 1035280031Sdim // FIXME: Assumes vectorcall is in use. 1036280031Sdim return isX86VectorTypeForVectorCall(getContext(), Ty); 1037280031Sdim } 1038280031Sdim 1039280031Sdim bool isHomogeneousAggregateSmallEnough(const Type *Ty, 1040280031Sdim uint64_t NumMembers) const override { 1041280031Sdim // FIXME: Assumes vectorcall is in use. 1042280031Sdim return isX86VectorCallAggregateSmallEnough(NumMembers); 1043280031Sdim } 1044280031Sdim 1045276479Sdim bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context) const; 1046202379Srdivacky 1047207619Srdivacky /// getIndirectResult - Give a source type \arg Ty, return a suitable result 1048207619Srdivacky /// such that the argument will be passed in memory. 1049276479Sdim ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const; 1050202379Srdivacky 1051296417Sdim ABIArgInfo getIndirectReturnResult(QualType Ty, CCState &State) const; 1052276479Sdim 1053341825Sdim /// Return the alignment to use for the given type on the stack. 1054218893Sdim unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const; 1055218893Sdim 1056239462Sdim Class classify(QualType Ty) const; 1057276479Sdim ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const; 1058276479Sdim ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const; 1059321369Sdim 1060341825Sdim /// Updates the number of available free registers, returns 1061296417Sdim /// true if any registers were allocated. 1062296417Sdim bool updateFreeRegs(QualType Ty, CCState &State) const; 1063202379Srdivacky 1064296417Sdim bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg, 1065296417Sdim bool &NeedsPadding) const; 1066296417Sdim bool shouldPrimitiveUseInReg(QualType Ty, CCState &State) const; 1067296417Sdim 1068309124Sdim bool canExpandIndirectArgument(QualType Ty) const; 1069309124Sdim 1070341825Sdim /// Rewrite the function info so that all memory arguments use 1071276479Sdim /// inalloca. 1072276479Sdim void rewriteWithInAlloca(CGFunctionInfo &FI) const; 1073276479Sdim 1074276479Sdim void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields, 1075296417Sdim CharUnits &StackOffset, ABIArgInfo &Info, 1076276479Sdim QualType Type) const; 1077360784Sdim void runVectorCallFirstPass(CGFunctionInfo &FI, CCState &State) const; 1078276479Sdim 1079239462Sdimpublic: 1080202379Srdivacky 1081276479Sdim void computeInfo(CGFunctionInfo &FI) const override; 1082296417Sdim Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 1083296417Sdim QualType Ty) const override; 1084202379Srdivacky 1085296417Sdim X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI, 1086296417Sdim bool RetSmallStructInRegABI, bool Win32StructABI, 1087296417Sdim unsigned NumRegisterParameters, bool SoftFloatABI) 1088309124Sdim : SwiftABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI), 1089341825Sdim IsRetSmallStructInRegABI(RetSmallStructInRegABI), 1090296417Sdim IsWin32StructABI(Win32StructABI), 1091296417Sdim IsSoftFloatABI(SoftFloatABI), 1092296417Sdim IsMCUABI(CGT.getTarget().getTriple().isOSIAMCU()), 1093296417Sdim DefaultNumRegisterParameters(NumRegisterParameters) {} 1094309124Sdim 1095341825Sdim bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars, 1096309124Sdim bool asReturnValue) const override { 1097309124Sdim // LLVM's x86-32 lowering currently only assigns up to three 1098309124Sdim // integer registers and three fp registers. Oddly, it'll use up to 1099309124Sdim // four vector registers for vectors, but those can overlap with the 1100309124Sdim // scalar registers. 1101309124Sdim return occupiesMoreThan(CGT, scalars, /*total*/ 3); 1102341825Sdim } 1103314564Sdim 1104314564Sdim bool isSwiftErrorInRegister() const override { 1105314564Sdim // x86-32 lowering does not support passing swifterror in a register. 1106314564Sdim return false; 1107314564Sdim } 1108202379Srdivacky}; 1109202379Srdivacky 1110202379Srdivackyclass X86_32TargetCodeGenInfo : public TargetCodeGenInfo { 1111202379Srdivackypublic: 1112296417Sdim X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI, 1113296417Sdim bool RetSmallStructInRegABI, bool Win32StructABI, 1114296417Sdim unsigned NumRegisterParameters, bool SoftFloatABI) 1115296417Sdim : TargetCodeGenInfo(new X86_32ABIInfo( 1116296417Sdim CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI, 1117296417Sdim NumRegisterParameters, SoftFloatABI)) {} 1118203955Srdivacky 1119261991Sdim static bool isStructReturnInRegABI( 1120261991Sdim const llvm::Triple &Triple, const CodeGenOptions &Opts); 1121261991Sdim 1122288943Sdim void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 1123341825Sdim CodeGen::CodeGenModule &CGM) const override; 1124204793Srdivacky 1125276479Sdim int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override { 1126204793Srdivacky // Darwin uses different dwarf register numbers for EH. 1127251662Sdim if (CGM.getTarget().getTriple().isOSDarwin()) return 5; 1128204793Srdivacky return 4; 1129204793Srdivacky } 1130204793Srdivacky 1131204793Srdivacky bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 1132276479Sdim llvm::Value *Address) const override; 1133218893Sdim 1134224145Sdim llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF, 1135226633Sdim StringRef Constraint, 1136276479Sdim llvm::Type* Ty) const override { 1137218893Sdim return X86AdjustInlineAsmType(CGF, Constraint, Ty); 1138218893Sdim } 1139218893Sdim 1140280031Sdim void addReturnRegisterOutputs(CodeGenFunction &CGF, LValue ReturnValue, 1141280031Sdim std::string &Constraints, 1142280031Sdim std::vector<llvm::Type *> &ResultRegTypes, 1143280031Sdim std::vector<llvm::Type *> &ResultTruncRegTypes, 1144280031Sdim std::vector<LValue> &ResultRegDests, 1145280031Sdim std::string &AsmString, 1146280031Sdim unsigned NumOutputs) const override; 1147280031Sdim 1148276479Sdim llvm::Constant * 1149276479Sdim getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override { 1150261991Sdim unsigned Sig = (0xeb << 0) | // jmp rel8 1151261991Sdim (0x06 << 8) | // .+0x08 1152327952Sdim ('v' << 16) | 1153327952Sdim ('2' << 24); 1154261991Sdim return llvm::ConstantInt::get(CGM.Int32Ty, Sig); 1155261991Sdim } 1156309124Sdim 1157309124Sdim StringRef getARCRetainAutoreleasedReturnValueMarker() const override { 1158309124Sdim return "movl\t%ebp, %ebp" 1159327952Sdim "\t\t// marker for objc_retainAutoreleaseReturnValue"; 1160309124Sdim } 1161202379Srdivacky}; 1162202379Srdivacky 1163202379Srdivacky} 1164202379Srdivacky 1165280031Sdim/// Rewrite input constraint references after adding some output constraints. 1166280031Sdim/// In the case where there is one output and one input and we add one output, 1167280031Sdim/// we need to replace all operand references greater than or equal to 1: 1168280031Sdim/// mov $0, $1 1169280031Sdim/// mov eax, $1 1170280031Sdim/// The result will be: 1171280031Sdim/// mov $0, $2 1172280031Sdim/// mov eax, $2 1173280031Sdimstatic void rewriteInputConstraintReferences(unsigned FirstIn, 1174280031Sdim unsigned NumNewOuts, 1175280031Sdim std::string &AsmString) { 1176280031Sdim std::string Buf; 1177280031Sdim llvm::raw_string_ostream OS(Buf); 1178280031Sdim size_t Pos = 0; 1179280031Sdim while (Pos < AsmString.size()) { 1180280031Sdim size_t DollarStart = AsmString.find('$', Pos); 1181280031Sdim if (DollarStart == std::string::npos) 1182280031Sdim DollarStart = AsmString.size(); 1183280031Sdim size_t DollarEnd = AsmString.find_first_not_of('$', DollarStart); 1184280031Sdim if (DollarEnd == std::string::npos) 1185280031Sdim DollarEnd = AsmString.size(); 1186280031Sdim OS << StringRef(&AsmString[Pos], DollarEnd - Pos); 1187280031Sdim Pos = DollarEnd; 1188280031Sdim size_t NumDollars = DollarEnd - DollarStart; 1189280031Sdim if (NumDollars % 2 != 0 && Pos < AsmString.size()) { 1190280031Sdim // We have an operand reference. 1191280031Sdim size_t DigitStart = Pos; 1192360784Sdim if (AsmString[DigitStart] == '{') { 1193360784Sdim OS << '{'; 1194360784Sdim ++DigitStart; 1195360784Sdim } 1196280031Sdim size_t DigitEnd = AsmString.find_first_not_of("0123456789", DigitStart); 1197280031Sdim if (DigitEnd == std::string::npos) 1198280031Sdim DigitEnd = AsmString.size(); 1199280031Sdim StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart); 1200280031Sdim unsigned OperandIndex; 1201280031Sdim if (!OperandStr.getAsInteger(10, OperandIndex)) { 1202280031Sdim if (OperandIndex >= FirstIn) 1203280031Sdim OperandIndex += NumNewOuts; 1204280031Sdim OS << OperandIndex; 1205280031Sdim } else { 1206280031Sdim OS << OperandStr; 1207280031Sdim } 1208280031Sdim Pos = DigitEnd; 1209280031Sdim } 1210280031Sdim } 1211280031Sdim AsmString = std::move(OS.str()); 1212280031Sdim} 1213280031Sdim 1214280031Sdim/// Add output constraints for EAX:EDX because they are return registers. 1215280031Sdimvoid X86_32TargetCodeGenInfo::addReturnRegisterOutputs( 1216280031Sdim CodeGenFunction &CGF, LValue ReturnSlot, std::string &Constraints, 1217280031Sdim std::vector<llvm::Type *> &ResultRegTypes, 1218280031Sdim std::vector<llvm::Type *> &ResultTruncRegTypes, 1219280031Sdim std::vector<LValue> &ResultRegDests, std::string &AsmString, 1220280031Sdim unsigned NumOutputs) const { 1221280031Sdim uint64_t RetWidth = CGF.getContext().getTypeSize(ReturnSlot.getType()); 1222280031Sdim 1223280031Sdim // Use the EAX constraint if the width is 32 or smaller and EAX:EDX if it is 1224280031Sdim // larger. 1225280031Sdim if (!Constraints.empty()) 1226280031Sdim Constraints += ','; 1227280031Sdim if (RetWidth <= 32) { 1228280031Sdim Constraints += "={eax}"; 1229280031Sdim ResultRegTypes.push_back(CGF.Int32Ty); 1230280031Sdim } else { 1231280031Sdim // Use the 'A' constraint for EAX:EDX. 1232280031Sdim Constraints += "=A"; 1233280031Sdim ResultRegTypes.push_back(CGF.Int64Ty); 1234280031Sdim } 1235280031Sdim 1236280031Sdim // Truncate EAX or EAX:EDX to an integer of the appropriate size. 1237280031Sdim llvm::Type *CoerceTy = llvm::IntegerType::get(CGF.getLLVMContext(), RetWidth); 1238280031Sdim ResultTruncRegTypes.push_back(CoerceTy); 1239280031Sdim 1240280031Sdim // Coerce the integer by bitcasting the return slot pointer. 1241360784Sdim ReturnSlot.setAddress(CGF.Builder.CreateBitCast(ReturnSlot.getAddress(CGF), 1242280031Sdim CoerceTy->getPointerTo())); 1243280031Sdim ResultRegDests.push_back(ReturnSlot); 1244280031Sdim 1245280031Sdim rewriteInputConstraintReferences(NumOutputs, 1, AsmString); 1246280031Sdim} 1247280031Sdim 1248202379Srdivacky/// shouldReturnTypeInRegister - Determine if the given type should be 1249296417Sdim/// returned in a register (for the Darwin and MCU ABI). 1250202379Srdivackybool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty, 1251276479Sdim ASTContext &Context) const { 1252202379Srdivacky uint64_t Size = Context.getTypeSize(Ty); 1253202379Srdivacky 1254296417Sdim // For i386, type must be register sized. 1255296417Sdim // For the MCU ABI, it only needs to be <= 8-byte 1256296417Sdim if ((IsMCUABI && Size > 64) || (!IsMCUABI && !isRegisterSize(Size))) 1257296417Sdim return false; 1258202379Srdivacky 1259202379Srdivacky if (Ty->isVectorType()) { 1260202379Srdivacky // 64- and 128- bit vectors inside structures are not returned in 1261202379Srdivacky // registers. 1262202379Srdivacky if (Size == 64 || Size == 128) 1263202379Srdivacky return false; 1264202379Srdivacky 1265202379Srdivacky return true; 1266202379Srdivacky } 1267202379Srdivacky 1268208600Srdivacky // If this is a builtin, pointer, enum, complex type, member pointer, or 1269208600Srdivacky // member function pointer it is ok. 1270208600Srdivacky if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() || 1271202379Srdivacky Ty->isAnyComplexType() || Ty->isEnumeralType() || 1272208600Srdivacky Ty->isBlockPointerType() || Ty->isMemberPointerType()) 1273202379Srdivacky return true; 1274202379Srdivacky 1275202379Srdivacky // Arrays are treated like records. 1276202379Srdivacky if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) 1277276479Sdim return shouldReturnTypeInRegister(AT->getElementType(), Context); 1278202379Srdivacky 1279202379Srdivacky // Otherwise, it must be a record type. 1280202379Srdivacky const RecordType *RT = Ty->getAs<RecordType>(); 1281202379Srdivacky if (!RT) return false; 1282202379Srdivacky 1283203955Srdivacky // FIXME: Traverse bases here too. 1284203955Srdivacky 1285202379Srdivacky // Structure types are passed in register if all fields would be 1286202379Srdivacky // passed in a register. 1287276479Sdim for (const auto *FD : RT->getDecl()->fields()) { 1288202379Srdivacky // Empty fields are ignored. 1289202379Srdivacky if (isEmptyField(Context, FD, true)) 1290202379Srdivacky continue; 1291202379Srdivacky 1292202379Srdivacky // Check fields recursively. 1293276479Sdim if (!shouldReturnTypeInRegister(FD->getType(), Context)) 1294202379Srdivacky return false; 1295202379Srdivacky } 1296202379Srdivacky return true; 1297202379Srdivacky} 1298202379Srdivacky 1299309124Sdimstatic bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) { 1300309124Sdim // Treat complex types as the element type. 1301309124Sdim if (const ComplexType *CTy = Ty->getAs<ComplexType>()) 1302309124Sdim Ty = CTy->getElementType(); 1303309124Sdim 1304309124Sdim // Check for a type which we know has a simple scalar argument-passing 1305309124Sdim // convention without any padding. (We're specifically looking for 32 1306309124Sdim // and 64-bit integer and integer-equivalents, float, and double.) 1307309124Sdim if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() && 1308309124Sdim !Ty->isEnumeralType() && !Ty->isBlockPointerType()) 1309309124Sdim return false; 1310309124Sdim 1311309124Sdim uint64_t Size = Context.getTypeSize(Ty); 1312309124Sdim return Size == 32 || Size == 64; 1313309124Sdim} 1314309124Sdim 1315321369Sdimstatic bool addFieldSizes(ASTContext &Context, const RecordDecl *RD, 1316321369Sdim uint64_t &Size) { 1317321369Sdim for (const auto *FD : RD->fields()) { 1318321369Sdim // Scalar arguments on the stack get 4 byte alignment on x86. If the 1319321369Sdim // argument is smaller than 32-bits, expanding the struct will create 1320321369Sdim // alignment padding. 1321321369Sdim if (!is32Or64BitBasicType(FD->getType(), Context)) 1322321369Sdim return false; 1323321369Sdim 1324321369Sdim // FIXME: Reject bit-fields wholesale; there are two problems, we don't know 1325321369Sdim // how to expand them yet, and the predicate for telling if a bitfield still 1326321369Sdim // counts as "basic" is more complicated than what we were doing previously. 1327321369Sdim if (FD->isBitField()) 1328321369Sdim return false; 1329321369Sdim 1330321369Sdim Size += Context.getTypeSize(FD->getType()); 1331321369Sdim } 1332321369Sdim return true; 1333321369Sdim} 1334321369Sdim 1335321369Sdimstatic bool addBaseAndFieldSizes(ASTContext &Context, const CXXRecordDecl *RD, 1336321369Sdim uint64_t &Size) { 1337321369Sdim // Don't do this if there are any non-empty bases. 1338321369Sdim for (const CXXBaseSpecifier &Base : RD->bases()) { 1339321369Sdim if (!addBaseAndFieldSizes(Context, Base.getType()->getAsCXXRecordDecl(), 1340321369Sdim Size)) 1341321369Sdim return false; 1342321369Sdim } 1343321369Sdim if (!addFieldSizes(Context, RD, Size)) 1344321369Sdim return false; 1345321369Sdim return true; 1346321369Sdim} 1347321369Sdim 1348309124Sdim/// Test whether an argument type which is to be passed indirectly (on the 1349309124Sdim/// stack) would have the equivalent layout if it was expanded into separate 1350309124Sdim/// arguments. If so, we prefer to do the latter to avoid inhibiting 1351309124Sdim/// optimizations. 1352309124Sdimbool X86_32ABIInfo::canExpandIndirectArgument(QualType Ty) const { 1353309124Sdim // We can only expand structure types. 1354309124Sdim const RecordType *RT = Ty->getAs<RecordType>(); 1355309124Sdim if (!RT) 1356309124Sdim return false; 1357309124Sdim const RecordDecl *RD = RT->getDecl(); 1358321369Sdim uint64_t Size = 0; 1359309124Sdim if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) { 1360321369Sdim if (!IsWin32StructABI) { 1361309124Sdim // On non-Windows, we have to conservatively match our old bitcode 1362309124Sdim // prototypes in order to be ABI-compatible at the bitcode level. 1363309124Sdim if (!CXXRD->isCLike()) 1364309124Sdim return false; 1365309124Sdim } else { 1366309124Sdim // Don't do this for dynamic classes. 1367309124Sdim if (CXXRD->isDynamicClass()) 1368309124Sdim return false; 1369309124Sdim } 1370321369Sdim if (!addBaseAndFieldSizes(getContext(), CXXRD, Size)) 1371309124Sdim return false; 1372321369Sdim } else { 1373321369Sdim if (!addFieldSizes(getContext(), RD, Size)) 1374309124Sdim return false; 1375309124Sdim } 1376309124Sdim 1377309124Sdim // We can do this if there was no alignment padding. 1378309124Sdim return Size == getContext().getTypeSize(Ty); 1379309124Sdim} 1380309124Sdim 1381296417SdimABIArgInfo X86_32ABIInfo::getIndirectReturnResult(QualType RetTy, CCState &State) const { 1382276479Sdim // If the return value is indirect, then the hidden argument is consuming one 1383276479Sdim // integer register. 1384276479Sdim if (State.FreeRegs) { 1385276479Sdim --State.FreeRegs; 1386296417Sdim if (!IsMCUABI) 1387296417Sdim return getNaturalAlignIndirectInReg(RetTy); 1388276479Sdim } 1389296417Sdim return getNaturalAlignIndirect(RetTy, /*ByVal=*/false); 1390276479Sdim} 1391276479Sdim 1392288943SdimABIArgInfo X86_32ABIInfo::classifyReturnType(QualType RetTy, 1393288943Sdim CCState &State) const { 1394212904Sdim if (RetTy->isVoidType()) 1395202379Srdivacky return ABIArgInfo::getIgnore(); 1396212904Sdim 1397280031Sdim const Type *Base = nullptr; 1398280031Sdim uint64_t NumElts = 0; 1399314564Sdim if ((State.CC == llvm::CallingConv::X86_VectorCall || 1400314564Sdim State.CC == llvm::CallingConv::X86_RegCall) && 1401280031Sdim isHomogeneousAggregate(RetTy, Base, NumElts)) { 1402280031Sdim // The LLVM struct type for such an aggregate should lower properly. 1403280031Sdim return ABIArgInfo::getDirect(); 1404280031Sdim } 1405280031Sdim 1406212904Sdim if (const VectorType *VT = RetTy->getAs<VectorType>()) { 1407202379Srdivacky // On Darwin, some vectors are returned in registers. 1408202379Srdivacky if (IsDarwinVectorABI) { 1409212904Sdim uint64_t Size = getContext().getTypeSize(RetTy); 1410202379Srdivacky 1411202379Srdivacky // 128-bit vectors are a special case; they are returned in 1412202379Srdivacky // registers and we need to make sure to pick a type the LLVM 1413202379Srdivacky // backend will like. 1414202379Srdivacky if (Size == 128) 1415212904Sdim return ABIArgInfo::getDirect(llvm::VectorType::get( 1416212904Sdim llvm::Type::getInt64Ty(getVMContext()), 2)); 1417202379Srdivacky 1418202379Srdivacky // Always return in register if it fits in a general purpose 1419202379Srdivacky // register, or if it is 64 bits and has a single element. 1420202379Srdivacky if ((Size == 8 || Size == 16 || Size == 32) || 1421202379Srdivacky (Size == 64 && VT->getNumElements() == 1)) 1422212904Sdim return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 1423212904Sdim Size)); 1424202379Srdivacky 1425296417Sdim return getIndirectReturnResult(RetTy, State); 1426202379Srdivacky } 1427202379Srdivacky 1428202379Srdivacky return ABIArgInfo::getDirect(); 1429212904Sdim } 1430212904Sdim 1431212904Sdim if (isAggregateTypeForABI(RetTy)) { 1432203955Srdivacky if (const RecordType *RT = RetTy->getAs<RecordType>()) { 1433202379Srdivacky // Structures with flexible arrays are always indirect. 1434202379Srdivacky if (RT->getDecl()->hasFlexibleArrayMember()) 1435296417Sdim return getIndirectReturnResult(RetTy, State); 1436202379Srdivacky } 1437212904Sdim 1438202379Srdivacky // If specified, structs and unions are always indirect. 1439296417Sdim if (!IsRetSmallStructInRegABI && !RetTy->isAnyComplexType()) 1440296417Sdim return getIndirectReturnResult(RetTy, State); 1441202379Srdivacky 1442309124Sdim // Ignore empty structs/unions. 1443309124Sdim if (isEmptyRecord(getContext(), RetTy, true)) 1444309124Sdim return ABIArgInfo::getIgnore(); 1445309124Sdim 1446202379Srdivacky // Small structures which are register sized are generally returned 1447202379Srdivacky // in a register. 1448276479Sdim if (shouldReturnTypeInRegister(RetTy, getContext())) { 1449212904Sdim uint64_t Size = getContext().getTypeSize(RetTy); 1450234353Sdim 1451234353Sdim // As a special-case, if the struct is a "single-element" struct, and 1452234353Sdim // the field is of type "float" or "double", return it in a 1453234353Sdim // floating-point register. (MSVC does not apply this special case.) 1454234353Sdim // We apply a similar transformation for pointer types to improve the 1455234353Sdim // quality of the generated IR. 1456234353Sdim if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext())) 1457251662Sdim if ((!IsWin32StructABI && SeltTy->isRealFloatingType()) 1458234353Sdim || SeltTy->hasPointerRepresentation()) 1459234353Sdim return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0))); 1460234353Sdim 1461234353Sdim // FIXME: We should be able to narrow this integer in cases with dead 1462234353Sdim // padding. 1463212904Sdim return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size)); 1464202379Srdivacky } 1465202379Srdivacky 1466296417Sdim return getIndirectReturnResult(RetTy, State); 1467212904Sdim } 1468203955Srdivacky 1469212904Sdim // Treat an enum type as its underlying type. 1470212904Sdim if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 1471212904Sdim RetTy = EnumTy->getDecl()->getIntegerType(); 1472212904Sdim 1473341825Sdim return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy) 1474341825Sdim : ABIArgInfo::getDirect()); 1475202379Srdivacky} 1476202379Srdivacky 1477239462Sdimstatic bool isSSEVectorType(ASTContext &Context, QualType Ty) { 1478239462Sdim return Ty->getAs<VectorType>() && Context.getTypeSize(Ty) == 128; 1479239462Sdim} 1480239462Sdim 1481218893Sdimstatic bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty) { 1482218893Sdim const RecordType *RT = Ty->getAs<RecordType>(); 1483218893Sdim if (!RT) 1484218893Sdim return 0; 1485218893Sdim const RecordDecl *RD = RT->getDecl(); 1486218893Sdim 1487218893Sdim // If this is a C++ record, check the bases first. 1488218893Sdim if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) 1489276479Sdim for (const auto &I : CXXRD->bases()) 1490276479Sdim if (!isRecordWithSSEVectorType(Context, I.getType())) 1491218893Sdim return false; 1492218893Sdim 1493276479Sdim for (const auto *i : RD->fields()) { 1494218893Sdim QualType FT = i->getType(); 1495218893Sdim 1496239462Sdim if (isSSEVectorType(Context, FT)) 1497218893Sdim return true; 1498218893Sdim 1499218893Sdim if (isRecordWithSSEVectorType(Context, FT)) 1500218893Sdim return true; 1501218893Sdim } 1502218893Sdim 1503218893Sdim return false; 1504218893Sdim} 1505218893Sdim 1506218893Sdimunsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty, 1507218893Sdim unsigned Align) const { 1508218893Sdim // Otherwise, if the alignment is less than or equal to the minimum ABI 1509218893Sdim // alignment, just use the default; the backend will handle this. 1510218893Sdim if (Align <= MinABIStackAlignInBytes) 1511218893Sdim return 0; // Use default alignment. 1512218893Sdim 1513218893Sdim // On non-Darwin, the stack type alignment is always 4. 1514218893Sdim if (!IsDarwinVectorABI) { 1515218893Sdim // Set explicit alignment, since we may need to realign the top. 1516218893Sdim return MinABIStackAlignInBytes; 1517218893Sdim } 1518218893Sdim 1519218893Sdim // Otherwise, if the type contains an SSE vector type, the alignment is 16. 1520239462Sdim if (Align >= 16 && (isSSEVectorType(getContext(), Ty) || 1521239462Sdim isRecordWithSSEVectorType(getContext(), Ty))) 1522218893Sdim return 16; 1523218893Sdim 1524218893Sdim return MinABIStackAlignInBytes; 1525218893Sdim} 1526218893Sdim 1527243830SdimABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal, 1528276479Sdim CCState &State) const { 1529243830Sdim if (!ByVal) { 1530276479Sdim if (State.FreeRegs) { 1531276479Sdim --State.FreeRegs; // Non-byval indirects just use one pointer. 1532296417Sdim if (!IsMCUABI) 1533296417Sdim return getNaturalAlignIndirectInReg(Ty); 1534243830Sdim } 1535296417Sdim return getNaturalAlignIndirect(Ty, false); 1536243830Sdim } 1537207619Srdivacky 1538218893Sdim // Compute the byval alignment. 1539218893Sdim unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8; 1540218893Sdim unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign); 1541218893Sdim if (StackAlign == 0) 1542296417Sdim return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true); 1543218893Sdim 1544218893Sdim // If the stack alignment is less than the type alignment, realign the 1545218893Sdim // argument. 1546276479Sdim bool Realign = TypeAlign > StackAlign; 1547296417Sdim return ABIArgInfo::getIndirect(CharUnits::fromQuantity(StackAlign), 1548296417Sdim /*ByVal=*/true, Realign); 1549202379Srdivacky} 1550202379Srdivacky 1551239462SdimX86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const { 1552239462Sdim const Type *T = isSingleElementStruct(Ty, getContext()); 1553239462Sdim if (!T) 1554239462Sdim T = Ty.getTypePtr(); 1555239462Sdim 1556239462Sdim if (const BuiltinType *BT = T->getAs<BuiltinType>()) { 1557239462Sdim BuiltinType::Kind K = BT->getKind(); 1558239462Sdim if (K == BuiltinType::Float || K == BuiltinType::Double) 1559239462Sdim return Float; 1560239462Sdim } 1561239462Sdim return Integer; 1562239462Sdim} 1563239462Sdim 1564296417Sdimbool X86_32ABIInfo::updateFreeRegs(QualType Ty, CCState &State) const { 1565296417Sdim if (!IsSoftFloatABI) { 1566296417Sdim Class C = classify(Ty); 1567296417Sdim if (C == Float) 1568296417Sdim return false; 1569296417Sdim } 1570239462Sdim 1571243830Sdim unsigned Size = getContext().getTypeSize(Ty); 1572243830Sdim unsigned SizeInRegs = (Size + 31) / 32; 1573243830Sdim 1574239462Sdim if (SizeInRegs == 0) 1575243830Sdim return false; 1576239462Sdim 1577296417Sdim if (!IsMCUABI) { 1578296417Sdim if (SizeInRegs > State.FreeRegs) { 1579296417Sdim State.FreeRegs = 0; 1580296417Sdim return false; 1581296417Sdim } 1582296417Sdim } else { 1583296417Sdim // The MCU psABI allows passing parameters in-reg even if there are 1584296417Sdim // earlier parameters that are passed on the stack. Also, 1585296417Sdim // it does not allow passing >8-byte structs in-register, 1586296417Sdim // even if there are 3 free registers available. 1587296417Sdim if (SizeInRegs > State.FreeRegs || SizeInRegs > 2) 1588296417Sdim return false; 1589239462Sdim } 1590243830Sdim 1591276479Sdim State.FreeRegs -= SizeInRegs; 1592296417Sdim return true; 1593296417Sdim} 1594239462Sdim 1595341825Sdimbool X86_32ABIInfo::shouldAggregateUseDirect(QualType Ty, CCState &State, 1596296417Sdim bool &InReg, 1597296417Sdim bool &NeedsPadding) const { 1598309124Sdim // On Windows, aggregates other than HFAs are never passed in registers, and 1599309124Sdim // they do not consume register slots. Homogenous floating-point aggregates 1600309124Sdim // (HFAs) have already been dealt with at this point. 1601309124Sdim if (IsWin32StructABI && isAggregateTypeForABI(Ty)) 1602309124Sdim return false; 1603309124Sdim 1604296417Sdim NeedsPadding = false; 1605296417Sdim InReg = !IsMCUABI; 1606296417Sdim 1607296417Sdim if (!updateFreeRegs(Ty, State)) 1608296417Sdim return false; 1609296417Sdim 1610296417Sdim if (IsMCUABI) 1611296417Sdim return true; 1612296417Sdim 1613280031Sdim if (State.CC == llvm::CallingConv::X86_FastCall || 1614314564Sdim State.CC == llvm::CallingConv::X86_VectorCall || 1615314564Sdim State.CC == llvm::CallingConv::X86_RegCall) { 1616296417Sdim if (getContext().getTypeSize(Ty) <= 32 && State.FreeRegs) 1617296417Sdim NeedsPadding = true; 1618239462Sdim 1619296417Sdim return false; 1620296417Sdim } 1621243830Sdim 1622296417Sdim return true; 1623296417Sdim} 1624243830Sdim 1625296417Sdimbool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const { 1626296417Sdim if (!updateFreeRegs(Ty, State)) 1627296417Sdim return false; 1628243830Sdim 1629296417Sdim if (IsMCUABI) 1630296417Sdim return false; 1631243830Sdim 1632296417Sdim if (State.CC == llvm::CallingConv::X86_FastCall || 1633314564Sdim State.CC == llvm::CallingConv::X86_VectorCall || 1634314564Sdim State.CC == llvm::CallingConv::X86_RegCall) { 1635296417Sdim if (getContext().getTypeSize(Ty) > 32) 1636296417Sdim return false; 1637296417Sdim 1638341825Sdim return (Ty->isIntegralOrEnumerationType() || Ty->isPointerType() || 1639296417Sdim Ty->isReferenceType()); 1640243830Sdim } 1641243830Sdim 1642243830Sdim return true; 1643239462Sdim} 1644239462Sdim 1645360784Sdimvoid X86_32ABIInfo::runVectorCallFirstPass(CGFunctionInfo &FI, CCState &State) const { 1646360784Sdim // Vectorcall x86 works subtly different than in x64, so the format is 1647360784Sdim // a bit different than the x64 version. First, all vector types (not HVAs) 1648360784Sdim // are assigned, with the first 6 ending up in the [XYZ]MM0-5 registers. 1649360784Sdim // This differs from the x64 implementation, where the first 6 by INDEX get 1650360784Sdim // registers. 1651360784Sdim // In the second pass over the arguments, HVAs are passed in the remaining 1652360784Sdim // vector registers if possible, or indirectly by address. The address will be 1653360784Sdim // passed in ECX/EDX if available. Any other arguments are passed according to 1654360784Sdim // the usual fastcall rules. 1655360784Sdim MutableArrayRef<CGFunctionInfoArgInfo> Args = FI.arguments(); 1656360784Sdim for (int I = 0, E = Args.size(); I < E; ++I) { 1657360784Sdim const Type *Base = nullptr; 1658360784Sdim uint64_t NumElts = 0; 1659360784Sdim const QualType &Ty = Args[I].type; 1660360784Sdim if ((Ty->isVectorType() || Ty->isBuiltinType()) && 1661360784Sdim isHomogeneousAggregate(Ty, Base, NumElts)) { 1662360784Sdim if (State.FreeSSERegs >= NumElts) { 1663360784Sdim State.FreeSSERegs -= NumElts; 1664360784Sdim Args[I].info = ABIArgInfo::getDirect(); 1665360784Sdim State.IsPreassigned.set(I); 1666360784Sdim } 1667360784Sdim } 1668360784Sdim } 1669360784Sdim} 1670360784Sdim 1671243830SdimABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty, 1672276479Sdim CCState &State) const { 1673202379Srdivacky // FIXME: Set alignment on indirect arguments. 1674360784Sdim bool IsFastCall = State.CC == llvm::CallingConv::X86_FastCall; 1675360784Sdim bool IsRegCall = State.CC == llvm::CallingConv::X86_RegCall; 1676360784Sdim bool IsVectorCall = State.CC == llvm::CallingConv::X86_VectorCall; 1677280031Sdim 1678280031Sdim Ty = useFirstFieldIfTransparentUnion(Ty); 1679280031Sdim 1680280031Sdim // Check with the C++ ABI first. 1681280031Sdim const RecordType *RT = Ty->getAs<RecordType>(); 1682280031Sdim if (RT) { 1683280031Sdim CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI()); 1684280031Sdim if (RAA == CGCXXABI::RAA_Indirect) { 1685280031Sdim return getIndirectResult(Ty, false, State); 1686280031Sdim } else if (RAA == CGCXXABI::RAA_DirectInMemory) { 1687280031Sdim // The field index doesn't matter, we'll fix it up later. 1688280031Sdim return ABIArgInfo::getInAlloca(/*FieldIndex=*/0); 1689280031Sdim } 1690280031Sdim } 1691280031Sdim 1692321369Sdim // Regcall uses the concept of a homogenous vector aggregate, similar 1693321369Sdim // to other targets. 1694280031Sdim const Type *Base = nullptr; 1695280031Sdim uint64_t NumElts = 0; 1696360784Sdim if ((IsRegCall || IsVectorCall) && 1697280031Sdim isHomogeneousAggregate(Ty, Base, NumElts)) { 1698321369Sdim if (State.FreeSSERegs >= NumElts) { 1699321369Sdim State.FreeSSERegs -= NumElts; 1700360784Sdim 1701360784Sdim // Vectorcall passes HVAs directly and does not flatten them, but regcall 1702360784Sdim // does. 1703360784Sdim if (IsVectorCall) 1704360784Sdim return getDirectX86Hva(); 1705360784Sdim 1706321369Sdim if (Ty->isBuiltinType() || Ty->isVectorType()) 1707280031Sdim return ABIArgInfo::getDirect(); 1708321369Sdim return ABIArgInfo::getExpand(); 1709280031Sdim } 1710321369Sdim return getIndirectResult(Ty, /*ByVal=*/false, State); 1711280031Sdim } 1712280031Sdim 1713212904Sdim if (isAggregateTypeForABI(Ty)) { 1714309124Sdim // Structures with flexible arrays are always indirect. 1715309124Sdim // FIXME: This should not be byval! 1716309124Sdim if (RT && RT->getDecl()->hasFlexibleArrayMember()) 1717309124Sdim return getIndirectResult(Ty, true, State); 1718207619Srdivacky 1719309124Sdim // Ignore empty structs/unions on non-Windows. 1720309124Sdim if (!IsWin32StructABI && isEmptyRecord(getContext(), Ty, true)) 1721202379Srdivacky return ABIArgInfo::getIgnore(); 1722202379Srdivacky 1723243830Sdim llvm::LLVMContext &LLVMContext = getVMContext(); 1724243830Sdim llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext); 1725309124Sdim bool NeedsPadding = false; 1726309124Sdim bool InReg; 1727296417Sdim if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) { 1728243830Sdim unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32; 1729261991Sdim SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32); 1730243830Sdim llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements); 1731296417Sdim if (InReg) 1732296417Sdim return ABIArgInfo::getDirectInReg(Result); 1733296417Sdim else 1734296417Sdim return ABIArgInfo::getDirect(Result); 1735243830Sdim } 1736276479Sdim llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : nullptr; 1737243830Sdim 1738202379Srdivacky // Expand small (<= 128-bit) record types when we know that the stack layout 1739202379Srdivacky // of those arguments will match the struct. This is important because the 1740202379Srdivacky // LLVM backend isn't smart enough to remove byval, which inhibits many 1741202379Srdivacky // optimizations. 1742296417Sdim // Don't do this for the MCU if there are still free integer registers 1743296417Sdim // (see X86_64 ABI for full explanation). 1744309124Sdim if (getContext().getTypeSize(Ty) <= 4 * 32 && 1745309124Sdim (!IsMCUABI || State.FreeRegs == 0) && canExpandIndirectArgument(Ty)) 1746276479Sdim return ABIArgInfo::getExpandWithPadding( 1747360784Sdim IsFastCall || IsVectorCall || IsRegCall, PaddingType); 1748202379Srdivacky 1749276479Sdim return getIndirectResult(Ty, true, State); 1750212904Sdim } 1751203955Srdivacky 1752212904Sdim if (const VectorType *VT = Ty->getAs<VectorType>()) { 1753212904Sdim // On Darwin, some vectors are passed in memory, we handle this by passing 1754212904Sdim // it as an i8/i16/i32/i64. 1755212904Sdim if (IsDarwinVectorABI) { 1756212904Sdim uint64_t Size = getContext().getTypeSize(Ty); 1757212904Sdim if ((Size == 8 || Size == 16 || Size == 32) || 1758212904Sdim (Size == 64 && VT->getNumElements() == 1)) 1759212904Sdim return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 1760212904Sdim Size)); 1761212904Sdim } 1762218893Sdim 1763249423Sdim if (IsX86_MMXType(CGT.ConvertType(Ty))) 1764249423Sdim return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64)); 1765218893Sdim 1766212904Sdim return ABIArgInfo::getDirect(); 1767202379Srdivacky } 1768218893Sdim 1769218893Sdim 1770212904Sdim if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 1771212904Sdim Ty = EnumTy->getDecl()->getIntegerType(); 1772212904Sdim 1773296417Sdim bool InReg = shouldPrimitiveUseInReg(Ty, State); 1774243830Sdim 1775243830Sdim if (Ty->isPromotableIntegerType()) { 1776243830Sdim if (InReg) 1777341825Sdim return ABIArgInfo::getExtendInReg(Ty); 1778341825Sdim return ABIArgInfo::getExtend(Ty); 1779243830Sdim } 1780296417Sdim 1781243830Sdim if (InReg) 1782243830Sdim return ABIArgInfo::getDirectInReg(); 1783243830Sdim return ABIArgInfo::getDirect(); 1784202379Srdivacky} 1785202379Srdivacky 1786239462Sdimvoid X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const { 1787360784Sdim CCState State(FI); 1788296417Sdim if (IsMCUABI) 1789296417Sdim State.FreeRegs = 3; 1790296417Sdim else if (State.CC == llvm::CallingConv::X86_FastCall) 1791276479Sdim State.FreeRegs = 2; 1792280031Sdim else if (State.CC == llvm::CallingConv::X86_VectorCall) { 1793280031Sdim State.FreeRegs = 2; 1794280031Sdim State.FreeSSERegs = 6; 1795280031Sdim } else if (FI.getHasRegParm()) 1796276479Sdim State.FreeRegs = FI.getRegParm(); 1797314564Sdim else if (State.CC == llvm::CallingConv::X86_RegCall) { 1798314564Sdim State.FreeRegs = 5; 1799314564Sdim State.FreeSSERegs = 8; 1800314564Sdim } else 1801276479Sdim State.FreeRegs = DefaultNumRegisterParameters; 1802239462Sdim 1803341825Sdim if (!::classifyReturnType(getCXXABI(), FI, *this)) { 1804276479Sdim FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), State); 1805276479Sdim } else if (FI.getReturnInfo().isIndirect()) { 1806276479Sdim // The C++ ABI is not aware of register usage, so we have to check if the 1807276479Sdim // return value was sret and put it in a register ourselves if appropriate. 1808276479Sdim if (State.FreeRegs) { 1809276479Sdim --State.FreeRegs; // The sret parameter consumes a register. 1810296417Sdim if (!IsMCUABI) 1811296417Sdim FI.getReturnInfo().setInReg(true); 1812276479Sdim } 1813239462Sdim } 1814239462Sdim 1815280031Sdim // The chain argument effectively gives us another free register. 1816280031Sdim if (FI.isChainCall()) 1817280031Sdim ++State.FreeRegs; 1818280031Sdim 1819360784Sdim // For vectorcall, do a first pass over the arguments, assigning FP and vector 1820360784Sdim // arguments to XMM registers as available. 1821360784Sdim if (State.CC == llvm::CallingConv::X86_VectorCall) 1822360784Sdim runVectorCallFirstPass(FI, State); 1823360784Sdim 1824276479Sdim bool UsedInAlloca = false; 1825360784Sdim MutableArrayRef<CGFunctionInfoArgInfo> Args = FI.arguments(); 1826360784Sdim for (int I = 0, E = Args.size(); I < E; ++I) { 1827360784Sdim // Skip arguments that have already been assigned. 1828360784Sdim if (State.IsPreassigned.test(I)) 1829360784Sdim continue; 1830360784Sdim 1831360784Sdim Args[I].info = classifyArgumentType(Args[I].type, State); 1832360784Sdim UsedInAlloca |= (Args[I].info.getKind() == ABIArgInfo::InAlloca); 1833276479Sdim } 1834276479Sdim 1835276479Sdim // If we needed to use inalloca for any argument, do a second pass and rewrite 1836276479Sdim // all the memory arguments to use inalloca. 1837276479Sdim if (UsedInAlloca) 1838276479Sdim rewriteWithInAlloca(FI); 1839239462Sdim} 1840239462Sdim 1841276479Sdimvoid 1842276479SdimX86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields, 1843296417Sdim CharUnits &StackOffset, ABIArgInfo &Info, 1844296417Sdim QualType Type) const { 1845296417Sdim // Arguments are always 4-byte-aligned. 1846296417Sdim CharUnits FieldAlign = CharUnits::fromQuantity(4); 1847296417Sdim 1848296417Sdim assert(StackOffset.isMultipleOf(FieldAlign) && "unaligned inalloca struct"); 1849276479Sdim Info = ABIArgInfo::getInAlloca(FrameFields.size()); 1850276479Sdim FrameFields.push_back(CGT.ConvertTypeForMem(Type)); 1851296417Sdim StackOffset += getContext().getTypeSizeInChars(Type); 1852276479Sdim 1853296417Sdim // Insert padding bytes to respect alignment. 1854296417Sdim CharUnits FieldEnd = StackOffset; 1855309124Sdim StackOffset = FieldEnd.alignTo(FieldAlign); 1856296417Sdim if (StackOffset != FieldEnd) { 1857296417Sdim CharUnits NumBytes = StackOffset - FieldEnd; 1858276479Sdim llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext()); 1859296417Sdim Ty = llvm::ArrayType::get(Ty, NumBytes.getQuantity()); 1860276479Sdim FrameFields.push_back(Ty); 1861276479Sdim } 1862276479Sdim} 1863276479Sdim 1864280031Sdimstatic bool isArgInAlloca(const ABIArgInfo &Info) { 1865280031Sdim // Leave ignored and inreg arguments alone. 1866280031Sdim switch (Info.getKind()) { 1867280031Sdim case ABIArgInfo::InAlloca: 1868280031Sdim return true; 1869280031Sdim case ABIArgInfo::Indirect: 1870280031Sdim assert(Info.getIndirectByVal()); 1871280031Sdim return true; 1872280031Sdim case ABIArgInfo::Ignore: 1873280031Sdim return false; 1874280031Sdim case ABIArgInfo::Direct: 1875280031Sdim case ABIArgInfo::Extend: 1876280031Sdim if (Info.getInReg()) 1877280031Sdim return false; 1878280031Sdim return true; 1879309124Sdim case ABIArgInfo::Expand: 1880309124Sdim case ABIArgInfo::CoerceAndExpand: 1881309124Sdim // These are aggregate types which are never passed in registers when 1882309124Sdim // inalloca is involved. 1883309124Sdim return true; 1884280031Sdim } 1885280031Sdim llvm_unreachable("invalid enum"); 1886280031Sdim} 1887280031Sdim 1888276479Sdimvoid X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const { 1889276479Sdim assert(IsWin32StructABI && "inalloca only supported on win32"); 1890276479Sdim 1891276479Sdim // Build a packed struct type for all of the arguments in memory. 1892276479Sdim SmallVector<llvm::Type *, 6> FrameFields; 1893276479Sdim 1894296417Sdim // The stack alignment is always 4. 1895296417Sdim CharUnits StackAlign = CharUnits::fromQuantity(4); 1896296417Sdim 1897296417Sdim CharUnits StackOffset; 1898280031Sdim CGFunctionInfo::arg_iterator I = FI.arg_begin(), E = FI.arg_end(); 1899276479Sdim 1900280031Sdim // Put 'this' into the struct before 'sret', if necessary. 1901280031Sdim bool IsThisCall = 1902280031Sdim FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall; 1903280031Sdim ABIArgInfo &Ret = FI.getReturnInfo(); 1904280031Sdim if (Ret.isIndirect() && Ret.isSRetAfterThis() && !IsThisCall && 1905280031Sdim isArgInAlloca(I->info)) { 1906280031Sdim addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type); 1907280031Sdim ++I; 1908280031Sdim } 1909280031Sdim 1910276479Sdim // Put the sret parameter into the inalloca struct if it's in memory. 1911276479Sdim if (Ret.isIndirect() && !Ret.getInReg()) { 1912276479Sdim CanQualType PtrTy = getContext().getPointerType(FI.getReturnType()); 1913276479Sdim addFieldToArgStruct(FrameFields, StackOffset, Ret, PtrTy); 1914276479Sdim // On Windows, the hidden sret parameter is always returned in eax. 1915276479Sdim Ret.setInAllocaSRet(IsWin32StructABI); 1916276479Sdim } 1917276479Sdim 1918276479Sdim // Skip the 'this' parameter in ecx. 1919280031Sdim if (IsThisCall) 1920276479Sdim ++I; 1921276479Sdim 1922276479Sdim // Put arguments passed in memory into the struct. 1923276479Sdim for (; I != E; ++I) { 1924280031Sdim if (isArgInAlloca(I->info)) 1925280031Sdim addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type); 1926276479Sdim } 1927276479Sdim 1928276479Sdim FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields, 1929296417Sdim /*isPacked=*/true), 1930296417Sdim StackAlign); 1931276479Sdim} 1932276479Sdim 1933296417SdimAddress X86_32ABIInfo::EmitVAArg(CodeGenFunction &CGF, 1934296417Sdim Address VAListAddr, QualType Ty) const { 1935202379Srdivacky 1936296417Sdim auto TypeInfo = getContext().getTypeInfoInChars(Ty); 1937234353Sdim 1938296417Sdim // x86-32 changes the alignment of certain arguments on the stack. 1939296417Sdim // 1940296417Sdim // Just messing with TypeInfo like this works because we never pass 1941296417Sdim // anything indirectly. 1942296417Sdim TypeInfo.second = CharUnits::fromQuantity( 1943296417Sdim getTypeStackAlignInBytes(Ty, TypeInfo.second.getQuantity())); 1944234353Sdim 1945296417Sdim return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false, 1946296417Sdim TypeInfo, CharUnits::fromQuantity(4), 1947296417Sdim /*AllowHigherAlign*/ true); 1948202379Srdivacky} 1949202379Srdivacky 1950276479Sdimbool X86_32TargetCodeGenInfo::isStructReturnInRegABI( 1951276479Sdim const llvm::Triple &Triple, const CodeGenOptions &Opts) { 1952276479Sdim assert(Triple.getArch() == llvm::Triple::x86); 1953276479Sdim 1954276479Sdim switch (Opts.getStructReturnConvention()) { 1955276479Sdim case CodeGenOptions::SRCK_Default: 1956276479Sdim break; 1957276479Sdim case CodeGenOptions::SRCK_OnStack: // -fpcc-struct-return 1958276479Sdim return false; 1959276479Sdim case CodeGenOptions::SRCK_InRegs: // -freg-struct-return 1960276479Sdim return true; 1961276479Sdim } 1962276479Sdim 1963296417Sdim if (Triple.isOSDarwin() || Triple.isOSIAMCU()) 1964276479Sdim return true; 1965276479Sdim 1966276479Sdim switch (Triple.getOS()) { 1967276479Sdim case llvm::Triple::DragonFly: 1968276479Sdim case llvm::Triple::FreeBSD: 1969276479Sdim case llvm::Triple::OpenBSD: 1970280031Sdim case llvm::Triple::Win32: 1971276479Sdim return true; 1972276479Sdim default: 1973276479Sdim return false; 1974276479Sdim } 1975276479Sdim} 1976276479Sdim 1977327952Sdimvoid X86_32TargetCodeGenInfo::setTargetAttributes( 1978341825Sdim const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const { 1979341825Sdim if (GV->isDeclaration()) 1980327952Sdim return; 1981296417Sdim if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) { 1982203955Srdivacky if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) { 1983203955Srdivacky llvm::Function *Fn = cast<llvm::Function>(GV); 1984335799Sdim Fn->addFnAttr("stackrealign"); 1985203955Srdivacky } 1986309124Sdim if (FD->hasAttr<AnyX86InterruptAttr>()) { 1987309124Sdim llvm::Function *Fn = cast<llvm::Function>(GV); 1988309124Sdim Fn->setCallingConv(llvm::CallingConv::X86_INTR); 1989309124Sdim } 1990203955Srdivacky } 1991203955Srdivacky} 1992203955Srdivacky 1993204793Srdivackybool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable( 1994204793Srdivacky CodeGen::CodeGenFunction &CGF, 1995204793Srdivacky llvm::Value *Address) const { 1996204793Srdivacky CodeGen::CGBuilderTy &Builder = CGF.Builder; 1997204793Srdivacky 1998234353Sdim llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4); 1999212904Sdim 2000204793Srdivacky // 0-7 are the eight integer registers; the order is different 2001204793Srdivacky // on Darwin (for EH), but the range is the same. 2002204793Srdivacky // 8 is %eip. 2003208600Srdivacky AssignToArrayRange(Builder, Address, Four8, 0, 8); 2004204793Srdivacky 2005251662Sdim if (CGF.CGM.getTarget().getTriple().isOSDarwin()) { 2006204793Srdivacky // 12-16 are st(0..4). Not sure why we stop at 4. 2007204793Srdivacky // These have size 16, which is sizeof(long double) on 2008204793Srdivacky // platforms with 8-byte alignment for that type. 2009234353Sdim llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16); 2010208600Srdivacky AssignToArrayRange(Builder, Address, Sixteen8, 12, 16); 2011212904Sdim 2012204793Srdivacky } else { 2013204793Srdivacky // 9 is %eflags, which doesn't get a size on Darwin for some 2014204793Srdivacky // reason. 2015296417Sdim Builder.CreateAlignedStore( 2016296417Sdim Four8, Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, Address, 9), 2017296417Sdim CharUnits::One()); 2018204793Srdivacky 2019204793Srdivacky // 11-16 are st(0..5). Not sure why we stop at 5. 2020204793Srdivacky // These have size 12, which is sizeof(long double) on 2021204793Srdivacky // platforms with 4-byte alignment for that type. 2022234353Sdim llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12); 2023208600Srdivacky AssignToArrayRange(Builder, Address, Twelve8, 11, 16); 2024208600Srdivacky } 2025204793Srdivacky 2026204793Srdivacky return false; 2027204793Srdivacky} 2028204793Srdivacky 2029210299Sed//===----------------------------------------------------------------------===// 2030210299Sed// X86-64 ABI Implementation 2031210299Sed//===----------------------------------------------------------------------===// 2032210299Sed 2033210299Sed 2034202379Srdivackynamespace { 2035288943Sdim/// The AVX ABI level for X86 targets. 2036288943Sdimenum class X86AVXABILevel { 2037288943Sdim None, 2038288943Sdim AVX, 2039288943Sdim AVX512 2040288943Sdim}; 2041288943Sdim 2042288943Sdim/// \p returns the size in bits of the largest (native) vector for \p AVXLevel. 2043288943Sdimstatic unsigned getNativeVectorSizeForAVXABI(X86AVXABILevel AVXLevel) { 2044288943Sdim switch (AVXLevel) { 2045288943Sdim case X86AVXABILevel::AVX512: 2046288943Sdim return 512; 2047288943Sdim case X86AVXABILevel::AVX: 2048288943Sdim return 256; 2049288943Sdim case X86AVXABILevel::None: 2050288943Sdim return 128; 2051288943Sdim } 2052288943Sdim llvm_unreachable("Unknown AVXLevel"); 2053288943Sdim} 2054288943Sdim 2055202379Srdivacky/// X86_64ABIInfo - The X86_64 ABI information. 2056309124Sdimclass X86_64ABIInfo : public SwiftABIInfo { 2057202379Srdivacky enum Class { 2058202379Srdivacky Integer = 0, 2059202379Srdivacky SSE, 2060202379Srdivacky SSEUp, 2061202379Srdivacky X87, 2062202379Srdivacky X87Up, 2063202379Srdivacky ComplexX87, 2064202379Srdivacky NoClass, 2065202379Srdivacky Memory 2066202379Srdivacky }; 2067202379Srdivacky 2068202379Srdivacky /// merge - Implement the X86_64 ABI merging algorithm. 2069202379Srdivacky /// 2070202379Srdivacky /// Merge an accumulating classification \arg Accum with a field 2071202379Srdivacky /// classification \arg Field. 2072202379Srdivacky /// 2073202379Srdivacky /// \param Accum - The accumulating classification. This should 2074202379Srdivacky /// always be either NoClass or the result of a previous merge 2075202379Srdivacky /// call. In addition, this should never be Memory (the caller 2076202379Srdivacky /// should just return Memory for the aggregate). 2077210299Sed static Class merge(Class Accum, Class Field); 2078202379Srdivacky 2079224145Sdim /// postMerge - Implement the X86_64 ABI post merging algorithm. 2080224145Sdim /// 2081224145Sdim /// Post merger cleanup, reduces a malformed Hi and Lo pair to 2082224145Sdim /// final MEMORY or SSE classes when necessary. 2083224145Sdim /// 2084224145Sdim /// \param AggregateSize - The size of the current aggregate in 2085224145Sdim /// the classification process. 2086224145Sdim /// 2087224145Sdim /// \param Lo - The classification for the parts of the type 2088224145Sdim /// residing in the low word of the containing object. 2089224145Sdim /// 2090224145Sdim /// \param Hi - The classification for the parts of the type 2091224145Sdim /// residing in the higher words of the containing object. 2092224145Sdim /// 2093224145Sdim void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const; 2094224145Sdim 2095202379Srdivacky /// classify - Determine the x86_64 register classes in which the 2096202379Srdivacky /// given type T should be passed. 2097202379Srdivacky /// 2098202379Srdivacky /// \param Lo - The classification for the parts of the type 2099202379Srdivacky /// residing in the low word of the containing object. 2100202379Srdivacky /// 2101202379Srdivacky /// \param Hi - The classification for the parts of the type 2102202379Srdivacky /// residing in the high word of the containing object. 2103202379Srdivacky /// 2104202379Srdivacky /// \param OffsetBase - The bit offset of this type in the 2105202379Srdivacky /// containing object. Some parameters are classified different 2106202379Srdivacky /// depending on whether they straddle an eightbyte boundary. 2107202379Srdivacky /// 2108261991Sdim /// \param isNamedArg - Whether the argument in question is a "named" 2109261991Sdim /// argument, as used in AMD64-ABI 3.5.7. 2110261991Sdim /// 2111202379Srdivacky /// If a word is unused its result will be NoClass; if a type should 2112202379Srdivacky /// be passed in Memory then at least the classification of \arg Lo 2113202379Srdivacky /// will be Memory. 2114202379Srdivacky /// 2115202379Srdivacky /// The \arg Lo class will be NoClass iff the argument is ignored. 2116202379Srdivacky /// 2117202379Srdivacky /// If the \arg Lo class is ComplexX87, then the \arg Hi class will 2118202379Srdivacky /// also be ComplexX87. 2119261991Sdim void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi, 2120261991Sdim bool isNamedArg) const; 2121202379Srdivacky 2122224145Sdim llvm::Type *GetByteVectorType(QualType Ty) const; 2123224145Sdim llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType, 2124224145Sdim unsigned IROffset, QualType SourceTy, 2125224145Sdim unsigned SourceOffset) const; 2126224145Sdim llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType, 2127224145Sdim unsigned IROffset, QualType SourceTy, 2128224145Sdim unsigned SourceOffset) const; 2129202379Srdivacky 2130202379Srdivacky /// getIndirectResult - Give a source type \arg Ty, return a suitable result 2131207619Srdivacky /// such that the argument will be returned in memory. 2132210299Sed ABIArgInfo getIndirectReturnResult(QualType Ty) const; 2133207619Srdivacky 2134207619Srdivacky /// getIndirectResult - Give a source type \arg Ty, return a suitable result 2135202379Srdivacky /// such that the argument will be passed in memory. 2136234353Sdim /// 2137234353Sdim /// \param freeIntRegs - The number of free integer registers remaining 2138234353Sdim /// available. 2139234353Sdim ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const; 2140202379Srdivacky 2141212904Sdim ABIArgInfo classifyReturnType(QualType RetTy) const; 2142202379Srdivacky 2143314564Sdim ABIArgInfo classifyArgumentType(QualType Ty, unsigned freeIntRegs, 2144314564Sdim unsigned &neededInt, unsigned &neededSSE, 2145261991Sdim bool isNamedArg) const; 2146202379Srdivacky 2147314564Sdim ABIArgInfo classifyRegCallStructType(QualType Ty, unsigned &NeededInt, 2148314564Sdim unsigned &NeededSSE) const; 2149314564Sdim 2150314564Sdim ABIArgInfo classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt, 2151314564Sdim unsigned &NeededSSE) const; 2152314564Sdim 2153234353Sdim bool IsIllegalVectorType(QualType Ty) const; 2154234353Sdim 2155221345Sdim /// The 0.98 ABI revision clarified a lot of ambiguities, 2156221345Sdim /// unfortunately in ways that were not always consistent with 2157221345Sdim /// certain previous compilers. In particular, platforms which 2158221345Sdim /// required strict binary compatibility with older versions of GCC 2159221345Sdim /// may need to exempt themselves. 2160221345Sdim bool honorsRevision0_98() const { 2161251662Sdim return !getTarget().getTriple().isOSDarwin(); 2162221345Sdim } 2163221345Sdim 2164323112Sdim /// GCC classifies <1 x long long> as SSE but some platform ABIs choose to 2165323112Sdim /// classify it as INTEGER (for compatibility with older clang compilers). 2166309124Sdim bool classifyIntegerMMXAsSSE() const { 2167323112Sdim // Clang <= 3.8 did not do this. 2168341825Sdim if (getContext().getLangOpts().getClangABICompat() <= 2169341825Sdim LangOptions::ClangABI::Ver3_8) 2170323112Sdim return false; 2171323112Sdim 2172309124Sdim const llvm::Triple &Triple = getTarget().getTriple(); 2173309124Sdim if (Triple.isOSDarwin() || Triple.getOS() == llvm::Triple::PS4) 2174309124Sdim return false; 2175309124Sdim if (Triple.isOSFreeBSD() && Triple.getOSMajorVersion() >= 10) 2176309124Sdim return false; 2177309124Sdim return true; 2178309124Sdim } 2179309124Sdim 2180360784Sdim // GCC classifies vectors of __int128 as memory. 2181360784Sdim bool passInt128VectorsInMem() const { 2182360784Sdim // Clang <= 9.0 did not do this. 2183360784Sdim if (getContext().getLangOpts().getClangABICompat() <= 2184360784Sdim LangOptions::ClangABI::Ver9) 2185360784Sdim return false; 2186360784Sdim 2187360784Sdim const llvm::Triple &T = getTarget().getTriple(); 2188360784Sdim return T.isOSLinux() || T.isOSNetBSD(); 2189360784Sdim } 2190360784Sdim 2191288943Sdim X86AVXABILevel AVXLevel; 2192243830Sdim // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on 2193243830Sdim // 64-bit hardware. 2194243830Sdim bool Has64BitPointers; 2195234353Sdim 2196202379Srdivackypublic: 2197288943Sdim X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) : 2198309124Sdim SwiftABIInfo(CGT), AVXLevel(AVXLevel), 2199243830Sdim Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) { 2200243830Sdim } 2201210299Sed 2202234353Sdim bool isPassedUsingAVXType(QualType type) const { 2203234353Sdim unsigned neededInt, neededSSE; 2204234353Sdim // The freeIntRegs argument doesn't matter here. 2205261991Sdim ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE, 2206261991Sdim /*isNamedArg*/true); 2207234353Sdim if (info.isDirect()) { 2208234353Sdim llvm::Type *ty = info.getCoerceToType(); 2209234353Sdim if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty)) 2210234353Sdim return (vectorTy->getBitWidth() > 128); 2211234353Sdim } 2212234353Sdim return false; 2213234353Sdim } 2214234353Sdim 2215276479Sdim void computeInfo(CGFunctionInfo &FI) const override; 2216202379Srdivacky 2217296417Sdim Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 2218296417Sdim QualType Ty) const override; 2219296417Sdim Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr, 2220296417Sdim QualType Ty) const override; 2221288943Sdim 2222288943Sdim bool has64BitPointers() const { 2223288943Sdim return Has64BitPointers; 2224288943Sdim } 2225309124Sdim 2226341825Sdim bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars, 2227309124Sdim bool asReturnValue) const override { 2228309124Sdim return occupiesMoreThan(CGT, scalars, /*total*/ 4); 2229341825Sdim } 2230314564Sdim bool isSwiftErrorInRegister() const override { 2231314564Sdim return true; 2232314564Sdim } 2233202379Srdivacky}; 2234202379Srdivacky 2235212904Sdim/// WinX86_64ABIInfo - The Windows X86_64 ABI information. 2236314564Sdimclass WinX86_64ABIInfo : public SwiftABIInfo { 2237212904Sdimpublic: 2238353358Sdim WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) 2239353358Sdim : SwiftABIInfo(CGT), AVXLevel(AVXLevel), 2240292735Sdim IsMingw64(getTarget().getTriple().isWindowsGNUEnvironment()) {} 2241212904Sdim 2242276479Sdim void computeInfo(CGFunctionInfo &FI) const override; 2243218893Sdim 2244296417Sdim Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 2245296417Sdim QualType Ty) const override; 2246280031Sdim 2247280031Sdim bool isHomogeneousAggregateBaseType(QualType Ty) const override { 2248280031Sdim // FIXME: Assumes vectorcall is in use. 2249280031Sdim return isX86VectorTypeForVectorCall(getContext(), Ty); 2250280031Sdim } 2251280031Sdim 2252280031Sdim bool isHomogeneousAggregateSmallEnough(const Type *Ty, 2253280031Sdim uint64_t NumMembers) const override { 2254280031Sdim // FIXME: Assumes vectorcall is in use. 2255280031Sdim return isX86VectorCallAggregateSmallEnough(NumMembers); 2256280031Sdim } 2257292735Sdim 2258341825Sdim bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type *> scalars, 2259314564Sdim bool asReturnValue) const override { 2260314564Sdim return occupiesMoreThan(CGT, scalars, /*total*/ 4); 2261314564Sdim } 2262314564Sdim 2263314564Sdim bool isSwiftErrorInRegister() const override { 2264314564Sdim return true; 2265314564Sdim } 2266314564Sdim 2267292735Sdimprivate: 2268314564Sdim ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs, bool IsReturnType, 2269314564Sdim bool IsVectorCall, bool IsRegCall) const; 2270314564Sdim ABIArgInfo reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs, 2271314564Sdim const ABIArgInfo ¤t) const; 2272314564Sdim void computeVectorCallArgs(CGFunctionInfo &FI, unsigned FreeSSERegs, 2273314564Sdim bool IsVectorCall, bool IsRegCall) const; 2274292735Sdim 2275353358Sdim X86AVXABILevel AVXLevel; 2276353358Sdim 2277353358Sdim bool IsMingw64; 2278212904Sdim}; 2279212904Sdim 2280202379Srdivackyclass X86_64TargetCodeGenInfo : public TargetCodeGenInfo { 2281202379Srdivackypublic: 2282288943Sdim X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) 2283288943Sdim : TargetCodeGenInfo(new X86_64ABIInfo(CGT, AVXLevel)) {} 2284204793Srdivacky 2285234353Sdim const X86_64ABIInfo &getABIInfo() const { 2286234353Sdim return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo()); 2287234353Sdim } 2288234353Sdim 2289353358Sdim /// Disable tail call on x86-64. The epilogue code before the tail jump blocks 2290353358Sdim /// the autoreleaseRV/retainRV optimization. 2291353358Sdim bool shouldSuppressTailCallsOfRetainAutoreleasedReturnValue() const override { 2292353358Sdim return true; 2293353358Sdim } 2294353358Sdim 2295276479Sdim int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override { 2296204793Srdivacky return 7; 2297204793Srdivacky } 2298204793Srdivacky 2299204793Srdivacky bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2300276479Sdim llvm::Value *Address) const override { 2301234353Sdim llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8); 2302204793Srdivacky 2303212904Sdim // 0-15 are the 16 integer registers. 2304212904Sdim // 16 is %rip. 2305234353Sdim AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16); 2306212904Sdim return false; 2307212904Sdim } 2308218893Sdim 2309224145Sdim llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF, 2310226633Sdim StringRef Constraint, 2311276479Sdim llvm::Type* Ty) const override { 2312218893Sdim return X86AdjustInlineAsmType(CGF, Constraint, Ty); 2313218893Sdim } 2314218893Sdim 2315234353Sdim bool isNoProtoCallVariadic(const CallArgList &args, 2316276479Sdim const FunctionNoProtoType *fnType) const override { 2317226633Sdim // The default CC on x86-64 sets %al to the number of SSA 2318226633Sdim // registers used, and GCC sets this when calling an unprototyped 2319234353Sdim // function, so we override the default behavior. However, don't do 2320234353Sdim // that when AVX types are involved: the ABI explicitly states it is 2321234353Sdim // undefined, and it doesn't work in practice because of how the ABI 2322234353Sdim // defines varargs anyway. 2323261991Sdim if (fnType->getCallConv() == CC_C) { 2324234353Sdim bool HasAVXType = false; 2325234353Sdim for (CallArgList::const_iterator 2326234353Sdim it = args.begin(), ie = args.end(); it != ie; ++it) { 2327234353Sdim if (getABIInfo().isPassedUsingAVXType(it->Ty)) { 2328234353Sdim HasAVXType = true; 2329234353Sdim break; 2330234353Sdim } 2331234353Sdim } 2332226633Sdim 2333234353Sdim if (!HasAVXType) 2334234353Sdim return true; 2335234353Sdim } 2336234353Sdim 2337234353Sdim return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType); 2338226633Sdim } 2339226633Sdim 2340276479Sdim llvm::Constant * 2341276479Sdim getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override { 2342327952Sdim unsigned Sig = (0xeb << 0) | // jmp rel8 2343327952Sdim (0x06 << 8) | // .+0x08 2344327952Sdim ('v' << 16) | 2345327952Sdim ('2' << 24); 2346261991Sdim return llvm::ConstantInt::get(CGM.Int32Ty, Sig); 2347261991Sdim } 2348309124Sdim 2349309124Sdim void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 2350341825Sdim CodeGen::CodeGenModule &CGM) const override { 2351341825Sdim if (GV->isDeclaration()) 2352327952Sdim return; 2353309124Sdim if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) { 2354327952Sdim if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) { 2355335799Sdim llvm::Function *Fn = cast<llvm::Function>(GV); 2356335799Sdim Fn->addFnAttr("stackrealign"); 2357327952Sdim } 2358309124Sdim if (FD->hasAttr<AnyX86InterruptAttr>()) { 2359309124Sdim llvm::Function *Fn = cast<llvm::Function>(GV); 2360309124Sdim Fn->setCallingConv(llvm::CallingConv::X86_INTR); 2361309124Sdim } 2362309124Sdim } 2363309124Sdim } 2364288943Sdim}; 2365261991Sdim 2366261991Sdimstatic std::string qualifyWindowsLibrary(llvm::StringRef Lib) { 2367288943Sdim // If the argument does not end in .lib, automatically add the suffix. 2368288943Sdim // If the argument contains a space, enclose it in quotes. 2369288943Sdim // This matches the behavior of MSVC. 2370288943Sdim bool Quote = (Lib.find(" ") != StringRef::npos); 2371288943Sdim std::string ArgStr = Quote ? "\"" : ""; 2372288943Sdim ArgStr += Lib; 2373344779Sdim if (!Lib.endswith_lower(".lib") && !Lib.endswith_lower(".a")) 2374261991Sdim ArgStr += ".lib"; 2375288943Sdim ArgStr += Quote ? "\"" : ""; 2376261991Sdim return ArgStr; 2377261991Sdim} 2378261991Sdim 2379261991Sdimclass WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo { 2380261991Sdimpublic: 2381261991Sdim WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, 2382296417Sdim bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI, 2383296417Sdim unsigned NumRegisterParameters) 2384296417Sdim : X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI, 2385296417Sdim Win32StructABI, NumRegisterParameters, false) {} 2386261991Sdim 2387288943Sdim void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 2388341825Sdim CodeGen::CodeGenModule &CGM) const override; 2389288943Sdim 2390261991Sdim void getDependentLibraryOption(llvm::StringRef Lib, 2391276479Sdim llvm::SmallString<24> &Opt) const override { 2392261991Sdim Opt = "/DEFAULTLIB:"; 2393261991Sdim Opt += qualifyWindowsLibrary(Lib); 2394261991Sdim } 2395261991Sdim 2396261991Sdim void getDetectMismatchOption(llvm::StringRef Name, 2397261991Sdim llvm::StringRef Value, 2398276479Sdim llvm::SmallString<32> &Opt) const override { 2399261991Sdim Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\""; 2400261991Sdim } 2401261991Sdim}; 2402261991Sdim 2403341825Sdimstatic void addStackProbeTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 2404341825Sdim CodeGen::CodeGenModule &CGM) { 2405341825Sdim if (llvm::Function *Fn = dyn_cast_or_null<llvm::Function>(GV)) { 2406288943Sdim 2407341825Sdim if (CGM.getCodeGenOpts().StackProbeSize != 4096) 2408288943Sdim Fn->addFnAttr("stack-probe-size", 2409288943Sdim llvm::utostr(CGM.getCodeGenOpts().StackProbeSize)); 2410341825Sdim if (CGM.getCodeGenOpts().NoStackArgProbe) 2411341825Sdim Fn->addFnAttr("no-stack-arg-probe"); 2412288943Sdim } 2413288943Sdim} 2414288943Sdim 2415327952Sdimvoid WinX86_32TargetCodeGenInfo::setTargetAttributes( 2416341825Sdim const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const { 2417341825Sdim X86_32TargetCodeGenInfo::setTargetAttributes(D, GV, CGM); 2418341825Sdim if (GV->isDeclaration()) 2419327952Sdim return; 2420341825Sdim addStackProbeTargetAttributes(D, GV, CGM); 2421288943Sdim} 2422288943Sdim 2423212904Sdimclass WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo { 2424212904Sdimpublic: 2425288943Sdim WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, 2426288943Sdim X86AVXABILevel AVXLevel) 2427353358Sdim : TargetCodeGenInfo(new WinX86_64ABIInfo(CGT, AVXLevel)) {} 2428212904Sdim 2429288943Sdim void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 2430341825Sdim CodeGen::CodeGenModule &CGM) const override; 2431288943Sdim 2432276479Sdim int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override { 2433212904Sdim return 7; 2434212904Sdim } 2435212904Sdim 2436212904Sdim bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2437276479Sdim llvm::Value *Address) const override { 2438234353Sdim llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8); 2439212904Sdim 2440208600Srdivacky // 0-15 are the 16 integer registers. 2441208600Srdivacky // 16 is %rip. 2442234353Sdim AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16); 2443204793Srdivacky return false; 2444204793Srdivacky } 2445261991Sdim 2446261991Sdim void getDependentLibraryOption(llvm::StringRef Lib, 2447276479Sdim llvm::SmallString<24> &Opt) const override { 2448261991Sdim Opt = "/DEFAULTLIB:"; 2449261991Sdim Opt += qualifyWindowsLibrary(Lib); 2450261991Sdim } 2451261991Sdim 2452261991Sdim void getDetectMismatchOption(llvm::StringRef Name, 2453261991Sdim llvm::StringRef Value, 2454276479Sdim llvm::SmallString<32> &Opt) const override { 2455261991Sdim Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\""; 2456261991Sdim } 2457202379Srdivacky}; 2458202379Srdivacky 2459327952Sdimvoid WinX86_64TargetCodeGenInfo::setTargetAttributes( 2460341825Sdim const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const { 2461341825Sdim TargetCodeGenInfo::setTargetAttributes(D, GV, CGM); 2462341825Sdim if (GV->isDeclaration()) 2463327952Sdim return; 2464327952Sdim if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) { 2465327952Sdim if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) { 2466335799Sdim llvm::Function *Fn = cast<llvm::Function>(GV); 2467335799Sdim Fn->addFnAttr("stackrealign"); 2468327952Sdim } 2469309124Sdim if (FD->hasAttr<AnyX86InterruptAttr>()) { 2470309124Sdim llvm::Function *Fn = cast<llvm::Function>(GV); 2471309124Sdim Fn->setCallingConv(llvm::CallingConv::X86_INTR); 2472309124Sdim } 2473309124Sdim } 2474309124Sdim 2475341825Sdim addStackProbeTargetAttributes(D, GV, CGM); 2476202379Srdivacky} 2477288943Sdim} 2478202379Srdivacky 2479224145Sdimvoid X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo, 2480224145Sdim Class &Hi) const { 2481224145Sdim // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done: 2482224145Sdim // 2483224145Sdim // (a) If one of the classes is Memory, the whole argument is passed in 2484224145Sdim // memory. 2485224145Sdim // 2486224145Sdim // (b) If X87UP is not preceded by X87, the whole argument is passed in 2487224145Sdim // memory. 2488224145Sdim // 2489224145Sdim // (c) If the size of the aggregate exceeds two eightbytes and the first 2490224145Sdim // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole 2491224145Sdim // argument is passed in memory. NOTE: This is necessary to keep the 2492224145Sdim // ABI working for processors that don't support the __m256 type. 2493224145Sdim // 2494224145Sdim // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE. 2495224145Sdim // 2496224145Sdim // Some of these are enforced by the merging logic. Others can arise 2497224145Sdim // only with unions; for example: 2498224145Sdim // union { _Complex double; unsigned; } 2499224145Sdim // 2500224145Sdim // Note that clauses (b) and (c) were added in 0.98. 2501224145Sdim // 2502224145Sdim if (Hi == Memory) 2503224145Sdim Lo = Memory; 2504224145Sdim if (Hi == X87Up && Lo != X87 && honorsRevision0_98()) 2505224145Sdim Lo = Memory; 2506224145Sdim if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp)) 2507224145Sdim Lo = Memory; 2508224145Sdim if (Hi == SSEUp && Lo != SSE) 2509224145Sdim Hi = SSE; 2510224145Sdim} 2511224145Sdim 2512210299SedX86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) { 2513202379Srdivacky // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is 2514202379Srdivacky // classified recursively so that always two fields are 2515202379Srdivacky // considered. The resulting class is calculated according to 2516202379Srdivacky // the classes of the fields in the eightbyte: 2517202379Srdivacky // 2518202379Srdivacky // (a) If both classes are equal, this is the resulting class. 2519202379Srdivacky // 2520202379Srdivacky // (b) If one of the classes is NO_CLASS, the resulting class is 2521202379Srdivacky // the other class. 2522202379Srdivacky // 2523202379Srdivacky // (c) If one of the classes is MEMORY, the result is the MEMORY 2524202379Srdivacky // class. 2525202379Srdivacky // 2526202379Srdivacky // (d) If one of the classes is INTEGER, the result is the 2527202379Srdivacky // INTEGER. 2528202379Srdivacky // 2529202379Srdivacky // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class, 2530202379Srdivacky // MEMORY is used as class. 2531202379Srdivacky // 2532202379Srdivacky // (f) Otherwise class SSE is used. 2533202379Srdivacky 2534202379Srdivacky // Accum should never be memory (we should have returned) or 2535202379Srdivacky // ComplexX87 (because this cannot be passed in a structure). 2536202379Srdivacky assert((Accum != Memory && Accum != ComplexX87) && 2537202379Srdivacky "Invalid accumulated classification during merge."); 2538202379Srdivacky if (Accum == Field || Field == NoClass) 2539202379Srdivacky return Accum; 2540210299Sed if (Field == Memory) 2541202379Srdivacky return Memory; 2542210299Sed if (Accum == NoClass) 2543202379Srdivacky return Field; 2544210299Sed if (Accum == Integer || Field == Integer) 2545202379Srdivacky return Integer; 2546210299Sed if (Field == X87 || Field == X87Up || Field == ComplexX87 || 2547210299Sed Accum == X87 || Accum == X87Up) 2548202379Srdivacky return Memory; 2549210299Sed return SSE; 2550202379Srdivacky} 2551202379Srdivacky 2552210299Sedvoid X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase, 2553261991Sdim Class &Lo, Class &Hi, bool isNamedArg) const { 2554202379Srdivacky // FIXME: This code can be simplified by introducing a simple value class for 2555202379Srdivacky // Class pairs with appropriate constructor methods for the various 2556202379Srdivacky // situations. 2557202379Srdivacky 2558202379Srdivacky // FIXME: Some of the split computations are wrong; unaligned vectors 2559202379Srdivacky // shouldn't be passed in registers for example, so there is no chance they 2560202379Srdivacky // can straddle an eightbyte. Verify & simplify. 2561202379Srdivacky 2562202379Srdivacky Lo = Hi = NoClass; 2563202379Srdivacky 2564202379Srdivacky Class &Current = OffsetBase < 64 ? Lo : Hi; 2565202379Srdivacky Current = Memory; 2566202379Srdivacky 2567202379Srdivacky if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) { 2568202379Srdivacky BuiltinType::Kind k = BT->getKind(); 2569202379Srdivacky 2570202379Srdivacky if (k == BuiltinType::Void) { 2571202379Srdivacky Current = NoClass; 2572202379Srdivacky } else if (k == BuiltinType::Int128 || k == BuiltinType::UInt128) { 2573202379Srdivacky Lo = Integer; 2574202379Srdivacky Hi = Integer; 2575202379Srdivacky } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) { 2576202379Srdivacky Current = Integer; 2577288943Sdim } else if (k == BuiltinType::Float || k == BuiltinType::Double) { 2578202379Srdivacky Current = SSE; 2579202379Srdivacky } else if (k == BuiltinType::LongDouble) { 2580288943Sdim const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat(); 2581314564Sdim if (LDF == &llvm::APFloat::IEEEquad()) { 2582288943Sdim Lo = SSE; 2583288943Sdim Hi = SSEUp; 2584314564Sdim } else if (LDF == &llvm::APFloat::x87DoubleExtended()) { 2585288943Sdim Lo = X87; 2586288943Sdim Hi = X87Up; 2587314564Sdim } else if (LDF == &llvm::APFloat::IEEEdouble()) { 2588288943Sdim Current = SSE; 2589288943Sdim } else 2590288943Sdim llvm_unreachable("unexpected long double representation!"); 2591202379Srdivacky } 2592202379Srdivacky // FIXME: _Decimal32 and _Decimal64 are SSE. 2593202379Srdivacky // FIXME: _float128 and _Decimal128 are (SSE, SSEUp). 2594210299Sed return; 2595210299Sed } 2596212904Sdim 2597210299Sed if (const EnumType *ET = Ty->getAs<EnumType>()) { 2598202379Srdivacky // Classify the underlying integer type. 2599261991Sdim classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg); 2600210299Sed return; 2601210299Sed } 2602212904Sdim 2603210299Sed if (Ty->hasPointerRepresentation()) { 2604202379Srdivacky Current = Integer; 2605210299Sed return; 2606210299Sed } 2607212904Sdim 2608210299Sed if (Ty->isMemberPointerType()) { 2609280031Sdim if (Ty->isMemberFunctionPointerType()) { 2610280031Sdim if (Has64BitPointers) { 2611280031Sdim // If Has64BitPointers, this is an {i64, i64}, so classify both 2612280031Sdim // Lo and Hi now. 2613280031Sdim Lo = Hi = Integer; 2614280031Sdim } else { 2615280031Sdim // Otherwise, with 32-bit pointers, this is an {i32, i32}. If that 2616280031Sdim // straddles an eightbyte boundary, Hi should be classified as well. 2617280031Sdim uint64_t EB_FuncPtr = (OffsetBase) / 64; 2618280031Sdim uint64_t EB_ThisAdj = (OffsetBase + 64 - 1) / 64; 2619280031Sdim if (EB_FuncPtr != EB_ThisAdj) { 2620280031Sdim Lo = Hi = Integer; 2621280031Sdim } else { 2622280031Sdim Current = Integer; 2623280031Sdim } 2624280031Sdim } 2625280031Sdim } else { 2626208600Srdivacky Current = Integer; 2627280031Sdim } 2628210299Sed return; 2629210299Sed } 2630212904Sdim 2631210299Sed if (const VectorType *VT = Ty->getAs<VectorType>()) { 2632212904Sdim uint64_t Size = getContext().getTypeSize(VT); 2633296417Sdim if (Size == 1 || Size == 8 || Size == 16 || Size == 32) { 2634296417Sdim // gcc passes the following as integer: 2635296417Sdim // 4 bytes - <4 x char>, <2 x short>, <1 x int>, <1 x float> 2636296417Sdim // 2 bytes - <2 x char>, <1 x short> 2637296417Sdim // 1 byte - <1 x char> 2638202379Srdivacky Current = Integer; 2639202379Srdivacky 2640202379Srdivacky // If this type crosses an eightbyte boundary, it should be 2641202379Srdivacky // split. 2642296417Sdim uint64_t EB_Lo = (OffsetBase) / 64; 2643296417Sdim uint64_t EB_Hi = (OffsetBase + Size - 1) / 64; 2644296417Sdim if (EB_Lo != EB_Hi) 2645202379Srdivacky Hi = Lo; 2646202379Srdivacky } else if (Size == 64) { 2647309124Sdim QualType ElementType = VT->getElementType(); 2648309124Sdim 2649202379Srdivacky // gcc passes <1 x double> in memory. :( 2650309124Sdim if (ElementType->isSpecificBuiltinType(BuiltinType::Double)) 2651202379Srdivacky return; 2652202379Srdivacky 2653309124Sdim // gcc passes <1 x long long> as SSE but clang used to unconditionally 2654309124Sdim // pass them as integer. For platforms where clang is the de facto 2655309124Sdim // platform compiler, we must continue to use integer. 2656309124Sdim if (!classifyIntegerMMXAsSSE() && 2657309124Sdim (ElementType->isSpecificBuiltinType(BuiltinType::LongLong) || 2658309124Sdim ElementType->isSpecificBuiltinType(BuiltinType::ULongLong) || 2659309124Sdim ElementType->isSpecificBuiltinType(BuiltinType::Long) || 2660309124Sdim ElementType->isSpecificBuiltinType(BuiltinType::ULong))) 2661202379Srdivacky Current = Integer; 2662202379Srdivacky else 2663202379Srdivacky Current = SSE; 2664202379Srdivacky 2665202379Srdivacky // If this type crosses an eightbyte boundary, it should be 2666202379Srdivacky // split. 2667202379Srdivacky if (OffsetBase && OffsetBase != 64) 2668202379Srdivacky Hi = Lo; 2669288943Sdim } else if (Size == 128 || 2670288943Sdim (isNamedArg && Size <= getNativeVectorSizeForAVXABI(AVXLevel))) { 2671360784Sdim QualType ElementType = VT->getElementType(); 2672360784Sdim 2673360784Sdim // gcc passes 256 and 512 bit <X x __int128> vectors in memory. :( 2674360784Sdim if (passInt128VectorsInMem() && Size != 128 && 2675360784Sdim (ElementType->isSpecificBuiltinType(BuiltinType::Int128) || 2676360784Sdim ElementType->isSpecificBuiltinType(BuiltinType::UInt128))) 2677360784Sdim return; 2678360784Sdim 2679224145Sdim // Arguments of 256-bits are split into four eightbyte chunks. The 2680224145Sdim // least significant one belongs to class SSE and all the others to class 2681224145Sdim // SSEUP. The original Lo and Hi design considers that types can't be 2682224145Sdim // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense. 2683224145Sdim // This design isn't correct for 256-bits, but since there're no cases 2684224145Sdim // where the upper parts would need to be inspected, avoid adding 2685224145Sdim // complexity and just consider Hi to match the 64-256 part. 2686261991Sdim // 2687261991Sdim // Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in 2688261991Sdim // registers if they are "named", i.e. not part of the "..." of a 2689261991Sdim // variadic function. 2690288943Sdim // 2691288943Sdim // Similarly, per 3.2.3. of the AVX512 draft, 512-bits ("named") args are 2692288943Sdim // split into eight eightbyte chunks, one SSE and seven SSEUP. 2693202379Srdivacky Lo = SSE; 2694202379Srdivacky Hi = SSEUp; 2695202379Srdivacky } 2696210299Sed return; 2697210299Sed } 2698212904Sdim 2699210299Sed if (const ComplexType *CT = Ty->getAs<ComplexType>()) { 2700212904Sdim QualType ET = getContext().getCanonicalType(CT->getElementType()); 2701202379Srdivacky 2702212904Sdim uint64_t Size = getContext().getTypeSize(Ty); 2703210299Sed if (ET->isIntegralOrEnumerationType()) { 2704202379Srdivacky if (Size <= 64) 2705202379Srdivacky Current = Integer; 2706202379Srdivacky else if (Size <= 128) 2707202379Srdivacky Lo = Hi = Integer; 2708288943Sdim } else if (ET == getContext().FloatTy) { 2709202379Srdivacky Current = SSE; 2710288943Sdim } else if (ET == getContext().DoubleTy) { 2711202379Srdivacky Lo = Hi = SSE; 2712288943Sdim } else if (ET == getContext().LongDoubleTy) { 2713288943Sdim const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat(); 2714314564Sdim if (LDF == &llvm::APFloat::IEEEquad()) 2715288943Sdim Current = Memory; 2716314564Sdim else if (LDF == &llvm::APFloat::x87DoubleExtended()) 2717288943Sdim Current = ComplexX87; 2718314564Sdim else if (LDF == &llvm::APFloat::IEEEdouble()) 2719288943Sdim Lo = Hi = SSE; 2720288943Sdim else 2721288943Sdim llvm_unreachable("unexpected long double representation!"); 2722288943Sdim } 2723202379Srdivacky 2724202379Srdivacky // If this complex type crosses an eightbyte boundary then it 2725202379Srdivacky // should be split. 2726202379Srdivacky uint64_t EB_Real = (OffsetBase) / 64; 2727212904Sdim uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64; 2728202379Srdivacky if (Hi == NoClass && EB_Real != EB_Imag) 2729202379Srdivacky Hi = Lo; 2730212904Sdim 2731210299Sed return; 2732210299Sed } 2733212904Sdim 2734212904Sdim if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) { 2735202379Srdivacky // Arrays are treated like structures. 2736202379Srdivacky 2737212904Sdim uint64_t Size = getContext().getTypeSize(Ty); 2738202379Srdivacky 2739202379Srdivacky // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger 2740314564Sdim // than eight eightbytes, ..., it has class MEMORY. 2741314564Sdim if (Size > 512) 2742202379Srdivacky return; 2743202379Srdivacky 2744202379Srdivacky // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned 2745202379Srdivacky // fields, it has class MEMORY. 2746202379Srdivacky // 2747202379Srdivacky // Only need to check alignment of array base. 2748212904Sdim if (OffsetBase % getContext().getTypeAlign(AT->getElementType())) 2749202379Srdivacky return; 2750202379Srdivacky 2751202379Srdivacky // Otherwise implement simplified merge. We could be smarter about 2752202379Srdivacky // this, but it isn't worth it and would be harder to verify. 2753202379Srdivacky Current = NoClass; 2754212904Sdim uint64_t EltSize = getContext().getTypeSize(AT->getElementType()); 2755202379Srdivacky uint64_t ArraySize = AT->getSize().getZExtValue(); 2756224145Sdim 2757224145Sdim // The only case a 256-bit wide vector could be used is when the array 2758224145Sdim // contains a single 256-bit element. Since Lo and Hi logic isn't extended 2759224145Sdim // to work for sizes wider than 128, early check and fallback to memory. 2760314564Sdim // 2761314564Sdim if (Size > 128 && 2762314564Sdim (Size != EltSize || Size > getNativeVectorSizeForAVXABI(AVXLevel))) 2763224145Sdim return; 2764224145Sdim 2765202379Srdivacky for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) { 2766202379Srdivacky Class FieldLo, FieldHi; 2767261991Sdim classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg); 2768202379Srdivacky Lo = merge(Lo, FieldLo); 2769202379Srdivacky Hi = merge(Hi, FieldHi); 2770202379Srdivacky if (Lo == Memory || Hi == Memory) 2771202379Srdivacky break; 2772202379Srdivacky } 2773202379Srdivacky 2774224145Sdim postMerge(Size, Lo, Hi); 2775202379Srdivacky assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification."); 2776210299Sed return; 2777210299Sed } 2778212904Sdim 2779210299Sed if (const RecordType *RT = Ty->getAs<RecordType>()) { 2780212904Sdim uint64_t Size = getContext().getTypeSize(Ty); 2781202379Srdivacky 2782202379Srdivacky // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger 2783314564Sdim // than eight eightbytes, ..., it has class MEMORY. 2784314564Sdim if (Size > 512) 2785202379Srdivacky return; 2786202379Srdivacky 2787202379Srdivacky // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial 2788202379Srdivacky // copy constructor or a non-trivial destructor, it is passed by invisible 2789202379Srdivacky // reference. 2790261991Sdim if (getRecordArgABI(RT, getCXXABI())) 2791202379Srdivacky return; 2792202379Srdivacky 2793202379Srdivacky const RecordDecl *RD = RT->getDecl(); 2794202379Srdivacky 2795202379Srdivacky // Assume variable sized types are passed in memory. 2796202379Srdivacky if (RD->hasFlexibleArrayMember()) 2797202379Srdivacky return; 2798202379Srdivacky 2799212904Sdim const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD); 2800202379Srdivacky 2801202379Srdivacky // Reset Lo class, this will be recomputed. 2802202379Srdivacky Current = NoClass; 2803202379Srdivacky 2804202379Srdivacky // If this is a C++ record, classify the bases first. 2805202379Srdivacky if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) { 2806276479Sdim for (const auto &I : CXXRD->bases()) { 2807276479Sdim assert(!I.isVirtual() && !I.getType()->isDependentType() && 2808202379Srdivacky "Unexpected base class!"); 2809360784Sdim const auto *Base = 2810360784Sdim cast<CXXRecordDecl>(I.getType()->castAs<RecordType>()->getDecl()); 2811202379Srdivacky 2812202379Srdivacky // Classify this field. 2813202379Srdivacky // 2814202379Srdivacky // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a 2815202379Srdivacky // single eightbyte, each is classified separately. Each eightbyte gets 2816202379Srdivacky // initialized to class NO_CLASS. 2817202379Srdivacky Class FieldLo, FieldHi; 2818239462Sdim uint64_t Offset = 2819239462Sdim OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base)); 2820276479Sdim classify(I.getType(), Offset, FieldLo, FieldHi, isNamedArg); 2821202379Srdivacky Lo = merge(Lo, FieldLo); 2822202379Srdivacky Hi = merge(Hi, FieldHi); 2823288943Sdim if (Lo == Memory || Hi == Memory) { 2824288943Sdim postMerge(Size, Lo, Hi); 2825288943Sdim return; 2826288943Sdim } 2827202379Srdivacky } 2828202379Srdivacky } 2829202379Srdivacky 2830202379Srdivacky // Classify the fields one at a time, merging the results. 2831202379Srdivacky unsigned idx = 0; 2832202379Srdivacky for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 2833202379Srdivacky i != e; ++i, ++idx) { 2834202379Srdivacky uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx); 2835202379Srdivacky bool BitField = i->isBitField(); 2836202379Srdivacky 2837314564Sdim // Ignore padding bit-fields. 2838314564Sdim if (BitField && i->isUnnamedBitfield()) 2839314564Sdim continue; 2840314564Sdim 2841224145Sdim // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than 2842224145Sdim // four eightbytes, or it contains unaligned fields, it has class MEMORY. 2843202379Srdivacky // 2844224145Sdim // The only case a 256-bit wide vector could be used is when the struct 2845224145Sdim // contains a single 256-bit element. Since Lo and Hi logic isn't extended 2846224145Sdim // to work for sizes wider than 128, early check and fallback to memory. 2847224145Sdim // 2848314564Sdim if (Size > 128 && (Size != getContext().getTypeSize(i->getType()) || 2849314564Sdim Size > getNativeVectorSizeForAVXABI(AVXLevel))) { 2850224145Sdim Lo = Memory; 2851288943Sdim postMerge(Size, Lo, Hi); 2852224145Sdim return; 2853224145Sdim } 2854202379Srdivacky // Note, skip this test for bit-fields, see below. 2855212904Sdim if (!BitField && Offset % getContext().getTypeAlign(i->getType())) { 2856202379Srdivacky Lo = Memory; 2857288943Sdim postMerge(Size, Lo, Hi); 2858202379Srdivacky return; 2859202379Srdivacky } 2860202379Srdivacky 2861202379Srdivacky // Classify this field. 2862202379Srdivacky // 2863202379Srdivacky // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate 2864202379Srdivacky // exceeds a single eightbyte, each is classified 2865202379Srdivacky // separately. Each eightbyte gets initialized to class 2866202379Srdivacky // NO_CLASS. 2867202379Srdivacky Class FieldLo, FieldHi; 2868202379Srdivacky 2869202379Srdivacky // Bit-fields require special handling, they do not force the 2870202379Srdivacky // structure to be passed in memory even if unaligned, and 2871202379Srdivacky // therefore they can straddle an eightbyte. 2872202379Srdivacky if (BitField) { 2873314564Sdim assert(!i->isUnnamedBitfield()); 2874202379Srdivacky uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx); 2875226633Sdim uint64_t Size = i->getBitWidthValue(getContext()); 2876202379Srdivacky 2877202379Srdivacky uint64_t EB_Lo = Offset / 64; 2878202379Srdivacky uint64_t EB_Hi = (Offset + Size - 1) / 64; 2879261991Sdim 2880202379Srdivacky if (EB_Lo) { 2881202379Srdivacky assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes."); 2882202379Srdivacky FieldLo = NoClass; 2883202379Srdivacky FieldHi = Integer; 2884202379Srdivacky } else { 2885202379Srdivacky FieldLo = Integer; 2886202379Srdivacky FieldHi = EB_Hi ? Integer : NoClass; 2887202379Srdivacky } 2888202379Srdivacky } else 2889261991Sdim classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg); 2890202379Srdivacky Lo = merge(Lo, FieldLo); 2891202379Srdivacky Hi = merge(Hi, FieldHi); 2892202379Srdivacky if (Lo == Memory || Hi == Memory) 2893202379Srdivacky break; 2894202379Srdivacky } 2895202379Srdivacky 2896224145Sdim postMerge(Size, Lo, Hi); 2897202379Srdivacky } 2898202379Srdivacky} 2899202379Srdivacky 2900210299SedABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const { 2901207619Srdivacky // If this is a scalar LLVM value then assume LLVM will pass it in the right 2902207619Srdivacky // place naturally. 2903212904Sdim if (!isAggregateTypeForABI(Ty)) { 2904207619Srdivacky // Treat an enum type as its underlying type. 2905207619Srdivacky if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 2906207619Srdivacky Ty = EnumTy->getDecl()->getIntegerType(); 2907207619Srdivacky 2908341825Sdim return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty) 2909341825Sdim : ABIArgInfo::getDirect()); 2910207619Srdivacky } 2911207619Srdivacky 2912296417Sdim return getNaturalAlignIndirect(Ty); 2913207619Srdivacky} 2914207619Srdivacky 2915234353Sdimbool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const { 2916234353Sdim if (const VectorType *VecTy = Ty->getAs<VectorType>()) { 2917234353Sdim uint64_t Size = getContext().getTypeSize(VecTy); 2918288943Sdim unsigned LargestVector = getNativeVectorSizeForAVXABI(AVXLevel); 2919234353Sdim if (Size <= 64 || Size > LargestVector) 2920234353Sdim return true; 2921360784Sdim QualType EltTy = VecTy->getElementType(); 2922360784Sdim if (passInt128VectorsInMem() && 2923360784Sdim (EltTy->isSpecificBuiltinType(BuiltinType::Int128) || 2924360784Sdim EltTy->isSpecificBuiltinType(BuiltinType::UInt128))) 2925360784Sdim return true; 2926234353Sdim } 2927234353Sdim 2928234353Sdim return false; 2929234353Sdim} 2930234353Sdim 2931234353SdimABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty, 2932234353Sdim unsigned freeIntRegs) const { 2933202379Srdivacky // If this is a scalar LLVM value then assume LLVM will pass it in the right 2934202379Srdivacky // place naturally. 2935234353Sdim // 2936234353Sdim // This assumption is optimistic, as there could be free registers available 2937234353Sdim // when we need to pass this argument in memory, and LLVM could try to pass 2938234353Sdim // the argument in the free register. This does not seem to happen currently, 2939234353Sdim // but this code would be much safer if we could mark the argument with 2940234353Sdim // 'onstack'. See PR12193. 2941234353Sdim if (!isAggregateTypeForABI(Ty) && !IsIllegalVectorType(Ty)) { 2942203955Srdivacky // Treat an enum type as its underlying type. 2943203955Srdivacky if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 2944203955Srdivacky Ty = EnumTy->getDecl()->getIntegerType(); 2945203955Srdivacky 2946341825Sdim return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty) 2947341825Sdim : ABIArgInfo::getDirect()); 2948203955Srdivacky } 2949202379Srdivacky 2950261991Sdim if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) 2951296417Sdim return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory); 2952202379Srdivacky 2953223017Sdim // Compute the byval alignment. We specify the alignment of the byval in all 2954223017Sdim // cases so that the mid-level optimizer knows the alignment of the byval. 2955223017Sdim unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U); 2956234353Sdim 2957234353Sdim // Attempt to avoid passing indirect results using byval when possible. This 2958234353Sdim // is important for good codegen. 2959234353Sdim // 2960234353Sdim // We do this by coercing the value into a scalar type which the backend can 2961234353Sdim // handle naturally (i.e., without using byval). 2962234353Sdim // 2963234353Sdim // For simplicity, we currently only do this when we have exhausted all of the 2964234353Sdim // free integer registers. Doing this when there are free integer registers 2965234353Sdim // would require more care, as we would have to ensure that the coerced value 2966234353Sdim // did not claim the unused register. That would require either reording the 2967234353Sdim // arguments to the function (so that any subsequent inreg values came first), 2968234353Sdim // or only doing this optimization when there were no following arguments that 2969234353Sdim // might be inreg. 2970234353Sdim // 2971234353Sdim // We currently expect it to be rare (particularly in well written code) for 2972234353Sdim // arguments to be passed on the stack when there are still free integer 2973234353Sdim // registers available (this would typically imply large structs being passed 2974234353Sdim // by value), so this seems like a fair tradeoff for now. 2975234353Sdim // 2976234353Sdim // We can revisit this if the backend grows support for 'onstack' parameter 2977234353Sdim // attributes. See PR12193. 2978234353Sdim if (freeIntRegs == 0) { 2979234353Sdim uint64_t Size = getContext().getTypeSize(Ty); 2980234353Sdim 2981234353Sdim // If this type fits in an eightbyte, coerce it into the matching integral 2982234353Sdim // type, which will end up on the stack (with alignment 8). 2983234353Sdim if (Align == 8 && Size <= 64) 2984234353Sdim return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 2985234353Sdim Size)); 2986234353Sdim } 2987234353Sdim 2988296417Sdim return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align)); 2989202379Srdivacky} 2990202379Srdivacky 2991280031Sdim/// The ABI specifies that a value should be passed in a full vector XMM/YMM 2992280031Sdim/// register. Pick an LLVM IR type that will be passed as a vector register. 2993224145Sdimllvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const { 2994280031Sdim // Wrapper structs/arrays that only contain vectors are passed just like 2995280031Sdim // vectors; strip them off if present. 2996280031Sdim if (const Type *InnerTy = isSingleElementStruct(Ty, getContext())) 2997280031Sdim Ty = QualType(InnerTy, 0); 2998280031Sdim 2999224145Sdim llvm::Type *IRType = CGT.ConvertType(Ty); 3000360784Sdim if (isa<llvm::VectorType>(IRType)) { 3001360784Sdim // Don't pass vXi128 vectors in their native type, the backend can't 3002360784Sdim // legalize them. 3003360784Sdim if (passInt128VectorsInMem() && 3004360784Sdim IRType->getVectorElementType()->isIntegerTy(128)) { 3005360784Sdim // Use a vXi64 vector. 3006360784Sdim uint64_t Size = getContext().getTypeSize(Ty); 3007360784Sdim return llvm::VectorType::get(llvm::Type::getInt64Ty(getVMContext()), 3008360784Sdim Size / 64); 3009360784Sdim } 3010360784Sdim 3011288943Sdim return IRType; 3012360784Sdim } 3013212904Sdim 3014360784Sdim if (IRType->getTypeID() == llvm::Type::FP128TyID) 3015360784Sdim return IRType; 3016360784Sdim 3017288943Sdim // We couldn't find the preferred IR vector type for 'Ty'. 3018288943Sdim uint64_t Size = getContext().getTypeSize(Ty); 3019314564Sdim assert((Size == 128 || Size == 256 || Size == 512) && "Invalid type found!"); 3020212904Sdim 3021360784Sdim 3022288943Sdim // Return a LLVM IR vector type based on the size of 'Ty'. 3023288943Sdim return llvm::VectorType::get(llvm::Type::getDoubleTy(getVMContext()), 3024288943Sdim Size / 64); 3025212904Sdim} 3026212904Sdim 3027212904Sdim/// BitsContainNoUserData - Return true if the specified [start,end) bit range 3028212904Sdim/// is known to either be off the end of the specified type or being in 3029212904Sdim/// alignment padding. The user type specified is known to be at most 128 bits 3030212904Sdim/// in size, and have passed through X86_64ABIInfo::classify with a successful 3031212904Sdim/// classification that put one of the two halves in the INTEGER class. 3032212904Sdim/// 3033212904Sdim/// It is conservatively correct to return false. 3034212904Sdimstatic bool BitsContainNoUserData(QualType Ty, unsigned StartBit, 3035212904Sdim unsigned EndBit, ASTContext &Context) { 3036212904Sdim // If the bytes being queried are off the end of the type, there is no user 3037212904Sdim // data hiding here. This handles analysis of builtins, vectors and other 3038212904Sdim // types that don't contain interesting padding. 3039212904Sdim unsigned TySize = (unsigned)Context.getTypeSize(Ty); 3040212904Sdim if (TySize <= StartBit) 3041212904Sdim return true; 3042212904Sdim 3043212904Sdim if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) { 3044212904Sdim unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType()); 3045212904Sdim unsigned NumElts = (unsigned)AT->getSize().getZExtValue(); 3046212904Sdim 3047212904Sdim // Check each element to see if the element overlaps with the queried range. 3048212904Sdim for (unsigned i = 0; i != NumElts; ++i) { 3049212904Sdim // If the element is after the span we care about, then we're done.. 3050212904Sdim unsigned EltOffset = i*EltSize; 3051212904Sdim if (EltOffset >= EndBit) break; 3052212904Sdim 3053212904Sdim unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0; 3054212904Sdim if (!BitsContainNoUserData(AT->getElementType(), EltStart, 3055212904Sdim EndBit-EltOffset, Context)) 3056212904Sdim return false; 3057212904Sdim } 3058212904Sdim // If it overlaps no elements, then it is safe to process as padding. 3059212904Sdim return true; 3060212904Sdim } 3061212904Sdim 3062212904Sdim if (const RecordType *RT = Ty->getAs<RecordType>()) { 3063212904Sdim const RecordDecl *RD = RT->getDecl(); 3064212904Sdim const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD); 3065212904Sdim 3066212904Sdim // If this is a C++ record, check the bases first. 3067212904Sdim if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) { 3068276479Sdim for (const auto &I : CXXRD->bases()) { 3069276479Sdim assert(!I.isVirtual() && !I.getType()->isDependentType() && 3070212904Sdim "Unexpected base class!"); 3071360784Sdim const auto *Base = 3072360784Sdim cast<CXXRecordDecl>(I.getType()->castAs<RecordType>()->getDecl()); 3073212904Sdim 3074212904Sdim // If the base is after the span we care about, ignore it. 3075239462Sdim unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base)); 3076212904Sdim if (BaseOffset >= EndBit) continue; 3077212904Sdim 3078212904Sdim unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0; 3079276479Sdim if (!BitsContainNoUserData(I.getType(), BaseStart, 3080212904Sdim EndBit-BaseOffset, Context)) 3081212904Sdim return false; 3082212904Sdim } 3083212904Sdim } 3084212904Sdim 3085212904Sdim // Verify that no field has data that overlaps the region of interest. Yes 3086212904Sdim // this could be sped up a lot by being smarter about queried fields, 3087212904Sdim // however we're only looking at structs up to 16 bytes, so we don't care 3088212904Sdim // much. 3089212904Sdim unsigned idx = 0; 3090212904Sdim for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 3091212904Sdim i != e; ++i, ++idx) { 3092212904Sdim unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx); 3093212904Sdim 3094212904Sdim // If we found a field after the region we care about, then we're done. 3095212904Sdim if (FieldOffset >= EndBit) break; 3096212904Sdim 3097212904Sdim unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0; 3098212904Sdim if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset, 3099212904Sdim Context)) 3100212904Sdim return false; 3101212904Sdim } 3102212904Sdim 3103212904Sdim // If nothing in this record overlapped the area of interest, then we're 3104212904Sdim // clean. 3105212904Sdim return true; 3106212904Sdim } 3107212904Sdim 3108212904Sdim return false; 3109212904Sdim} 3110212904Sdim 3111212904Sdim/// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a 3112212904Sdim/// float member at the specified offset. For example, {int,{float}} has a 3113212904Sdim/// float at offset 4. It is conservatively correct for this routine to return 3114212904Sdim/// false. 3115226633Sdimstatic bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset, 3116243830Sdim const llvm::DataLayout &TD) { 3117212904Sdim // Base case if we find a float. 3118212904Sdim if (IROffset == 0 && IRType->isFloatTy()) 3119212904Sdim return true; 3120212904Sdim 3121212904Sdim // If this is a struct, recurse into the field at the specified offset. 3122226633Sdim if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) { 3123212904Sdim const llvm::StructLayout *SL = TD.getStructLayout(STy); 3124212904Sdim unsigned Elt = SL->getElementContainingOffset(IROffset); 3125212904Sdim IROffset -= SL->getElementOffset(Elt); 3126212904Sdim return ContainsFloatAtOffset(STy->getElementType(Elt), IROffset, TD); 3127212904Sdim } 3128212904Sdim 3129212904Sdim // If this is an array, recurse into the field at the specified offset. 3130226633Sdim if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) { 3131226633Sdim llvm::Type *EltTy = ATy->getElementType(); 3132212904Sdim unsigned EltSize = TD.getTypeAllocSize(EltTy); 3133212904Sdim IROffset -= IROffset/EltSize*EltSize; 3134212904Sdim return ContainsFloatAtOffset(EltTy, IROffset, TD); 3135212904Sdim } 3136212904Sdim 3137212904Sdim return false; 3138212904Sdim} 3139212904Sdim 3140212904Sdim 3141212904Sdim/// GetSSETypeAtOffset - Return a type that will be passed by the backend in the 3142212904Sdim/// low 8 bytes of an XMM register, corresponding to the SSE class. 3143224145Sdimllvm::Type *X86_64ABIInfo:: 3144224145SdimGetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset, 3145212904Sdim QualType SourceTy, unsigned SourceOffset) const { 3146212904Sdim // The only three choices we have are either double, <2 x float>, or float. We 3147212904Sdim // pass as float if the last 4 bytes is just padding. This happens for 3148212904Sdim // structs that contain 3 floats. 3149212904Sdim if (BitsContainNoUserData(SourceTy, SourceOffset*8+32, 3150212904Sdim SourceOffset*8+64, getContext())) 3151212904Sdim return llvm::Type::getFloatTy(getVMContext()); 3152212904Sdim 3153212904Sdim // We want to pass as <2 x float> if the LLVM IR type contains a float at 3154212904Sdim // offset+0 and offset+4. Walk the LLVM IR type to find out if this is the 3155212904Sdim // case. 3156243830Sdim if (ContainsFloatAtOffset(IRType, IROffset, getDataLayout()) && 3157243830Sdim ContainsFloatAtOffset(IRType, IROffset+4, getDataLayout())) 3158212904Sdim return llvm::VectorType::get(llvm::Type::getFloatTy(getVMContext()), 2); 3159212904Sdim 3160212904Sdim return llvm::Type::getDoubleTy(getVMContext()); 3161212904Sdim} 3162212904Sdim 3163212904Sdim 3164212904Sdim/// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in 3165212904Sdim/// an 8-byte GPR. This means that we either have a scalar or we are talking 3166212904Sdim/// about the high or low part of an up-to-16-byte struct. This routine picks 3167212904Sdim/// the best LLVM IR type to represent this, which may be i64 or may be anything 3168212904Sdim/// else that the backend will pass in a GPR that works better (e.g. i8, %foo*, 3169212904Sdim/// etc). 3170212904Sdim/// 3171212904Sdim/// PrefType is an LLVM IR type that corresponds to (part of) the IR type for 3172212904Sdim/// the source type. IROffset is an offset in bytes into the LLVM IR type that 3173212904Sdim/// the 8-byte value references. PrefType may be null. 3174212904Sdim/// 3175276479Sdim/// SourceTy is the source-level type for the entire argument. SourceOffset is 3176212904Sdim/// an offset into this that we're processing (which is always either 0 or 8). 3177212904Sdim/// 3178224145Sdimllvm::Type *X86_64ABIInfo:: 3179224145SdimGetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset, 3180212904Sdim QualType SourceTy, unsigned SourceOffset) const { 3181212904Sdim // If we're dealing with an un-offset LLVM IR type, then it means that we're 3182212904Sdim // returning an 8-byte unit starting with it. See if we can safely use it. 3183212904Sdim if (IROffset == 0) { 3184212904Sdim // Pointers and int64's always fill the 8-byte unit. 3185243830Sdim if ((isa<llvm::PointerType>(IRType) && Has64BitPointers) || 3186243830Sdim IRType->isIntegerTy(64)) 3187212904Sdim return IRType; 3188212904Sdim 3189212904Sdim // If we have a 1/2/4-byte integer, we can use it only if the rest of the 3190212904Sdim // goodness in the source type is just tail padding. This is allowed to 3191212904Sdim // kick in for struct {double,int} on the int, but not on 3192212904Sdim // struct{double,int,int} because we wouldn't return the second int. We 3193212904Sdim // have to do this analysis on the source type because we can't depend on 3194212904Sdim // unions being lowered a specific way etc. 3195212904Sdim if (IRType->isIntegerTy(8) || IRType->isIntegerTy(16) || 3196243830Sdim IRType->isIntegerTy(32) || 3197243830Sdim (isa<llvm::PointerType>(IRType) && !Has64BitPointers)) { 3198243830Sdim unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 32 : 3199243830Sdim cast<llvm::IntegerType>(IRType)->getBitWidth(); 3200212904Sdim 3201212904Sdim if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth, 3202212904Sdim SourceOffset*8+64, getContext())) 3203212904Sdim return IRType; 3204212904Sdim } 3205212904Sdim } 3206212904Sdim 3207226633Sdim if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) { 3208212904Sdim // If this is a struct, recurse into the field at the specified offset. 3209243830Sdim const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy); 3210212904Sdim if (IROffset < SL->getSizeInBytes()) { 3211212904Sdim unsigned FieldIdx = SL->getElementContainingOffset(IROffset); 3212212904Sdim IROffset -= SL->getElementOffset(FieldIdx); 3213212904Sdim 3214212904Sdim return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset, 3215212904Sdim SourceTy, SourceOffset); 3216212904Sdim } 3217212904Sdim } 3218212904Sdim 3219226633Sdim if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) { 3220224145Sdim llvm::Type *EltTy = ATy->getElementType(); 3221243830Sdim unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy); 3222212904Sdim unsigned EltOffset = IROffset/EltSize*EltSize; 3223212904Sdim return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy, 3224212904Sdim SourceOffset); 3225212904Sdim } 3226212904Sdim 3227212904Sdim // Okay, we don't have any better idea of what to pass, so we pass this in an 3228212904Sdim // integer register that isn't too big to fit the rest of the struct. 3229212904Sdim unsigned TySizeInBytes = 3230212904Sdim (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity(); 3231212904Sdim 3232212904Sdim assert(TySizeInBytes != SourceOffset && "Empty field?"); 3233212904Sdim 3234212904Sdim // It is always safe to classify this as an integer type up to i64 that 3235212904Sdim // isn't larger than the structure. 3236212904Sdim return llvm::IntegerType::get(getVMContext(), 3237212904Sdim std::min(TySizeInBytes-SourceOffset, 8U)*8); 3238212904Sdim} 3239212904Sdim 3240212904Sdim 3241212904Sdim/// GetX86_64ByValArgumentPair - Given a high and low type that can ideally 3242212904Sdim/// be used as elements of a two register pair to pass or return, return a 3243212904Sdim/// first class aggregate to represent them. For example, if the low part of 3244212904Sdim/// a by-value argument should be passed as i32* and the high part as float, 3245212904Sdim/// return {i32*, float}. 3246224145Sdimstatic llvm::Type * 3247224145SdimGetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi, 3248243830Sdim const llvm::DataLayout &TD) { 3249212904Sdim // In order to correctly satisfy the ABI, we need to the high part to start 3250212904Sdim // at offset 8. If the high and low parts we inferred are both 4-byte types 3251212904Sdim // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have 3252212904Sdim // the second element at offset 8. Check for this: 3253212904Sdim unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo); 3254212904Sdim unsigned HiAlign = TD.getABITypeAlignment(Hi); 3255309124Sdim unsigned HiStart = llvm::alignTo(LoSize, HiAlign); 3256212904Sdim assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!"); 3257218893Sdim 3258212904Sdim // To handle this, we have to increase the size of the low part so that the 3259212904Sdim // second element will start at an 8 byte offset. We can't increase the size 3260212904Sdim // of the second element because it might make us access off the end of the 3261212904Sdim // struct. 3262212904Sdim if (HiStart != 8) { 3263288943Sdim // There are usually two sorts of types the ABI generation code can produce 3264288943Sdim // for the low part of a pair that aren't 8 bytes in size: float or 3265288943Sdim // i8/i16/i32. This can also include pointers when they are 32-bit (X32 and 3266288943Sdim // NaCl). 3267212904Sdim // Promote these to a larger type. 3268212904Sdim if (Lo->isFloatTy()) 3269212904Sdim Lo = llvm::Type::getDoubleTy(Lo->getContext()); 3270212904Sdim else { 3271288943Sdim assert((Lo->isIntegerTy() || Lo->isPointerTy()) 3272288943Sdim && "Invalid/unknown lo type"); 3273212904Sdim Lo = llvm::Type::getInt64Ty(Lo->getContext()); 3274212904Sdim } 3275212904Sdim } 3276218893Sdim 3277321369Sdim llvm::StructType *Result = llvm::StructType::get(Lo, Hi); 3278218893Sdim 3279212904Sdim // Verify that the second element is at an 8-byte offset. 3280212904Sdim assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 && 3281212904Sdim "Invalid x86-64 argument pair!"); 3282212904Sdim return Result; 3283212904Sdim} 3284212904Sdim 3285210299SedABIArgInfo X86_64ABIInfo:: 3286212904SdimclassifyReturnType(QualType RetTy) const { 3287202379Srdivacky // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the 3288202379Srdivacky // classification algorithm. 3289202379Srdivacky X86_64ABIInfo::Class Lo, Hi; 3290261991Sdim classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true); 3291202379Srdivacky 3292202379Srdivacky // Check some invariants. 3293202379Srdivacky assert((Hi != Memory || Lo == Memory) && "Invalid memory classification."); 3294202379Srdivacky assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification."); 3295202379Srdivacky 3296276479Sdim llvm::Type *ResType = nullptr; 3297202379Srdivacky switch (Lo) { 3298202379Srdivacky case NoClass: 3299212904Sdim if (Hi == NoClass) 3300212904Sdim return ABIArgInfo::getIgnore(); 3301212904Sdim // If the low part is just padding, it takes no register, leave ResType 3302212904Sdim // null. 3303212904Sdim assert((Hi == SSE || Hi == Integer || Hi == X87Up) && 3304212904Sdim "Unknown missing lo part"); 3305212904Sdim break; 3306202379Srdivacky 3307202379Srdivacky case SSEUp: 3308202379Srdivacky case X87Up: 3309226633Sdim llvm_unreachable("Invalid classification for lo word."); 3310202379Srdivacky 3311202379Srdivacky // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via 3312202379Srdivacky // hidden argument. 3313202379Srdivacky case Memory: 3314210299Sed return getIndirectReturnResult(RetTy); 3315202379Srdivacky 3316202379Srdivacky // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next 3317202379Srdivacky // available register of the sequence %rax, %rdx is used. 3318202379Srdivacky case Integer: 3319224145Sdim ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0); 3320202379Srdivacky 3321212904Sdim // If we have a sign or zero extended integer, make sure to return Extend 3322212904Sdim // so that the parameter gets the right LLVM IR attributes. 3323212904Sdim if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) { 3324212904Sdim // Treat an enum type as its underlying type. 3325212904Sdim if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 3326212904Sdim RetTy = EnumTy->getDecl()->getIntegerType(); 3327212904Sdim 3328212904Sdim if (RetTy->isIntegralOrEnumerationType() && 3329212904Sdim RetTy->isPromotableIntegerType()) 3330341825Sdim return ABIArgInfo::getExtend(RetTy); 3331212904Sdim } 3332212904Sdim break; 3333212904Sdim 3334202379Srdivacky // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next 3335202379Srdivacky // available SSE register of the sequence %xmm0, %xmm1 is used. 3336202379Srdivacky case SSE: 3337224145Sdim ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0); 3338212904Sdim break; 3339202379Srdivacky 3340202379Srdivacky // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is 3341202379Srdivacky // returned on the X87 stack in %st0 as 80-bit x87 number. 3342202379Srdivacky case X87: 3343212904Sdim ResType = llvm::Type::getX86_FP80Ty(getVMContext()); 3344212904Sdim break; 3345202379Srdivacky 3346202379Srdivacky // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real 3347202379Srdivacky // part of the value is returned in %st0 and the imaginary part in 3348202379Srdivacky // %st1. 3349202379Srdivacky case ComplexX87: 3350202379Srdivacky assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification."); 3351224145Sdim ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()), 3352321369Sdim llvm::Type::getX86_FP80Ty(getVMContext())); 3353202379Srdivacky break; 3354202379Srdivacky } 3355202379Srdivacky 3356276479Sdim llvm::Type *HighPart = nullptr; 3357202379Srdivacky switch (Hi) { 3358202379Srdivacky // Memory was handled previously and X87 should 3359202379Srdivacky // never occur as a hi class. 3360202379Srdivacky case Memory: 3361202379Srdivacky case X87: 3362226633Sdim llvm_unreachable("Invalid classification for hi word."); 3363202379Srdivacky 3364202379Srdivacky case ComplexX87: // Previously handled. 3365212904Sdim case NoClass: 3366212904Sdim break; 3367202379Srdivacky 3368202379Srdivacky case Integer: 3369224145Sdim HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8); 3370212904Sdim if (Lo == NoClass) // Return HighPart at offset 8 in memory. 3371212904Sdim return ABIArgInfo::getDirect(HighPart, 8); 3372202379Srdivacky break; 3373202379Srdivacky case SSE: 3374224145Sdim HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8); 3375212904Sdim if (Lo == NoClass) // Return HighPart at offset 8 in memory. 3376212904Sdim return ABIArgInfo::getDirect(HighPart, 8); 3377202379Srdivacky break; 3378202379Srdivacky 3379202379Srdivacky // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte 3380224145Sdim // is passed in the next available eightbyte chunk if the last used 3381224145Sdim // vector register. 3382202379Srdivacky // 3383221345Sdim // SSEUP should always be preceded by SSE, just widen. 3384202379Srdivacky case SSEUp: 3385202379Srdivacky assert(Lo == SSE && "Unexpected SSEUp classification."); 3386224145Sdim ResType = GetByteVectorType(RetTy); 3387202379Srdivacky break; 3388202379Srdivacky 3389202379Srdivacky // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is 3390202379Srdivacky // returned together with the previous X87 value in %st0. 3391202379Srdivacky case X87Up: 3392221345Sdim // If X87Up is preceded by X87, we don't need to do 3393202379Srdivacky // anything. However, in some cases with unions it may not be 3394221345Sdim // preceded by X87. In such situations we follow gcc and pass the 3395202379Srdivacky // extra bits in an SSE reg. 3396212904Sdim if (Lo != X87) { 3397224145Sdim HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8); 3398212904Sdim if (Lo == NoClass) // Return HighPart at offset 8 in memory. 3399212904Sdim return ABIArgInfo::getDirect(HighPart, 8); 3400212904Sdim } 3401202379Srdivacky break; 3402202379Srdivacky } 3403218893Sdim 3404212904Sdim // If a high part was specified, merge it together with the low part. It is 3405212904Sdim // known to pass in the high eightbyte of the result. We do this by forming a 3406212904Sdim // first class struct aggregate with the high and low part: {low, high} 3407212904Sdim if (HighPart) 3408243830Sdim ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout()); 3409202379Srdivacky 3410212904Sdim return ABIArgInfo::getDirect(ResType); 3411202379Srdivacky} 3412202379Srdivacky 3413234353SdimABIArgInfo X86_64ABIInfo::classifyArgumentType( 3414261991Sdim QualType Ty, unsigned freeIntRegs, unsigned &neededInt, unsigned &neededSSE, 3415261991Sdim bool isNamedArg) 3416234353Sdim const 3417234353Sdim{ 3418280031Sdim Ty = useFirstFieldIfTransparentUnion(Ty); 3419280031Sdim 3420202379Srdivacky X86_64ABIInfo::Class Lo, Hi; 3421261991Sdim classify(Ty, 0, Lo, Hi, isNamedArg); 3422202379Srdivacky 3423202379Srdivacky // Check some invariants. 3424202379Srdivacky // FIXME: Enforce these by construction. 3425202379Srdivacky assert((Hi != Memory || Lo == Memory) && "Invalid memory classification."); 3426202379Srdivacky assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification."); 3427202379Srdivacky 3428202379Srdivacky neededInt = 0; 3429202379Srdivacky neededSSE = 0; 3430276479Sdim llvm::Type *ResType = nullptr; 3431202379Srdivacky switch (Lo) { 3432202379Srdivacky case NoClass: 3433212904Sdim if (Hi == NoClass) 3434212904Sdim return ABIArgInfo::getIgnore(); 3435212904Sdim // If the low part is just padding, it takes no register, leave ResType 3436212904Sdim // null. 3437212904Sdim assert((Hi == SSE || Hi == Integer || Hi == X87Up) && 3438212904Sdim "Unknown missing lo part"); 3439212904Sdim break; 3440202379Srdivacky 3441202379Srdivacky // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument 3442202379Srdivacky // on the stack. 3443202379Srdivacky case Memory: 3444202379Srdivacky 3445202379Srdivacky // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or 3446202379Srdivacky // COMPLEX_X87, it is passed in memory. 3447202379Srdivacky case X87: 3448202379Srdivacky case ComplexX87: 3449261991Sdim if (getRecordArgABI(Ty, getCXXABI()) == CGCXXABI::RAA_Indirect) 3450224145Sdim ++neededInt; 3451234353Sdim return getIndirectResult(Ty, freeIntRegs); 3452202379Srdivacky 3453202379Srdivacky case SSEUp: 3454202379Srdivacky case X87Up: 3455226633Sdim llvm_unreachable("Invalid classification for lo word."); 3456202379Srdivacky 3457202379Srdivacky // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next 3458202379Srdivacky // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8 3459202379Srdivacky // and %r9 is used. 3460202379Srdivacky case Integer: 3461202379Srdivacky ++neededInt; 3462212904Sdim 3463212904Sdim // Pick an 8-byte type based on the preferred type. 3464224145Sdim ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0); 3465212904Sdim 3466212904Sdim // If we have a sign or zero extended integer, make sure to return Extend 3467212904Sdim // so that the parameter gets the right LLVM IR attributes. 3468212904Sdim if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) { 3469212904Sdim // Treat an enum type as its underlying type. 3470212904Sdim if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 3471212904Sdim Ty = EnumTy->getDecl()->getIntegerType(); 3472212904Sdim 3473212904Sdim if (Ty->isIntegralOrEnumerationType() && 3474212904Sdim Ty->isPromotableIntegerType()) 3475341825Sdim return ABIArgInfo::getExtend(Ty); 3476212904Sdim } 3477212904Sdim 3478202379Srdivacky break; 3479202379Srdivacky 3480202379Srdivacky // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next 3481202379Srdivacky // available SSE register is used, the registers are taken in the 3482202379Srdivacky // order from %xmm0 to %xmm7. 3483218893Sdim case SSE: { 3484224145Sdim llvm::Type *IRType = CGT.ConvertType(Ty); 3485224145Sdim ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0); 3486202379Srdivacky ++neededSSE; 3487202379Srdivacky break; 3488202379Srdivacky } 3489218893Sdim } 3490202379Srdivacky 3491276479Sdim llvm::Type *HighPart = nullptr; 3492202379Srdivacky switch (Hi) { 3493202379Srdivacky // Memory was handled previously, ComplexX87 and X87 should 3494221345Sdim // never occur as hi classes, and X87Up must be preceded by X87, 3495202379Srdivacky // which is passed in memory. 3496202379Srdivacky case Memory: 3497202379Srdivacky case X87: 3498202379Srdivacky case ComplexX87: 3499226633Sdim llvm_unreachable("Invalid classification for hi word."); 3500202379Srdivacky 3501202379Srdivacky case NoClass: break; 3502212904Sdim 3503212904Sdim case Integer: 3504202379Srdivacky ++neededInt; 3505212904Sdim // Pick an 8-byte type based on the preferred type. 3506224145Sdim HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8); 3507210299Sed 3508212904Sdim if (Lo == NoClass) // Pass HighPart at offset 8 in memory. 3509212904Sdim return ABIArgInfo::getDirect(HighPart, 8); 3510202379Srdivacky break; 3511202379Srdivacky 3512202379Srdivacky // X87Up generally doesn't occur here (long double is passed in 3513202379Srdivacky // memory), except in situations involving unions. 3514202379Srdivacky case X87Up: 3515202379Srdivacky case SSE: 3516224145Sdim HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8); 3517212904Sdim 3518212904Sdim if (Lo == NoClass) // Pass HighPart at offset 8 in memory. 3519212904Sdim return ABIArgInfo::getDirect(HighPart, 8); 3520212904Sdim 3521202379Srdivacky ++neededSSE; 3522202379Srdivacky break; 3523202379Srdivacky 3524202379Srdivacky // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the 3525202379Srdivacky // eightbyte is passed in the upper half of the last used SSE 3526212904Sdim // register. This only happens when 128-bit vectors are passed. 3527202379Srdivacky case SSEUp: 3528212904Sdim assert(Lo == SSE && "Unexpected SSEUp classification"); 3529224145Sdim ResType = GetByteVectorType(Ty); 3530202379Srdivacky break; 3531202379Srdivacky } 3532202379Srdivacky 3533212904Sdim // If a high part was specified, merge it together with the low part. It is 3534212904Sdim // known to pass in the high eightbyte of the result. We do this by forming a 3535212904Sdim // first class struct aggregate with the high and low part: {low, high} 3536212904Sdim if (HighPart) 3537243830Sdim ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout()); 3538218893Sdim 3539212904Sdim return ABIArgInfo::getDirect(ResType); 3540202379Srdivacky} 3541202379Srdivacky 3542314564SdimABIArgInfo 3543314564SdimX86_64ABIInfo::classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt, 3544314564Sdim unsigned &NeededSSE) const { 3545314564Sdim auto RT = Ty->getAs<RecordType>(); 3546314564Sdim assert(RT && "classifyRegCallStructType only valid with struct types"); 3547314564Sdim 3548314564Sdim if (RT->getDecl()->hasFlexibleArrayMember()) 3549314564Sdim return getIndirectReturnResult(Ty); 3550314564Sdim 3551314564Sdim // Sum up bases 3552314564Sdim if (auto CXXRD = dyn_cast<CXXRecordDecl>(RT->getDecl())) { 3553314564Sdim if (CXXRD->isDynamicClass()) { 3554314564Sdim NeededInt = NeededSSE = 0; 3555314564Sdim return getIndirectReturnResult(Ty); 3556314564Sdim } 3557314564Sdim 3558314564Sdim for (const auto &I : CXXRD->bases()) 3559314564Sdim if (classifyRegCallStructTypeImpl(I.getType(), NeededInt, NeededSSE) 3560314564Sdim .isIndirect()) { 3561314564Sdim NeededInt = NeededSSE = 0; 3562314564Sdim return getIndirectReturnResult(Ty); 3563314564Sdim } 3564314564Sdim } 3565314564Sdim 3566314564Sdim // Sum up members 3567314564Sdim for (const auto *FD : RT->getDecl()->fields()) { 3568314564Sdim if (FD->getType()->isRecordType() && !FD->getType()->isUnionType()) { 3569314564Sdim if (classifyRegCallStructTypeImpl(FD->getType(), NeededInt, NeededSSE) 3570314564Sdim .isIndirect()) { 3571314564Sdim NeededInt = NeededSSE = 0; 3572314564Sdim return getIndirectReturnResult(Ty); 3573314564Sdim } 3574314564Sdim } else { 3575314564Sdim unsigned LocalNeededInt, LocalNeededSSE; 3576314564Sdim if (classifyArgumentType(FD->getType(), UINT_MAX, LocalNeededInt, 3577314564Sdim LocalNeededSSE, true) 3578314564Sdim .isIndirect()) { 3579314564Sdim NeededInt = NeededSSE = 0; 3580314564Sdim return getIndirectReturnResult(Ty); 3581314564Sdim } 3582314564Sdim NeededInt += LocalNeededInt; 3583314564Sdim NeededSSE += LocalNeededSSE; 3584314564Sdim } 3585314564Sdim } 3586314564Sdim 3587314564Sdim return ABIArgInfo::getDirect(); 3588314564Sdim} 3589314564Sdim 3590314564SdimABIArgInfo X86_64ABIInfo::classifyRegCallStructType(QualType Ty, 3591314564Sdim unsigned &NeededInt, 3592314564Sdim unsigned &NeededSSE) const { 3593314564Sdim 3594314564Sdim NeededInt = 0; 3595314564Sdim NeededSSE = 0; 3596314564Sdim 3597314564Sdim return classifyRegCallStructTypeImpl(Ty, NeededInt, NeededSSE); 3598314564Sdim} 3599314564Sdim 3600212904Sdimvoid X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const { 3601202379Srdivacky 3602329033Sdim const unsigned CallingConv = FI.getCallingConvention(); 3603329033Sdim // It is possible to force Win64 calling convention on any x86_64 target by 3604329033Sdim // using __attribute__((ms_abi)). In such case to correctly emit Win64 3605329033Sdim // compatible code delegate this call to WinX86_64ABIInfo::computeInfo. 3606329033Sdim if (CallingConv == llvm::CallingConv::Win64) { 3607353358Sdim WinX86_64ABIInfo Win64ABIInfo(CGT, AVXLevel); 3608329033Sdim Win64ABIInfo.computeInfo(FI); 3609329033Sdim return; 3610329033Sdim } 3611212904Sdim 3612329033Sdim bool IsRegCall = CallingConv == llvm::CallingConv::X86_RegCall; 3613329033Sdim 3614202379Srdivacky // Keep track of the number of assigned registers. 3615314564Sdim unsigned FreeIntRegs = IsRegCall ? 11 : 6; 3616314564Sdim unsigned FreeSSERegs = IsRegCall ? 16 : 8; 3617314564Sdim unsigned NeededInt, NeededSSE; 3618202379Srdivacky 3619341825Sdim if (!::classifyReturnType(getCXXABI(), FI, *this)) { 3620327952Sdim if (IsRegCall && FI.getReturnType()->getTypePtr()->isRecordType() && 3621327952Sdim !FI.getReturnType()->getTypePtr()->isUnionType()) { 3622327952Sdim FI.getReturnInfo() = 3623327952Sdim classifyRegCallStructType(FI.getReturnType(), NeededInt, NeededSSE); 3624327952Sdim if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) { 3625327952Sdim FreeIntRegs -= NeededInt; 3626327952Sdim FreeSSERegs -= NeededSSE; 3627327952Sdim } else { 3628327952Sdim FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType()); 3629327952Sdim } 3630327952Sdim } else if (IsRegCall && FI.getReturnType()->getAs<ComplexType>()) { 3631327952Sdim // Complex Long Double Type is passed in Memory when Regcall 3632327952Sdim // calling convention is used. 3633327952Sdim const ComplexType *CT = FI.getReturnType()->getAs<ComplexType>(); 3634327952Sdim if (getContext().getCanonicalType(CT->getElementType()) == 3635327952Sdim getContext().LongDoubleTy) 3636327952Sdim FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType()); 3637327952Sdim } else 3638327952Sdim FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 3639327952Sdim } 3640314564Sdim 3641202379Srdivacky // If the return value is indirect, then the hidden argument is consuming one 3642202379Srdivacky // integer register. 3643202379Srdivacky if (FI.getReturnInfo().isIndirect()) 3644314564Sdim --FreeIntRegs; 3645202379Srdivacky 3646280031Sdim // The chain argument effectively gives us another free register. 3647280031Sdim if (FI.isChainCall()) 3648314564Sdim ++FreeIntRegs; 3649261991Sdim 3650280031Sdim unsigned NumRequiredArgs = FI.getNumRequiredArgs(); 3651202379Srdivacky // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers 3652202379Srdivacky // get assigned (in left-to-right order) for passing as follows... 3653280031Sdim unsigned ArgNo = 0; 3654202379Srdivacky for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 3655280031Sdim it != ie; ++it, ++ArgNo) { 3656280031Sdim bool IsNamedArg = ArgNo < NumRequiredArgs; 3657261991Sdim 3658314564Sdim if (IsRegCall && it->type->isStructureOrClassType()) 3659314564Sdim it->info = classifyRegCallStructType(it->type, NeededInt, NeededSSE); 3660314564Sdim else 3661314564Sdim it->info = classifyArgumentType(it->type, FreeIntRegs, NeededInt, 3662314564Sdim NeededSSE, IsNamedArg); 3663202379Srdivacky 3664202379Srdivacky // AMD64-ABI 3.2.3p3: If there are no registers available for any 3665202379Srdivacky // eightbyte of an argument, the whole argument is passed on the 3666202379Srdivacky // stack. If registers have already been assigned for some 3667202379Srdivacky // eightbytes of such an argument, the assignments get reverted. 3668314564Sdim if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) { 3669314564Sdim FreeIntRegs -= NeededInt; 3670314564Sdim FreeSSERegs -= NeededSSE; 3671202379Srdivacky } else { 3672314564Sdim it->info = getIndirectResult(it->type, FreeIntRegs); 3673202379Srdivacky } 3674202379Srdivacky } 3675202379Srdivacky} 3676202379Srdivacky 3677296417Sdimstatic Address EmitX86_64VAArgFromMemory(CodeGenFunction &CGF, 3678296417Sdim Address VAListAddr, QualType Ty) { 3679353358Sdim Address overflow_arg_area_p = 3680353358Sdim CGF.Builder.CreateStructGEP(VAListAddr, 2, "overflow_arg_area_p"); 3681202379Srdivacky llvm::Value *overflow_arg_area = 3682202379Srdivacky CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area"); 3683202379Srdivacky 3684202379Srdivacky // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16 3685202379Srdivacky // byte boundary if alignment needed by type exceeds 8 byte boundary. 3686234353Sdim // It isn't stated explicitly in the standard, but in practice we use 3687234353Sdim // alignment greater than 16 where necessary. 3688296417Sdim CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty); 3689296417Sdim if (Align > CharUnits::fromQuantity(8)) { 3690296417Sdim overflow_arg_area = emitRoundPointerUpToAlignment(CGF, overflow_arg_area, 3691296417Sdim Align); 3692202379Srdivacky } 3693202379Srdivacky 3694202379Srdivacky // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area. 3695226633Sdim llvm::Type *LTy = CGF.ConvertTypeForMem(Ty); 3696202379Srdivacky llvm::Value *Res = 3697202379Srdivacky CGF.Builder.CreateBitCast(overflow_arg_area, 3698202379Srdivacky llvm::PointerType::getUnqual(LTy)); 3699202379Srdivacky 3700202379Srdivacky // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to: 3701202379Srdivacky // l->overflow_arg_area + sizeof(type). 3702202379Srdivacky // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to 3703202379Srdivacky // an 8 byte boundary. 3704202379Srdivacky 3705202379Srdivacky uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8; 3706202379Srdivacky llvm::Value *Offset = 3707210299Sed llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7) & ~7); 3708202379Srdivacky overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset, 3709202379Srdivacky "overflow_arg_area.next"); 3710202379Srdivacky CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p); 3711202379Srdivacky 3712202379Srdivacky // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type. 3713296417Sdim return Address(Res, Align); 3714202379Srdivacky} 3715202379Srdivacky 3716296417SdimAddress X86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 3717296417Sdim QualType Ty) const { 3718202379Srdivacky // Assume that va_list type is correct; should be pointer to LLVM type: 3719202379Srdivacky // struct { 3720202379Srdivacky // i32 gp_offset; 3721202379Srdivacky // i32 fp_offset; 3722202379Srdivacky // i8* overflow_arg_area; 3723202379Srdivacky // i8* reg_save_area; 3724202379Srdivacky // }; 3725202379Srdivacky unsigned neededInt, neededSSE; 3726212904Sdim 3727296417Sdim Ty = getContext().getCanonicalType(Ty); 3728288943Sdim ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE, 3729261991Sdim /*isNamedArg*/false); 3730202379Srdivacky 3731202379Srdivacky // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed 3732202379Srdivacky // in the registers. If not go to step 7. 3733202379Srdivacky if (!neededInt && !neededSSE) 3734296417Sdim return EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty); 3735202379Srdivacky 3736202379Srdivacky // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of 3737202379Srdivacky // general purpose registers needed to pass type and num_fp to hold 3738202379Srdivacky // the number of floating point registers needed. 3739202379Srdivacky 3740202379Srdivacky // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into 3741202379Srdivacky // registers. In the case: l->gp_offset > 48 - num_gp * 8 or 3742202379Srdivacky // l->fp_offset > 304 - num_fp * 16 go to step 7. 3743202379Srdivacky // 3744202379Srdivacky // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of 3745202379Srdivacky // register save space). 3746202379Srdivacky 3747276479Sdim llvm::Value *InRegs = nullptr; 3748296417Sdim Address gp_offset_p = Address::invalid(), fp_offset_p = Address::invalid(); 3749296417Sdim llvm::Value *gp_offset = nullptr, *fp_offset = nullptr; 3750202379Srdivacky if (neededInt) { 3751353358Sdim gp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 0, "gp_offset_p"); 3752202379Srdivacky gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset"); 3753210299Sed InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8); 3754210299Sed InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp"); 3755202379Srdivacky } 3756202379Srdivacky 3757202379Srdivacky if (neededSSE) { 3758353358Sdim fp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 1, "fp_offset_p"); 3759202379Srdivacky fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset"); 3760202379Srdivacky llvm::Value *FitsInFP = 3761210299Sed llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16); 3762210299Sed FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp"); 3763202379Srdivacky InRegs = InRegs ? CGF.Builder.CreateAnd(InRegs, FitsInFP) : FitsInFP; 3764202379Srdivacky } 3765202379Srdivacky 3766202379Srdivacky llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg"); 3767202379Srdivacky llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem"); 3768202379Srdivacky llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end"); 3769202379Srdivacky CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock); 3770202379Srdivacky 3771202379Srdivacky // Emit code to load the value if it was passed in registers. 3772202379Srdivacky 3773202379Srdivacky CGF.EmitBlock(InRegBlock); 3774202379Srdivacky 3775202379Srdivacky // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with 3776202379Srdivacky // an offset of l->gp_offset and/or l->fp_offset. This may require 3777202379Srdivacky // copying to a temporary location in case the parameter is passed 3778202379Srdivacky // in different register classes or requires an alignment greater 3779202379Srdivacky // than 8 for general purpose registers and 16 for XMM registers. 3780202379Srdivacky // 3781202379Srdivacky // FIXME: This really results in shameful code when we end up needing to 3782202379Srdivacky // collect arguments from different places; often what should result in a 3783202379Srdivacky // simple assembling of a structure from scattered addresses has many more 3784202379Srdivacky // loads than necessary. Can we clean this up? 3785226633Sdim llvm::Type *LTy = CGF.ConvertTypeForMem(Ty); 3786296417Sdim llvm::Value *RegSaveArea = CGF.Builder.CreateLoad( 3787353358Sdim CGF.Builder.CreateStructGEP(VAListAddr, 3), "reg_save_area"); 3788296417Sdim 3789296417Sdim Address RegAddr = Address::invalid(); 3790202379Srdivacky if (neededInt && neededSSE) { 3791202379Srdivacky // FIXME: Cleanup. 3792212904Sdim assert(AI.isDirect() && "Unexpected ABI info for mixed regs"); 3793226633Sdim llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType()); 3794296417Sdim Address Tmp = CGF.CreateMemTemp(Ty); 3795296417Sdim Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST); 3796202379Srdivacky assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs"); 3797226633Sdim llvm::Type *TyLo = ST->getElementType(0); 3798226633Sdim llvm::Type *TyHi = ST->getElementType(1); 3799212904Sdim assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) && 3800202379Srdivacky "Unexpected ABI info for mixed regs"); 3801226633Sdim llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo); 3802226633Sdim llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi); 3803296417Sdim llvm::Value *GPAddr = CGF.Builder.CreateGEP(RegSaveArea, gp_offset); 3804296417Sdim llvm::Value *FPAddr = CGF.Builder.CreateGEP(RegSaveArea, fp_offset); 3805276479Sdim llvm::Value *RegLoAddr = TyLo->isFPOrFPVectorTy() ? FPAddr : GPAddr; 3806276479Sdim llvm::Value *RegHiAddr = TyLo->isFPOrFPVectorTy() ? GPAddr : FPAddr; 3807296417Sdim 3808296417Sdim // Copy the first element. 3809314564Sdim // FIXME: Our choice of alignment here and below is probably pessimistic. 3810314564Sdim llvm::Value *V = CGF.Builder.CreateAlignedLoad( 3811314564Sdim TyLo, CGF.Builder.CreateBitCast(RegLoAddr, PTyLo), 3812314564Sdim CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyLo))); 3813353358Sdim CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0)); 3814202379Srdivacky 3815296417Sdim // Copy the second element. 3816314564Sdim V = CGF.Builder.CreateAlignedLoad( 3817314564Sdim TyHi, CGF.Builder.CreateBitCast(RegHiAddr, PTyHi), 3818314564Sdim CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyHi))); 3819353358Sdim CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1)); 3820296417Sdim 3821296417Sdim RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy); 3822202379Srdivacky } else if (neededInt) { 3823296417Sdim RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, gp_offset), 3824296417Sdim CharUnits::fromQuantity(8)); 3825296417Sdim RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy); 3826261991Sdim 3827261991Sdim // Copy to a temporary if necessary to ensure the appropriate alignment. 3828261991Sdim std::pair<CharUnits, CharUnits> SizeAlign = 3829296417Sdim getContext().getTypeInfoInChars(Ty); 3830261991Sdim uint64_t TySize = SizeAlign.first.getQuantity(); 3831296417Sdim CharUnits TyAlign = SizeAlign.second; 3832296417Sdim 3833296417Sdim // Copy into a temporary if the type is more aligned than the 3834296417Sdim // register save area. 3835296417Sdim if (TyAlign.getQuantity() > 8) { 3836296417Sdim Address Tmp = CGF.CreateMemTemp(Ty); 3837296417Sdim CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, false); 3838261991Sdim RegAddr = Tmp; 3839261991Sdim } 3840341825Sdim 3841210299Sed } else if (neededSSE == 1) { 3842296417Sdim RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset), 3843296417Sdim CharUnits::fromQuantity(16)); 3844296417Sdim RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy); 3845202379Srdivacky } else { 3846210299Sed assert(neededSSE == 2 && "Invalid number of needed registers!"); 3847210299Sed // SSE registers are spaced 16 bytes apart in the register save 3848210299Sed // area, we need to collect the two eightbytes together. 3849296417Sdim // The ABI isn't explicit about this, but it seems reasonable 3850296417Sdim // to assume that the slots are 16-byte aligned, since the stack is 3851296417Sdim // naturally 16-byte aligned and the prologue is expected to store 3852296417Sdim // all the SSE registers to the RSA. 3853296417Sdim Address RegAddrLo = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset), 3854296417Sdim CharUnits::fromQuantity(16)); 3855296417Sdim Address RegAddrHi = 3856296417Sdim CGF.Builder.CreateConstInBoundsByteGEP(RegAddrLo, 3857296417Sdim CharUnits::fromQuantity(16)); 3858341825Sdim llvm::Type *ST = AI.canHaveCoerceToType() 3859341825Sdim ? AI.getCoerceToType() 3860341825Sdim : llvm::StructType::get(CGF.DoubleTy, CGF.DoubleTy); 3861296417Sdim llvm::Value *V; 3862296417Sdim Address Tmp = CGF.CreateMemTemp(Ty); 3863296417Sdim Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST); 3864341825Sdim V = CGF.Builder.CreateLoad(CGF.Builder.CreateElementBitCast( 3865341825Sdim RegAddrLo, ST->getStructElementType(0))); 3866353358Sdim CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0)); 3867341825Sdim V = CGF.Builder.CreateLoad(CGF.Builder.CreateElementBitCast( 3868341825Sdim RegAddrHi, ST->getStructElementType(1))); 3869353358Sdim CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1)); 3870296417Sdim 3871296417Sdim RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy); 3872202379Srdivacky } 3873202379Srdivacky 3874202379Srdivacky // AMD64-ABI 3.5.7p5: Step 5. Set: 3875202379Srdivacky // l->gp_offset = l->gp_offset + num_gp * 8 3876202379Srdivacky // l->fp_offset = l->fp_offset + num_fp * 16. 3877202379Srdivacky if (neededInt) { 3878210299Sed llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8); 3879202379Srdivacky CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset), 3880202379Srdivacky gp_offset_p); 3881202379Srdivacky } 3882202379Srdivacky if (neededSSE) { 3883210299Sed llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16); 3884202379Srdivacky CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset), 3885202379Srdivacky fp_offset_p); 3886202379Srdivacky } 3887202379Srdivacky CGF.EmitBranch(ContBlock); 3888202379Srdivacky 3889202379Srdivacky // Emit code to load the value if it was passed in memory. 3890202379Srdivacky 3891202379Srdivacky CGF.EmitBlock(InMemBlock); 3892296417Sdim Address MemAddr = EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty); 3893202379Srdivacky 3894202379Srdivacky // Return the appropriate result. 3895202379Srdivacky 3896202379Srdivacky CGF.EmitBlock(ContBlock); 3897296417Sdim Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock, MemAddr, InMemBlock, 3898296417Sdim "vaarg.addr"); 3899202379Srdivacky return ResAddr; 3900202379Srdivacky} 3901202379Srdivacky 3902296417SdimAddress X86_64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr, 3903296417Sdim QualType Ty) const { 3904296417Sdim return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false, 3905296417Sdim CGF.getContext().getTypeInfoInChars(Ty), 3906296417Sdim CharUnits::fromQuantity(8), 3907296417Sdim /*allowHigherAlign*/ false); 3908296417Sdim} 3909296417Sdim 3910314564SdimABIArgInfo 3911314564SdimWinX86_64ABIInfo::reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs, 3912314564Sdim const ABIArgInfo ¤t) const { 3913314564Sdim // Assumes vectorCall calling convention. 3914314564Sdim const Type *Base = nullptr; 3915314564Sdim uint64_t NumElts = 0; 3916314564Sdim 3917314564Sdim if (!Ty->isBuiltinType() && !Ty->isVectorType() && 3918314564Sdim isHomogeneousAggregate(Ty, Base, NumElts) && FreeSSERegs >= NumElts) { 3919314564Sdim FreeSSERegs -= NumElts; 3920314564Sdim return getDirectX86Hva(); 3921314564Sdim } 3922314564Sdim return current; 3923314564Sdim} 3924314564Sdim 3925280031SdimABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs, 3926314564Sdim bool IsReturnType, bool IsVectorCall, 3927314564Sdim bool IsRegCall) const { 3928210299Sed 3929218893Sdim if (Ty->isVoidType()) 3930218893Sdim return ABIArgInfo::getIgnore(); 3931210299Sed 3932218893Sdim if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 3933218893Sdim Ty = EnumTy->getDecl()->getIntegerType(); 3934212904Sdim 3935280031Sdim TypeInfo Info = getContext().getTypeInfo(Ty); 3936280031Sdim uint64_t Width = Info.Width; 3937296417Sdim CharUnits Align = getContext().toCharUnitsFromBits(Info.Align); 3938212904Sdim 3939276479Sdim const RecordType *RT = Ty->getAs<RecordType>(); 3940276479Sdim if (RT) { 3941276479Sdim if (!IsReturnType) { 3942261991Sdim if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI())) 3943296417Sdim return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory); 3944251662Sdim } 3945251662Sdim 3946251662Sdim if (RT->getDecl()->hasFlexibleArrayMember()) 3947296417Sdim return getNaturalAlignIndirect(Ty, /*ByVal=*/false); 3948296417Sdim 3949276479Sdim } 3950219077Sdim 3951314564Sdim const Type *Base = nullptr; 3952314564Sdim uint64_t NumElts = 0; 3953280031Sdim // vectorcall adds the concept of a homogenous vector aggregate, similar to 3954280031Sdim // other targets. 3955314564Sdim if ((IsVectorCall || IsRegCall) && 3956314564Sdim isHomogeneousAggregate(Ty, Base, NumElts)) { 3957314564Sdim if (IsRegCall) { 3958314564Sdim if (FreeSSERegs >= NumElts) { 3959314564Sdim FreeSSERegs -= NumElts; 3960314564Sdim if (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType()) 3961314564Sdim return ABIArgInfo::getDirect(); 3962314564Sdim return ABIArgInfo::getExpand(); 3963314564Sdim } 3964314564Sdim return ABIArgInfo::getIndirect(Align, /*ByVal=*/false); 3965314564Sdim } else if (IsVectorCall) { 3966314564Sdim if (FreeSSERegs >= NumElts && 3967314564Sdim (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())) { 3968314564Sdim FreeSSERegs -= NumElts; 3969280031Sdim return ABIArgInfo::getDirect(); 3970314564Sdim } else if (IsReturnType) { 3971314564Sdim return ABIArgInfo::getExpand(); 3972314564Sdim } else if (!Ty->isBuiltinType() && !Ty->isVectorType()) { 3973314564Sdim // HVAs are delayed and reclassified in the 2nd step. 3974314564Sdim return ABIArgInfo::getIndirect(Align, /*ByVal=*/false); 3975314564Sdim } 3976280031Sdim } 3977280031Sdim } 3978280031Sdim 3979276479Sdim if (Ty->isMemberPointerType()) { 3980276479Sdim // If the member pointer is represented by an LLVM int or ptr, pass it 3981276479Sdim // directly. 3982276479Sdim llvm::Type *LLTy = CGT.ConvertType(Ty); 3983276479Sdim if (LLTy->isPointerTy() || LLTy->isIntegerTy()) 3984276479Sdim return ABIArgInfo::getDirect(); 3985276479Sdim } 3986276479Sdim 3987288943Sdim if (RT || Ty->isAnyComplexType() || Ty->isMemberPointerType()) { 3988219077Sdim // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is 3989219077Sdim // not 1, 2, 4, or 8 bytes, must be passed by reference." 3990280031Sdim if (Width > 64 || !llvm::isPowerOf2_64(Width)) 3991296417Sdim return getNaturalAlignIndirect(Ty, /*ByVal=*/false); 3992202379Srdivacky 3993276479Sdim // Otherwise, coerce it to a small integer. 3994280031Sdim return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Width)); 3995202379Srdivacky } 3996202379Srdivacky 3997344779Sdim if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) { 3998344779Sdim switch (BT->getKind()) { 3999344779Sdim case BuiltinType::Bool: 4000344779Sdim // Bool type is always extended to the ABI, other builtin types are not 4001344779Sdim // extended. 4002344779Sdim return ABIArgInfo::getExtend(Ty); 4003202379Srdivacky 4004344779Sdim case BuiltinType::LongDouble: 4005344779Sdim // Mingw64 GCC uses the old 80 bit extended precision floating point 4006344779Sdim // unit. It passes them indirectly through memory. 4007344779Sdim if (IsMingw64) { 4008344779Sdim const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat(); 4009344779Sdim if (LDF == &llvm::APFloat::x87DoubleExtended()) 4010344779Sdim return ABIArgInfo::getIndirect(Align, /*ByVal=*/false); 4011344779Sdim } 4012344779Sdim break; 4013344779Sdim 4014344779Sdim case BuiltinType::Int128: 4015344779Sdim case BuiltinType::UInt128: 4016344779Sdim // If it's a parameter type, the normal ABI rule is that arguments larger 4017344779Sdim // than 8 bytes are passed indirectly. GCC follows it. We follow it too, 4018344779Sdim // even though it isn't particularly efficient. 4019344779Sdim if (!IsReturnType) 4020344779Sdim return ABIArgInfo::getIndirect(Align, /*ByVal=*/false); 4021344779Sdim 4022344779Sdim // Mingw64 GCC returns i128 in XMM0. Coerce to v2i64 to handle that. 4023344779Sdim // Clang matches them for compatibility. 4024344779Sdim return ABIArgInfo::getDirect( 4025344779Sdim llvm::VectorType::get(llvm::Type::getInt64Ty(getVMContext()), 2)); 4026344779Sdim 4027344779Sdim default: 4028344779Sdim break; 4029344779Sdim } 4030292735Sdim } 4031292735Sdim 4032218893Sdim return ABIArgInfo::getDirect(); 4033202379Srdivacky} 4034202379Srdivacky 4035314564Sdimvoid WinX86_64ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI, 4036314564Sdim unsigned FreeSSERegs, 4037314564Sdim bool IsVectorCall, 4038314564Sdim bool IsRegCall) const { 4039314564Sdim unsigned Count = 0; 4040314564Sdim for (auto &I : FI.arguments()) { 4041321369Sdim // Vectorcall in x64 only permits the first 6 arguments to be passed 4042321369Sdim // as XMM/YMM registers. 4043314564Sdim if (Count < VectorcallMaxParamNumAsReg) 4044314564Sdim I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall); 4045314564Sdim else { 4046314564Sdim // Since these cannot be passed in registers, pretend no registers 4047314564Sdim // are left. 4048314564Sdim unsigned ZeroSSERegsAvail = 0; 4049314564Sdim I.info = classify(I.type, /*FreeSSERegs=*/ZeroSSERegsAvail, false, 4050314564Sdim IsVectorCall, IsRegCall); 4051314564Sdim } 4052314564Sdim ++Count; 4053314564Sdim } 4054314564Sdim 4055314564Sdim for (auto &I : FI.arguments()) { 4056321369Sdim I.info = reclassifyHvaArgType(I.type, FreeSSERegs, I.info); 4057314564Sdim } 4058314564Sdim} 4059314564Sdim 4060218893Sdimvoid WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const { 4061353358Sdim const unsigned CC = FI.getCallingConvention(); 4062353358Sdim bool IsVectorCall = CC == llvm::CallingConv::X86_VectorCall; 4063353358Sdim bool IsRegCall = CC == llvm::CallingConv::X86_RegCall; 4064280031Sdim 4065353358Sdim // If __attribute__((sysv_abi)) is in use, use the SysV argument 4066353358Sdim // classification rules. 4067353358Sdim if (CC == llvm::CallingConv::X86_64_SysV) { 4068353358Sdim X86_64ABIInfo SysVABIInfo(CGT, AVXLevel); 4069353358Sdim SysVABIInfo.computeInfo(FI); 4070353358Sdim return; 4071353358Sdim } 4072353358Sdim 4073314564Sdim unsigned FreeSSERegs = 0; 4074314564Sdim if (IsVectorCall) { 4075314564Sdim // We can use up to 4 SSE return registers with vectorcall. 4076314564Sdim FreeSSERegs = 4; 4077314564Sdim } else if (IsRegCall) { 4078314564Sdim // RegCall gives us 16 SSE registers. 4079314564Sdim FreeSSERegs = 16; 4080314564Sdim } 4081314564Sdim 4082276479Sdim if (!getCXXABI().classifyReturnType(FI)) 4083314564Sdim FI.getReturnInfo() = classify(FI.getReturnType(), FreeSSERegs, true, 4084314564Sdim IsVectorCall, IsRegCall); 4085202379Srdivacky 4086314564Sdim if (IsVectorCall) { 4087314564Sdim // We can use up to 6 SSE register parameters with vectorcall. 4088314564Sdim FreeSSERegs = 6; 4089314564Sdim } else if (IsRegCall) { 4090314564Sdim // RegCall gives us 16 SSE registers, we can reuse the return registers. 4091314564Sdim FreeSSERegs = 16; 4092314564Sdim } 4093314564Sdim 4094314564Sdim if (IsVectorCall) { 4095314564Sdim computeVectorCallArgs(FI, FreeSSERegs, IsVectorCall, IsRegCall); 4096314564Sdim } else { 4097314564Sdim for (auto &I : FI.arguments()) 4098314564Sdim I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall); 4099314564Sdim } 4100314564Sdim 4101202379Srdivacky} 4102202379Srdivacky 4103296417SdimAddress WinX86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 4104296417Sdim QualType Ty) const { 4105314564Sdim 4106314564Sdim bool IsIndirect = false; 4107314564Sdim 4108314564Sdim // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is 4109314564Sdim // not 1, 2, 4, or 8 bytes, must be passed by reference." 4110314564Sdim if (isAggregateTypeForABI(Ty) || Ty->isMemberPointerType()) { 4111314564Sdim uint64_t Width = getContext().getTypeSize(Ty); 4112314564Sdim IsIndirect = Width > 64 || !llvm::isPowerOf2_64(Width); 4113314564Sdim } 4114314564Sdim 4115314564Sdim return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, 4116296417Sdim CGF.getContext().getTypeInfoInChars(Ty), 4117296417Sdim CharUnits::fromQuantity(8), 4118296417Sdim /*allowHigherAlign*/ false); 4119202379Srdivacky} 4120202379Srdivacky 4121205219Srdivacky// PowerPC-32 4122205219Srdivackynamespace { 4123275759Sdim/// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information. 4124275759Sdimclass PPC32_SVR4_ABIInfo : public DefaultABIInfo { 4125327952Sdim bool IsSoftFloatABI; 4126363496Sdim bool IsRetSmallStructInRegABI; 4127327952Sdim 4128327952Sdim CharUnits getParamTypeAlignment(QualType Ty) const; 4129327952Sdim 4130205219Srdivackypublic: 4131363496Sdim PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI, 4132363496Sdim bool RetSmallStructInRegABI) 4133363496Sdim : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI), 4134363496Sdim IsRetSmallStructInRegABI(RetSmallStructInRegABI) {} 4135212904Sdim 4136363496Sdim ABIArgInfo classifyReturnType(QualType RetTy) const; 4137363496Sdim 4138363496Sdim void computeInfo(CGFunctionInfo &FI) const override { 4139363496Sdim if (!getCXXABI().classifyReturnType(FI)) 4140363496Sdim FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 4141363496Sdim for (auto &I : FI.arguments()) 4142363496Sdim I.info = classifyArgumentType(I.type); 4143363496Sdim } 4144363496Sdim 4145296417Sdim Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 4146296417Sdim QualType Ty) const override; 4147275759Sdim}; 4148275759Sdim 4149275759Sdimclass PPC32TargetCodeGenInfo : public TargetCodeGenInfo { 4150275759Sdimpublic: 4151363496Sdim PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI, 4152363496Sdim bool RetSmallStructInRegABI) 4153363496Sdim : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT, SoftFloatABI, 4154363496Sdim RetSmallStructInRegABI)) {} 4155275759Sdim 4156363496Sdim static bool isStructReturnInRegABI(const llvm::Triple &Triple, 4157363496Sdim const CodeGenOptions &Opts); 4158363496Sdim 4159276479Sdim int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override { 4160205219Srdivacky // This is recovered from gcc output. 4161205219Srdivacky return 1; // r1 is the dedicated stack pointer 4162205219Srdivacky } 4163205219Srdivacky 4164205219Srdivacky bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 4165276479Sdim llvm::Value *Address) const override; 4166205219Srdivacky}; 4167327952Sdim} 4168205219Srdivacky 4169327952SdimCharUnits PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const { 4170327952Sdim // Complex types are passed just like their elements 4171327952Sdim if (const ComplexType *CTy = Ty->getAs<ComplexType>()) 4172327952Sdim Ty = CTy->getElementType(); 4173327952Sdim 4174327952Sdim if (Ty->isVectorType()) 4175327952Sdim return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 4176327952Sdim : 4); 4177327952Sdim 4178327952Sdim // For single-element float/vector structs, we consider the whole type 4179327952Sdim // to have the same alignment requirements as its single element. 4180327952Sdim const Type *AlignTy = nullptr; 4181327952Sdim if (const Type *EltType = isSingleElementStruct(Ty, getContext())) { 4182327952Sdim const BuiltinType *BT = EltType->getAs<BuiltinType>(); 4183327952Sdim if ((EltType->isVectorType() && getContext().getTypeSize(EltType) == 128) || 4184327952Sdim (BT && BT->isFloatingPoint())) 4185327952Sdim AlignTy = EltType; 4186327952Sdim } 4187327952Sdim 4188327952Sdim if (AlignTy) 4189327952Sdim return CharUnits::fromQuantity(AlignTy->isVectorType() ? 16 : 4); 4190327952Sdim return CharUnits::fromQuantity(4); 4191205219Srdivacky} 4192205219Srdivacky 4193363496SdimABIArgInfo PPC32_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const { 4194363496Sdim uint64_t Size; 4195363496Sdim 4196363496Sdim // -msvr4-struct-return puts small aggregates in GPR3 and GPR4. 4197363496Sdim if (isAggregateTypeForABI(RetTy) && IsRetSmallStructInRegABI && 4198363496Sdim (Size = getContext().getTypeSize(RetTy)) <= 64) { 4199363496Sdim // System V ABI (1995), page 3-22, specified: 4200363496Sdim // > A structure or union whose size is less than or equal to 8 bytes 4201363496Sdim // > shall be returned in r3 and r4, as if it were first stored in the 4202363496Sdim // > 8-byte aligned memory area and then the low addressed word were 4203363496Sdim // > loaded into r3 and the high-addressed word into r4. Bits beyond 4204363496Sdim // > the last member of the structure or union are not defined. 4205363496Sdim // 4206363496Sdim // GCC for big-endian PPC32 inserts the pad before the first member, 4207363496Sdim // not "beyond the last member" of the struct. To stay compatible 4208363496Sdim // with GCC, we coerce the struct to an integer of the same size. 4209363496Sdim // LLVM will extend it and return i32 in r3, or i64 in r3:r4. 4210363496Sdim if (Size == 0) 4211363496Sdim return ABIArgInfo::getIgnore(); 4212363496Sdim else { 4213363496Sdim llvm::Type *CoerceTy = llvm::Type::getIntNTy(getVMContext(), Size); 4214363496Sdim return ABIArgInfo::getDirect(CoerceTy); 4215363496Sdim } 4216363496Sdim } 4217363496Sdim 4218363496Sdim return DefaultABIInfo::classifyReturnType(RetTy); 4219363496Sdim} 4220363496Sdim 4221309124Sdim// TODO: this implementation is now likely redundant with 4222309124Sdim// DefaultABIInfo::EmitVAArg. 4223296417SdimAddress PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList, 4224296417Sdim QualType Ty) const { 4225327952Sdim if (getTarget().getTriple().isOSDarwin()) { 4226327952Sdim auto TI = getContext().getTypeInfoInChars(Ty); 4227327952Sdim TI.second = getParamTypeAlignment(Ty); 4228327952Sdim 4229327952Sdim CharUnits SlotSize = CharUnits::fromQuantity(4); 4230327952Sdim return emitVoidPtrVAArg(CGF, VAList, Ty, 4231327952Sdim classifyArgumentType(Ty).isIndirect(), TI, SlotSize, 4232327952Sdim /*AllowHigherAlign=*/true); 4233327952Sdim } 4234327952Sdim 4235296417Sdim const unsigned OverflowLimit = 8; 4236275759Sdim if (const ComplexType *CTy = Ty->getAs<ComplexType>()) { 4237275759Sdim // TODO: Implement this. For now ignore. 4238275759Sdim (void)CTy; 4239309124Sdim return Address::invalid(); // FIXME? 4240275759Sdim } 4241275759Sdim 4242296417Sdim // struct __va_list_tag { 4243296417Sdim // unsigned char gpr; 4244296417Sdim // unsigned char fpr; 4245296417Sdim // unsigned short reserved; 4246296417Sdim // void *overflow_arg_area; 4247296417Sdim // void *reg_save_area; 4248296417Sdim // }; 4249296417Sdim 4250275759Sdim bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64; 4251288943Sdim bool isInt = 4252288943Sdim Ty->isIntegerType() || Ty->isPointerType() || Ty->isAggregateType(); 4253296417Sdim bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(Ty) == 64; 4254275759Sdim 4255296417Sdim // All aggregates are passed indirectly? That doesn't seem consistent 4256296417Sdim // with the argument-lowering code. 4257296417Sdim bool isIndirect = Ty->isAggregateType(); 4258296417Sdim 4259275759Sdim CGBuilderTy &Builder = CGF.Builder; 4260296417Sdim 4261296417Sdim // The calling convention either uses 1-2 GPRs or 1 FPR. 4262296417Sdim Address NumRegsAddr = Address::invalid(); 4263296417Sdim if (isInt || IsSoftFloatABI) { 4264353358Sdim NumRegsAddr = Builder.CreateStructGEP(VAList, 0, "gpr"); 4265296417Sdim } else { 4266353358Sdim NumRegsAddr = Builder.CreateStructGEP(VAList, 1, "fpr"); 4267275759Sdim } 4268275759Sdim 4269296417Sdim llvm::Value *NumRegs = Builder.CreateLoad(NumRegsAddr, "numUsedRegs"); 4270275759Sdim 4271296417Sdim // "Align" the register count when TY is i64. 4272296417Sdim if (isI64 || (isF64 && IsSoftFloatABI)) { 4273296417Sdim NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(1)); 4274296417Sdim NumRegs = Builder.CreateAnd(NumRegs, Builder.getInt8((uint8_t) ~1U)); 4275296417Sdim } 4276275759Sdim 4277296417Sdim llvm::Value *CC = 4278296417Sdim Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond"); 4279275759Sdim 4280275759Sdim llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs"); 4281275759Sdim llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow"); 4282275759Sdim llvm::BasicBlock *Cont = CGF.createBasicBlock("cont"); 4283275759Sdim 4284275759Sdim Builder.CreateCondBr(CC, UsingRegs, UsingOverflow); 4285275759Sdim 4286296417Sdim llvm::Type *DirectTy = CGF.ConvertType(Ty); 4287296417Sdim if (isIndirect) DirectTy = DirectTy->getPointerTo(0); 4288275759Sdim 4289296417Sdim // Case 1: consume registers. 4290296417Sdim Address RegAddr = Address::invalid(); 4291296417Sdim { 4292296417Sdim CGF.EmitBlock(UsingRegs); 4293296417Sdim 4294353358Sdim Address RegSaveAreaPtr = Builder.CreateStructGEP(VAList, 4); 4295296417Sdim RegAddr = Address(Builder.CreateLoad(RegSaveAreaPtr), 4296296417Sdim CharUnits::fromQuantity(8)); 4297296417Sdim assert(RegAddr.getElementType() == CGF.Int8Ty); 4298296417Sdim 4299296417Sdim // Floating-point registers start after the general-purpose registers. 4300296417Sdim if (!(isInt || IsSoftFloatABI)) { 4301296417Sdim RegAddr = Builder.CreateConstInBoundsByteGEP(RegAddr, 4302296417Sdim CharUnits::fromQuantity(32)); 4303296417Sdim } 4304296417Sdim 4305296417Sdim // Get the address of the saved value by scaling the number of 4306341825Sdim // registers we've used by the number of 4307296417Sdim CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8); 4308296417Sdim llvm::Value *RegOffset = 4309296417Sdim Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity())); 4310296417Sdim RegAddr = Address(Builder.CreateInBoundsGEP(CGF.Int8Ty, 4311296417Sdim RegAddr.getPointer(), RegOffset), 4312296417Sdim RegAddr.getAlignment().alignmentOfArrayElement(RegSize)); 4313296417Sdim RegAddr = Builder.CreateElementBitCast(RegAddr, DirectTy); 4314296417Sdim 4315296417Sdim // Increase the used-register count. 4316296417Sdim NumRegs = 4317341825Sdim Builder.CreateAdd(NumRegs, 4318296417Sdim Builder.getInt8((isI64 || (isF64 && IsSoftFloatABI)) ? 2 : 1)); 4319296417Sdim Builder.CreateStore(NumRegs, NumRegsAddr); 4320296417Sdim 4321296417Sdim CGF.EmitBranch(Cont); 4322275759Sdim } 4323275759Sdim 4324296417Sdim // Case 2: consume space in the overflow area. 4325296417Sdim Address MemAddr = Address::invalid(); 4326296417Sdim { 4327296417Sdim CGF.EmitBlock(UsingOverflow); 4328275759Sdim 4329296417Sdim Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr); 4330275759Sdim 4331296417Sdim // Everything in the overflow area is rounded up to a size of at least 4. 4332296417Sdim CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4); 4333296417Sdim 4334296417Sdim CharUnits Size; 4335296417Sdim if (!isIndirect) { 4336296417Sdim auto TypeInfo = CGF.getContext().getTypeInfoInChars(Ty); 4337309124Sdim Size = TypeInfo.first.alignTo(OverflowAreaAlign); 4338296417Sdim } else { 4339296417Sdim Size = CGF.getPointerSize(); 4340296417Sdim } 4341296417Sdim 4342353358Sdim Address OverflowAreaAddr = Builder.CreateStructGEP(VAList, 3); 4343296417Sdim Address OverflowArea(Builder.CreateLoad(OverflowAreaAddr, "argp.cur"), 4344296417Sdim OverflowAreaAlign); 4345296417Sdim // Round up address of argument to alignment 4346296417Sdim CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty); 4347296417Sdim if (Align > OverflowAreaAlign) { 4348296417Sdim llvm::Value *Ptr = OverflowArea.getPointer(); 4349296417Sdim OverflowArea = Address(emitRoundPointerUpToAlignment(CGF, Ptr, Align), 4350296417Sdim Align); 4351296417Sdim } 4352341825Sdim 4353296417Sdim MemAddr = Builder.CreateElementBitCast(OverflowArea, DirectTy); 4354296417Sdim 4355296417Sdim // Increase the overflow area. 4356296417Sdim OverflowArea = Builder.CreateConstInBoundsByteGEP(OverflowArea, Size); 4357296417Sdim Builder.CreateStore(OverflowArea.getPointer(), OverflowAreaAddr); 4358296417Sdim CGF.EmitBranch(Cont); 4359296417Sdim } 4360296417Sdim 4361275759Sdim CGF.EmitBlock(Cont); 4362275759Sdim 4363296417Sdim // Merge the cases with a phi. 4364296417Sdim Address Result = emitMergePHI(CGF, RegAddr, UsingRegs, MemAddr, UsingOverflow, 4365296417Sdim "vaarg.addr"); 4366275759Sdim 4367296417Sdim // Load the pointer if the argument was passed indirectly. 4368296417Sdim if (isIndirect) { 4369296417Sdim Result = Address(Builder.CreateLoad(Result, "aggr"), 4370296417Sdim getContext().getTypeAlignInChars(Ty)); 4371275759Sdim } 4372275759Sdim 4373275759Sdim return Result; 4374275759Sdim} 4375275759Sdim 4376363496Sdimbool PPC32TargetCodeGenInfo::isStructReturnInRegABI( 4377363496Sdim const llvm::Triple &Triple, const CodeGenOptions &Opts) { 4378363496Sdim assert(Triple.getArch() == llvm::Triple::ppc); 4379363496Sdim 4380363496Sdim switch (Opts.getStructReturnConvention()) { 4381363496Sdim case CodeGenOptions::SRCK_Default: 4382363496Sdim break; 4383363496Sdim case CodeGenOptions::SRCK_OnStack: // -maix-struct-return 4384363496Sdim return false; 4385363496Sdim case CodeGenOptions::SRCK_InRegs: // -msvr4-struct-return 4386363496Sdim return true; 4387363496Sdim } 4388363496Sdim 4389363496Sdim if (Triple.isOSBinFormatELF() && !Triple.isOSLinux()) 4390363496Sdim return true; 4391363496Sdim 4392363496Sdim return false; 4393363496Sdim} 4394363496Sdim 4395205219Srdivackybool 4396205219SrdivackyPPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 4397205219Srdivacky llvm::Value *Address) const { 4398205219Srdivacky // This is calculated from the LLVM and GCC tables and verified 4399205219Srdivacky // against gcc output. AFAIK all ABIs use the same encoding. 4400205219Srdivacky 4401205219Srdivacky CodeGen::CGBuilderTy &Builder = CGF.Builder; 4402205219Srdivacky 4403234353Sdim llvm::IntegerType *i8 = CGF.Int8Ty; 4404205219Srdivacky llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4); 4405205219Srdivacky llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8); 4406205219Srdivacky llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16); 4407205219Srdivacky 4408205219Srdivacky // 0-31: r0-31, the 4-byte general-purpose registers 4409208600Srdivacky AssignToArrayRange(Builder, Address, Four8, 0, 31); 4410205219Srdivacky 4411205219Srdivacky // 32-63: fp0-31, the 8-byte floating-point registers 4412208600Srdivacky AssignToArrayRange(Builder, Address, Eight8, 32, 63); 4413205219Srdivacky 4414205219Srdivacky // 64-76 are various 4-byte special-purpose registers: 4415205219Srdivacky // 64: mq 4416205219Srdivacky // 65: lr 4417205219Srdivacky // 66: ctr 4418205219Srdivacky // 67: ap 4419205219Srdivacky // 68-75 cr0-7 4420205219Srdivacky // 76: xer 4421208600Srdivacky AssignToArrayRange(Builder, Address, Four8, 64, 76); 4422205219Srdivacky 4423205219Srdivacky // 77-108: v0-31, the 16-byte vector registers 4424208600Srdivacky AssignToArrayRange(Builder, Address, Sixteen8, 77, 108); 4425205219Srdivacky 4426205219Srdivacky // 109: vrsave 4427205219Srdivacky // 110: vscr 4428205219Srdivacky // 111: spe_acc 4429205219Srdivacky // 112: spefscr 4430205219Srdivacky // 113: sfp 4431208600Srdivacky AssignToArrayRange(Builder, Address, Four8, 109, 113); 4432205219Srdivacky 4433212904Sdim return false; 4434205219Srdivacky} 4435205219Srdivacky 4436239462Sdim// PowerPC-64 4437205219Srdivacky 4438239462Sdimnamespace { 4439243830Sdim/// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information. 4440341825Sdimclass PPC64_SVR4_ABIInfo : public SwiftABIInfo { 4441276479Sdimpublic: 4442276479Sdim enum ABIKind { 4443276479Sdim ELFv1 = 0, 4444276479Sdim ELFv2 4445276479Sdim }; 4446243830Sdim 4447276479Sdimprivate: 4448276479Sdim static const unsigned GPRBits = 64; 4449276479Sdim ABIKind Kind; 4450288943Sdim bool HasQPX; 4451309149Sdim bool IsSoftFloatABI; 4452276479Sdim 4453288943Sdim // A vector of float or double will be promoted to <4 x f32> or <4 x f64> and 4454288943Sdim // will be passed in a QPX register. 4455288943Sdim bool IsQPXVectorTy(const Type *Ty) const { 4456288943Sdim if (!HasQPX) 4457288943Sdim return false; 4458288943Sdim 4459288943Sdim if (const VectorType *VT = Ty->getAs<VectorType>()) { 4460288943Sdim unsigned NumElements = VT->getNumElements(); 4461288943Sdim if (NumElements == 1) 4462288943Sdim return false; 4463288943Sdim 4464288943Sdim if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) { 4465288943Sdim if (getContext().getTypeSize(Ty) <= 256) 4466288943Sdim return true; 4467288943Sdim } else if (VT->getElementType()-> 4468288943Sdim isSpecificBuiltinType(BuiltinType::Float)) { 4469288943Sdim if (getContext().getTypeSize(Ty) <= 128) 4470288943Sdim return true; 4471288943Sdim } 4472288943Sdim } 4473288943Sdim 4474288943Sdim return false; 4475288943Sdim } 4476288943Sdim 4477288943Sdim bool IsQPXVectorTy(QualType Ty) const { 4478288943Sdim return IsQPXVectorTy(Ty.getTypePtr()); 4479288943Sdim } 4480288943Sdim 4481243830Sdimpublic: 4482309149Sdim PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX, 4483309149Sdim bool SoftFloatABI) 4484341825Sdim : SwiftABIInfo(CGT), Kind(Kind), HasQPX(HasQPX), 4485309149Sdim IsSoftFloatABI(SoftFloatABI) {} 4486243830Sdim 4487243830Sdim bool isPromotableTypeForABI(QualType Ty) const; 4488296417Sdim CharUnits getParamTypeAlignment(QualType Ty) const; 4489243830Sdim 4490243830Sdim ABIArgInfo classifyReturnType(QualType RetTy) const; 4491243830Sdim ABIArgInfo classifyArgumentType(QualType Ty) const; 4492243830Sdim 4493280031Sdim bool isHomogeneousAggregateBaseType(QualType Ty) const override; 4494280031Sdim bool isHomogeneousAggregateSmallEnough(const Type *Ty, 4495280031Sdim uint64_t Members) const override; 4496280031Sdim 4497243830Sdim // TODO: We can add more logic to computeInfo to improve performance. 4498243830Sdim // Example: For aggregate arguments that fit in a register, we could 4499243830Sdim // use getDirectInReg (as is done below for structs containing a single 4500243830Sdim // floating-point value) to avoid pushing them to memory on function 4501243830Sdim // entry. This would require changing the logic in PPCISelLowering 4502243830Sdim // when lowering the parameters in the caller and args in the callee. 4503276479Sdim void computeInfo(CGFunctionInfo &FI) const override { 4504276479Sdim if (!getCXXABI().classifyReturnType(FI)) 4505276479Sdim FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 4506276479Sdim for (auto &I : FI.arguments()) { 4507243830Sdim // We rely on the default argument classification for the most part. 4508243830Sdim // One exception: An aggregate containing a single floating-point 4509261991Sdim // or vector item must be passed in a register if one is available. 4510276479Sdim const Type *T = isSingleElementStruct(I.type, getContext()); 4511243830Sdim if (T) { 4512243830Sdim const BuiltinType *BT = T->getAs<BuiltinType>(); 4513288943Sdim if (IsQPXVectorTy(T) || 4514288943Sdim (T->isVectorType() && getContext().getTypeSize(T) == 128) || 4515276479Sdim (BT && BT->isFloatingPoint())) { 4516243830Sdim QualType QT(T, 0); 4517276479Sdim I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT)); 4518243830Sdim continue; 4519243830Sdim } 4520243830Sdim } 4521276479Sdim I.info = classifyArgumentType(I.type); 4522243830Sdim } 4523243830Sdim } 4524243830Sdim 4525296417Sdim Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 4526296417Sdim QualType Ty) const override; 4527341825Sdim 4528341825Sdim bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars, 4529341825Sdim bool asReturnValue) const override { 4530341825Sdim return occupiesMoreThan(CGT, scalars, /*total*/ 4); 4531341825Sdim } 4532341825Sdim 4533341825Sdim bool isSwiftErrorInRegister() const override { 4534341825Sdim return false; 4535341825Sdim } 4536243830Sdim}; 4537243830Sdim 4538243830Sdimclass PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo { 4539288943Sdim 4540243830Sdimpublic: 4541276479Sdim PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT, 4542309149Sdim PPC64_SVR4_ABIInfo::ABIKind Kind, bool HasQPX, 4543309149Sdim bool SoftFloatABI) 4544309149Sdim : TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT, Kind, HasQPX, 4545309149Sdim SoftFloatABI)) {} 4546243830Sdim 4547276479Sdim int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override { 4548243830Sdim // This is recovered from gcc output. 4549243830Sdim return 1; // r1 is the dedicated stack pointer 4550243830Sdim } 4551243830Sdim 4552243830Sdim bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 4553276479Sdim llvm::Value *Address) const override; 4554243830Sdim}; 4555243830Sdim 4556239462Sdimclass PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo { 4557239462Sdimpublic: 4558239462Sdim PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {} 4559239462Sdim 4560276479Sdim int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override { 4561239462Sdim // This is recovered from gcc output. 4562239462Sdim return 1; // r1 is the dedicated stack pointer 4563239462Sdim } 4564239462Sdim 4565239462Sdim bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 4566276479Sdim llvm::Value *Address) const override; 4567239462Sdim}; 4568239462Sdim 4569239462Sdim} 4570239462Sdim 4571243830Sdim// Return true if the ABI requires Ty to be passed sign- or zero- 4572243830Sdim// extended to 64 bits. 4573239462Sdimbool 4574243830SdimPPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const { 4575243830Sdim // Treat an enum type as its underlying type. 4576243830Sdim if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 4577243830Sdim Ty = EnumTy->getDecl()->getIntegerType(); 4578243830Sdim 4579243830Sdim // Promotable integer types are required to be promoted by the ABI. 4580243830Sdim if (Ty->isPromotableIntegerType()) 4581243830Sdim return true; 4582243830Sdim 4583243830Sdim // In addition to the usual promotable integer types, we also need to 4584243830Sdim // extend all 32-bit types, since the ABI requires promotion to 64 bits. 4585243830Sdim if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) 4586243830Sdim switch (BT->getKind()) { 4587243830Sdim case BuiltinType::Int: 4588243830Sdim case BuiltinType::UInt: 4589243830Sdim return true; 4590243830Sdim default: 4591243830Sdim break; 4592243830Sdim } 4593243830Sdim 4594243830Sdim return false; 4595243830Sdim} 4596243830Sdim 4597296417Sdim/// isAlignedParamType - Determine whether a type requires 16-byte or 4598296417Sdim/// higher alignment in the parameter area. Always returns at least 8. 4599296417SdimCharUnits PPC64_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const { 4600276479Sdim // Complex types are passed just like their elements. 4601276479Sdim if (const ComplexType *CTy = Ty->getAs<ComplexType>()) 4602276479Sdim Ty = CTy->getElementType(); 4603276479Sdim 4604276479Sdim // Only vector types of size 16 bytes need alignment (larger types are 4605276479Sdim // passed via reference, smaller types are not aligned). 4606288943Sdim if (IsQPXVectorTy(Ty)) { 4607288943Sdim if (getContext().getTypeSize(Ty) > 128) 4608296417Sdim return CharUnits::fromQuantity(32); 4609288943Sdim 4610296417Sdim return CharUnits::fromQuantity(16); 4611288943Sdim } else if (Ty->isVectorType()) { 4612296417Sdim return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8); 4613288943Sdim } 4614276479Sdim 4615276479Sdim // For single-element float/vector structs, we consider the whole type 4616276479Sdim // to have the same alignment requirements as its single element. 4617276479Sdim const Type *AlignAsType = nullptr; 4618276479Sdim const Type *EltType = isSingleElementStruct(Ty, getContext()); 4619276479Sdim if (EltType) { 4620276479Sdim const BuiltinType *BT = EltType->getAs<BuiltinType>(); 4621288943Sdim if (IsQPXVectorTy(EltType) || (EltType->isVectorType() && 4622276479Sdim getContext().getTypeSize(EltType) == 128) || 4623276479Sdim (BT && BT->isFloatingPoint())) 4624276479Sdim AlignAsType = EltType; 4625276479Sdim } 4626276479Sdim 4627276479Sdim // Likewise for ELFv2 homogeneous aggregates. 4628276479Sdim const Type *Base = nullptr; 4629276479Sdim uint64_t Members = 0; 4630276479Sdim if (!AlignAsType && Kind == ELFv2 && 4631276479Sdim isAggregateTypeForABI(Ty) && isHomogeneousAggregate(Ty, Base, Members)) 4632276479Sdim AlignAsType = Base; 4633276479Sdim 4634276479Sdim // With special case aggregates, only vector base types need alignment. 4635288943Sdim if (AlignAsType && IsQPXVectorTy(AlignAsType)) { 4636288943Sdim if (getContext().getTypeSize(AlignAsType) > 128) 4637296417Sdim return CharUnits::fromQuantity(32); 4638288943Sdim 4639296417Sdim return CharUnits::fromQuantity(16); 4640288943Sdim } else if (AlignAsType) { 4641296417Sdim return CharUnits::fromQuantity(AlignAsType->isVectorType() ? 16 : 8); 4642288943Sdim } 4643276479Sdim 4644276479Sdim // Otherwise, we only need alignment for any aggregate type that 4645276479Sdim // has an alignment requirement of >= 16 bytes. 4646288943Sdim if (isAggregateTypeForABI(Ty) && getContext().getTypeAlign(Ty) >= 128) { 4647288943Sdim if (HasQPX && getContext().getTypeAlign(Ty) >= 256) 4648296417Sdim return CharUnits::fromQuantity(32); 4649296417Sdim return CharUnits::fromQuantity(16); 4650288943Sdim } 4651276479Sdim 4652296417Sdim return CharUnits::fromQuantity(8); 4653276479Sdim} 4654276479Sdim 4655276479Sdim/// isHomogeneousAggregate - Return true if a type is an ELFv2 homogeneous 4656276479Sdim/// aggregate. Base is set to the base element type, and Members is set 4657276479Sdim/// to the number of base elements. 4658280031Sdimbool ABIInfo::isHomogeneousAggregate(QualType Ty, const Type *&Base, 4659280031Sdim uint64_t &Members) const { 4660276479Sdim if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) { 4661276479Sdim uint64_t NElements = AT->getSize().getZExtValue(); 4662276479Sdim if (NElements == 0) 4663276479Sdim return false; 4664276479Sdim if (!isHomogeneousAggregate(AT->getElementType(), Base, Members)) 4665276479Sdim return false; 4666276479Sdim Members *= NElements; 4667276479Sdim } else if (const RecordType *RT = Ty->getAs<RecordType>()) { 4668276479Sdim const RecordDecl *RD = RT->getDecl(); 4669276479Sdim if (RD->hasFlexibleArrayMember()) 4670276479Sdim return false; 4671276479Sdim 4672276479Sdim Members = 0; 4673280031Sdim 4674280031Sdim // If this is a C++ record, check the bases first. 4675280031Sdim if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) { 4676280031Sdim for (const auto &I : CXXRD->bases()) { 4677280031Sdim // Ignore empty records. 4678280031Sdim if (isEmptyRecord(getContext(), I.getType(), true)) 4679280031Sdim continue; 4680280031Sdim 4681280031Sdim uint64_t FldMembers; 4682280031Sdim if (!isHomogeneousAggregate(I.getType(), Base, FldMembers)) 4683280031Sdim return false; 4684280031Sdim 4685280031Sdim Members += FldMembers; 4686280031Sdim } 4687280031Sdim } 4688280031Sdim 4689276479Sdim for (const auto *FD : RD->fields()) { 4690276479Sdim // Ignore (non-zero arrays of) empty records. 4691276479Sdim QualType FT = FD->getType(); 4692276479Sdim while (const ConstantArrayType *AT = 4693276479Sdim getContext().getAsConstantArrayType(FT)) { 4694276479Sdim if (AT->getSize().getZExtValue() == 0) 4695276479Sdim return false; 4696276479Sdim FT = AT->getElementType(); 4697276479Sdim } 4698276479Sdim if (isEmptyRecord(getContext(), FT, true)) 4699276479Sdim continue; 4700276479Sdim 4701276479Sdim // For compatibility with GCC, ignore empty bitfields in C++ mode. 4702276479Sdim if (getContext().getLangOpts().CPlusPlus && 4703341825Sdim FD->isZeroLengthBitField(getContext())) 4704276479Sdim continue; 4705276479Sdim 4706276479Sdim uint64_t FldMembers; 4707276479Sdim if (!isHomogeneousAggregate(FD->getType(), Base, FldMembers)) 4708276479Sdim return false; 4709276479Sdim 4710276479Sdim Members = (RD->isUnion() ? 4711276479Sdim std::max(Members, FldMembers) : Members + FldMembers); 4712276479Sdim } 4713276479Sdim 4714276479Sdim if (!Base) 4715276479Sdim return false; 4716276479Sdim 4717276479Sdim // Ensure there is no padding. 4718276479Sdim if (getContext().getTypeSize(Base) * Members != 4719276479Sdim getContext().getTypeSize(Ty)) 4720276479Sdim return false; 4721276479Sdim } else { 4722276479Sdim Members = 1; 4723276479Sdim if (const ComplexType *CT = Ty->getAs<ComplexType>()) { 4724276479Sdim Members = 2; 4725276479Sdim Ty = CT->getElementType(); 4726276479Sdim } 4727276479Sdim 4728280031Sdim // Most ABIs only support float, double, and some vector type widths. 4729280031Sdim if (!isHomogeneousAggregateBaseType(Ty)) 4730276479Sdim return false; 4731276479Sdim 4732276479Sdim // The base type must be the same for all members. Types that 4733276479Sdim // agree in both total size and mode (float vs. vector) are 4734276479Sdim // treated as being equivalent here. 4735276479Sdim const Type *TyPtr = Ty.getTypePtr(); 4736309124Sdim if (!Base) { 4737276479Sdim Base = TyPtr; 4738309124Sdim // If it's a non-power-of-2 vector, its size is already a power-of-2, 4739309124Sdim // so make sure to widen it explicitly. 4740309124Sdim if (const VectorType *VT = Base->getAs<VectorType>()) { 4741309124Sdim QualType EltTy = VT->getElementType(); 4742309124Sdim unsigned NumElements = 4743309124Sdim getContext().getTypeSize(VT) / getContext().getTypeSize(EltTy); 4744309124Sdim Base = getContext() 4745309124Sdim .getVectorType(EltTy, NumElements, VT->getVectorKind()) 4746309124Sdim .getTypePtr(); 4747309124Sdim } 4748309124Sdim } 4749276479Sdim 4750276479Sdim if (Base->isVectorType() != TyPtr->isVectorType() || 4751276479Sdim getContext().getTypeSize(Base) != getContext().getTypeSize(TyPtr)) 4752276479Sdim return false; 4753276479Sdim } 4754280031Sdim return Members > 0 && isHomogeneousAggregateSmallEnough(Base, Members); 4755280031Sdim} 4756276479Sdim 4757280031Sdimbool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const { 4758280031Sdim // Homogeneous aggregates for ELFv2 must have base types of float, 4759280031Sdim // double, long double, or 128-bit vectors. 4760280031Sdim if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) { 4761280031Sdim if (BT->getKind() == BuiltinType::Float || 4762280031Sdim BT->getKind() == BuiltinType::Double || 4763341825Sdim BT->getKind() == BuiltinType::LongDouble || 4764341825Sdim (getContext().getTargetInfo().hasFloat128Type() && 4765341825Sdim (BT->getKind() == BuiltinType::Float128))) { 4766309149Sdim if (IsSoftFloatABI) 4767309149Sdim return false; 4768280031Sdim return true; 4769309149Sdim } 4770280031Sdim } 4771280031Sdim if (const VectorType *VT = Ty->getAs<VectorType>()) { 4772288943Sdim if (getContext().getTypeSize(VT) == 128 || IsQPXVectorTy(Ty)) 4773280031Sdim return true; 4774280031Sdim } 4775280031Sdim return false; 4776280031Sdim} 4777280031Sdim 4778280031Sdimbool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough( 4779280031Sdim const Type *Base, uint64_t Members) const { 4780341825Sdim // Vector and fp128 types require one register, other floating point types 4781341825Sdim // require one or two registers depending on their size. 4782280031Sdim uint32_t NumRegs = 4783341825Sdim ((getContext().getTargetInfo().hasFloat128Type() && 4784341825Sdim Base->isFloat128Type()) || 4785341825Sdim Base->isVectorType()) ? 1 4786341825Sdim : (getContext().getTypeSize(Base) + 63) / 64; 4787276479Sdim 4788276479Sdim // Homogeneous Aggregates may occupy at most 8 registers. 4789280031Sdim return Members * NumRegs <= 8; 4790276479Sdim} 4791276479Sdim 4792243830SdimABIArgInfo 4793243830SdimPPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const { 4794280031Sdim Ty = useFirstFieldIfTransparentUnion(Ty); 4795280031Sdim 4796249423Sdim if (Ty->isAnyComplexType()) 4797249423Sdim return ABIArgInfo::getDirect(); 4798249423Sdim 4799276479Sdim // Non-Altivec vector types are passed in GPRs (smaller than 16 bytes) 4800276479Sdim // or via reference (larger than 16 bytes). 4801288943Sdim if (Ty->isVectorType() && !IsQPXVectorTy(Ty)) { 4802276479Sdim uint64_t Size = getContext().getTypeSize(Ty); 4803276479Sdim if (Size > 128) 4804296417Sdim return getNaturalAlignIndirect(Ty, /*ByVal=*/false); 4805276479Sdim else if (Size < 128) { 4806276479Sdim llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size); 4807276479Sdim return ABIArgInfo::getDirect(CoerceTy); 4808276479Sdim } 4809276479Sdim } 4810276479Sdim 4811243830Sdim if (isAggregateTypeForABI(Ty)) { 4812261991Sdim if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) 4813296417Sdim return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory); 4814243830Sdim 4815296417Sdim uint64_t ABIAlign = getParamTypeAlignment(Ty).getQuantity(); 4816296417Sdim uint64_t TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity(); 4817276479Sdim 4818276479Sdim // ELFv2 homogeneous aggregates are passed as array types. 4819276479Sdim const Type *Base = nullptr; 4820276479Sdim uint64_t Members = 0; 4821276479Sdim if (Kind == ELFv2 && 4822276479Sdim isHomogeneousAggregate(Ty, Base, Members)) { 4823276479Sdim llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0)); 4824276479Sdim llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members); 4825276479Sdim return ABIArgInfo::getDirect(CoerceTy); 4826276479Sdim } 4827276479Sdim 4828276479Sdim // If an aggregate may end up fully in registers, we do not 4829276479Sdim // use the ByVal method, but pass the aggregate as array. 4830276479Sdim // This is usually beneficial since we avoid forcing the 4831276479Sdim // back-end to store the argument to memory. 4832276479Sdim uint64_t Bits = getContext().getTypeSize(Ty); 4833276479Sdim if (Bits > 0 && Bits <= 8 * GPRBits) { 4834276479Sdim llvm::Type *CoerceTy; 4835276479Sdim 4836276479Sdim // Types up to 8 bytes are passed as integer type (which will be 4837276479Sdim // properly aligned in the argument save area doubleword). 4838276479Sdim if (Bits <= GPRBits) 4839309124Sdim CoerceTy = 4840309124Sdim llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8)); 4841276479Sdim // Larger types are passed as arrays, with the base type selected 4842276479Sdim // according to the required alignment in the save area. 4843276479Sdim else { 4844276479Sdim uint64_t RegBits = ABIAlign * 8; 4845309124Sdim uint64_t NumRegs = llvm::alignTo(Bits, RegBits) / RegBits; 4846276479Sdim llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits); 4847276479Sdim CoerceTy = llvm::ArrayType::get(RegTy, NumRegs); 4848276479Sdim } 4849276479Sdim 4850276479Sdim return ABIArgInfo::getDirect(CoerceTy); 4851276479Sdim } 4852276479Sdim 4853276479Sdim // All other aggregates are passed ByVal. 4854296417Sdim return ABIArgInfo::getIndirect(CharUnits::fromQuantity(ABIAlign), 4855296417Sdim /*ByVal=*/true, 4856276479Sdim /*Realign=*/TyAlign > ABIAlign); 4857243830Sdim } 4858243830Sdim 4859341825Sdim return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty) 4860341825Sdim : ABIArgInfo::getDirect()); 4861243830Sdim} 4862243830Sdim 4863243830SdimABIArgInfo 4864243830SdimPPC64_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const { 4865243830Sdim if (RetTy->isVoidType()) 4866243830Sdim return ABIArgInfo::getIgnore(); 4867243830Sdim 4868249423Sdim if (RetTy->isAnyComplexType()) 4869249423Sdim return ABIArgInfo::getDirect(); 4870249423Sdim 4871276479Sdim // Non-Altivec vector types are returned in GPRs (smaller than 16 bytes) 4872276479Sdim // or via reference (larger than 16 bytes). 4873288943Sdim if (RetTy->isVectorType() && !IsQPXVectorTy(RetTy)) { 4874276479Sdim uint64_t Size = getContext().getTypeSize(RetTy); 4875276479Sdim if (Size > 128) 4876296417Sdim return getNaturalAlignIndirect(RetTy); 4877276479Sdim else if (Size < 128) { 4878276479Sdim llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size); 4879276479Sdim return ABIArgInfo::getDirect(CoerceTy); 4880276479Sdim } 4881276479Sdim } 4882276479Sdim 4883276479Sdim if (isAggregateTypeForABI(RetTy)) { 4884276479Sdim // ELFv2 homogeneous aggregates are returned as array types. 4885276479Sdim const Type *Base = nullptr; 4886276479Sdim uint64_t Members = 0; 4887276479Sdim if (Kind == ELFv2 && 4888276479Sdim isHomogeneousAggregate(RetTy, Base, Members)) { 4889276479Sdim llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0)); 4890276479Sdim llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members); 4891276479Sdim return ABIArgInfo::getDirect(CoerceTy); 4892276479Sdim } 4893276479Sdim 4894276479Sdim // ELFv2 small aggregates are returned in up to two registers. 4895276479Sdim uint64_t Bits = getContext().getTypeSize(RetTy); 4896276479Sdim if (Kind == ELFv2 && Bits <= 2 * GPRBits) { 4897276479Sdim if (Bits == 0) 4898276479Sdim return ABIArgInfo::getIgnore(); 4899276479Sdim 4900276479Sdim llvm::Type *CoerceTy; 4901276479Sdim if (Bits > GPRBits) { 4902276479Sdim CoerceTy = llvm::IntegerType::get(getVMContext(), GPRBits); 4903321369Sdim CoerceTy = llvm::StructType::get(CoerceTy, CoerceTy); 4904276479Sdim } else 4905309124Sdim CoerceTy = 4906309124Sdim llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8)); 4907276479Sdim return ABIArgInfo::getDirect(CoerceTy); 4908276479Sdim } 4909276479Sdim 4910276479Sdim // All other aggregates are returned indirectly. 4911296417Sdim return getNaturalAlignIndirect(RetTy); 4912276479Sdim } 4913243830Sdim 4914341825Sdim return (isPromotableTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy) 4915341825Sdim : ABIArgInfo::getDirect()); 4916243830Sdim} 4917243830Sdim 4918243830Sdim// Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine. 4919296417SdimAddress PPC64_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 4920296417Sdim QualType Ty) const { 4921296417Sdim auto TypeInfo = getContext().getTypeInfoInChars(Ty); 4922296417Sdim TypeInfo.second = getParamTypeAlignment(Ty); 4923243830Sdim 4924296417Sdim CharUnits SlotSize = CharUnits::fromQuantity(8); 4925243830Sdim 4926249423Sdim // If we have a complex type and the base type is smaller than 8 bytes, 4927249423Sdim // the ABI calls for the real and imaginary parts to be right-adjusted 4928249423Sdim // in separate doublewords. However, Clang expects us to produce a 4929249423Sdim // pointer to a structure with the two parts packed tightly. So generate 4930249423Sdim // loads of the real and imaginary parts relative to the va_list pointer, 4931249423Sdim // and store them to a temporary structure. 4932296417Sdim if (const ComplexType *CTy = Ty->getAs<ComplexType>()) { 4933296417Sdim CharUnits EltSize = TypeInfo.first / 2; 4934296417Sdim if (EltSize < SlotSize) { 4935296417Sdim Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, CGF.Int8Ty, 4936296417Sdim SlotSize * 2, SlotSize, 4937296417Sdim SlotSize, /*AllowHigher*/ true); 4938296417Sdim 4939296417Sdim Address RealAddr = Addr; 4940296417Sdim Address ImagAddr = RealAddr; 4941296417Sdim if (CGF.CGM.getDataLayout().isBigEndian()) { 4942296417Sdim RealAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, 4943296417Sdim SlotSize - EltSize); 4944296417Sdim ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(ImagAddr, 4945296417Sdim 2 * SlotSize - EltSize); 4946296417Sdim } else { 4947296417Sdim ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize); 4948296417Sdim } 4949296417Sdim 4950296417Sdim llvm::Type *EltTy = CGF.ConvertTypeForMem(CTy->getElementType()); 4951296417Sdim RealAddr = CGF.Builder.CreateElementBitCast(RealAddr, EltTy); 4952296417Sdim ImagAddr = CGF.Builder.CreateElementBitCast(ImagAddr, EltTy); 4953296417Sdim llvm::Value *Real = CGF.Builder.CreateLoad(RealAddr, ".vareal"); 4954296417Sdim llvm::Value *Imag = CGF.Builder.CreateLoad(ImagAddr, ".vaimag"); 4955296417Sdim 4956296417Sdim Address Temp = CGF.CreateMemTemp(Ty, "vacplx"); 4957296417Sdim CGF.EmitStoreOfComplex({Real, Imag}, CGF.MakeAddrLValue(Temp, Ty), 4958296417Sdim /*init*/ true); 4959296417Sdim return Temp; 4960276479Sdim } 4961249423Sdim } 4962249423Sdim 4963296417Sdim // Otherwise, just use the general rule. 4964296417Sdim return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false, 4965296417Sdim TypeInfo, SlotSize, /*AllowHigher*/ true); 4966243830Sdim} 4967243830Sdim 4968243830Sdimstatic bool 4969243830SdimPPC64_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 4970243830Sdim llvm::Value *Address) { 4971239462Sdim // This is calculated from the LLVM and GCC tables and verified 4972239462Sdim // against gcc output. AFAIK all ABIs use the same encoding. 4973239462Sdim 4974239462Sdim CodeGen::CGBuilderTy &Builder = CGF.Builder; 4975239462Sdim 4976239462Sdim llvm::IntegerType *i8 = CGF.Int8Ty; 4977239462Sdim llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4); 4978239462Sdim llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8); 4979239462Sdim llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16); 4980239462Sdim 4981239462Sdim // 0-31: r0-31, the 8-byte general-purpose registers 4982239462Sdim AssignToArrayRange(Builder, Address, Eight8, 0, 31); 4983239462Sdim 4984239462Sdim // 32-63: fp0-31, the 8-byte floating-point registers 4985239462Sdim AssignToArrayRange(Builder, Address, Eight8, 32, 63); 4986239462Sdim 4987314564Sdim // 64-67 are various 8-byte special-purpose registers: 4988239462Sdim // 64: mq 4989239462Sdim // 65: lr 4990239462Sdim // 66: ctr 4991239462Sdim // 67: ap 4992314564Sdim AssignToArrayRange(Builder, Address, Eight8, 64, 67); 4993314564Sdim 4994314564Sdim // 68-76 are various 4-byte special-purpose registers: 4995239462Sdim // 68-75 cr0-7 4996239462Sdim // 76: xer 4997314564Sdim AssignToArrayRange(Builder, Address, Four8, 68, 76); 4998239462Sdim 4999239462Sdim // 77-108: v0-31, the 16-byte vector registers 5000239462Sdim AssignToArrayRange(Builder, Address, Sixteen8, 77, 108); 5001239462Sdim 5002239462Sdim // 109: vrsave 5003239462Sdim // 110: vscr 5004239462Sdim // 111: spe_acc 5005239462Sdim // 112: spefscr 5006239462Sdim // 113: sfp 5007314564Sdim // 114: tfhar 5008314564Sdim // 115: tfiar 5009314564Sdim // 116: texasr 5010314564Sdim AssignToArrayRange(Builder, Address, Eight8, 109, 116); 5011239462Sdim 5012239462Sdim return false; 5013239462Sdim} 5014239462Sdim 5015243830Sdimbool 5016243830SdimPPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable( 5017243830Sdim CodeGen::CodeGenFunction &CGF, 5018243830Sdim llvm::Value *Address) const { 5019243830Sdim 5020243830Sdim return PPC64_initDwarfEHRegSizeTable(CGF, Address); 5021243830Sdim} 5022243830Sdim 5023243830Sdimbool 5024243830SdimPPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 5025243830Sdim llvm::Value *Address) const { 5026243830Sdim 5027243830Sdim return PPC64_initDwarfEHRegSizeTable(CGF, Address); 5028243830Sdim} 5029243830Sdim 5030210299Sed//===----------------------------------------------------------------------===// 5031276479Sdim// AArch64 ABI Implementation 5032276479Sdim//===----------------------------------------------------------------------===// 5033276479Sdim 5034276479Sdimnamespace { 5035276479Sdim 5036309124Sdimclass AArch64ABIInfo : public SwiftABIInfo { 5037276479Sdimpublic: 5038276479Sdim enum ABIKind { 5039276479Sdim AAPCS = 0, 5040321369Sdim DarwinPCS, 5041321369Sdim Win64 5042276479Sdim }; 5043276479Sdim 5044276479Sdimprivate: 5045276479Sdim ABIKind Kind; 5046276479Sdim 5047276479Sdimpublic: 5048309124Sdim AArch64ABIInfo(CodeGenTypes &CGT, ABIKind Kind) 5049309124Sdim : SwiftABIInfo(CGT), Kind(Kind) {} 5050276479Sdim 5051276479Sdimprivate: 5052276479Sdim ABIKind getABIKind() const { return Kind; } 5053276479Sdim bool isDarwinPCS() const { return Kind == DarwinPCS; } 5054276479Sdim 5055360784Sdim ABIArgInfo classifyReturnType(QualType RetTy, bool IsVariadic) const; 5056280031Sdim ABIArgInfo classifyArgumentType(QualType RetTy) const; 5057280031Sdim bool isHomogeneousAggregateBaseType(QualType Ty) const override; 5058280031Sdim bool isHomogeneousAggregateSmallEnough(const Type *Ty, 5059280031Sdim uint64_t Members) const override; 5060280031Sdim 5061276479Sdim bool isIllegalVectorType(QualType Ty) const; 5062276479Sdim 5063280031Sdim void computeInfo(CGFunctionInfo &FI) const override { 5064341825Sdim if (!::classifyReturnType(getCXXABI(), FI, *this)) 5065360784Sdim FI.getReturnInfo() = 5066360784Sdim classifyReturnType(FI.getReturnType(), FI.isVariadic()); 5067276479Sdim 5068280031Sdim for (auto &it : FI.arguments()) 5069280031Sdim it.info = classifyArgumentType(it.type); 5070276479Sdim } 5071276479Sdim 5072296417Sdim Address EmitDarwinVAArg(Address VAListAddr, QualType Ty, 5073296417Sdim CodeGenFunction &CGF) const; 5074276479Sdim 5075296417Sdim Address EmitAAPCSVAArg(Address VAListAddr, QualType Ty, 5076296417Sdim CodeGenFunction &CGF) const; 5077276479Sdim 5078296417Sdim Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 5079296417Sdim QualType Ty) const override { 5080321369Sdim return Kind == Win64 ? EmitMSVAArg(CGF, VAListAddr, Ty) 5081321369Sdim : isDarwinPCS() ? EmitDarwinVAArg(VAListAddr, Ty, CGF) 5082321369Sdim : EmitAAPCSVAArg(VAListAddr, Ty, CGF); 5083276479Sdim } 5084309124Sdim 5085321369Sdim Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr, 5086321369Sdim QualType Ty) const override; 5087321369Sdim 5088341825Sdim bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars, 5089309124Sdim bool asReturnValue) const override { 5090309124Sdim return occupiesMoreThan(CGT, scalars, /*total*/ 4); 5091309124Sdim } 5092314564Sdim bool isSwiftErrorInRegister() const override { 5093314564Sdim return true; 5094314564Sdim } 5095321369Sdim 5096321369Sdim bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy, 5097321369Sdim unsigned elts) const override; 5098276479Sdim}; 5099276479Sdim 5100276479Sdimclass AArch64TargetCodeGenInfo : public TargetCodeGenInfo { 5101276479Sdimpublic: 5102276479Sdim AArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind Kind) 5103276479Sdim : TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {} 5104276479Sdim 5105288943Sdim StringRef getARCRetainAutoreleasedReturnValueMarker() const override { 5106327952Sdim return "mov\tfp, fp\t\t// marker for objc_retainAutoreleaseReturnValue"; 5107276479Sdim } 5108276479Sdim 5109288943Sdim int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override { 5110288943Sdim return 31; 5111288943Sdim } 5112276479Sdim 5113288943Sdim bool doesReturnSlotInterfereWithArgs() const override { return false; } 5114344779Sdim 5115344779Sdim void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 5116344779Sdim CodeGen::CodeGenModule &CGM) const override { 5117344779Sdim const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D); 5118344779Sdim if (!FD) 5119344779Sdim return; 5120344779Sdim 5121360784Sdim CodeGenOptions::SignReturnAddressScope Scope = CGM.getCodeGenOpts().getSignReturnAddress(); 5122360784Sdim CodeGenOptions::SignReturnAddressKeyValue Key = CGM.getCodeGenOpts().getSignReturnAddressKey(); 5123360784Sdim bool BranchTargetEnforcement = CGM.getCodeGenOpts().BranchTargetEnforcement; 5124360784Sdim if (const auto *TA = FD->getAttr<TargetAttr>()) { 5125360784Sdim ParsedTargetAttr Attr = TA->parse(); 5126360784Sdim if (!Attr.BranchProtection.empty()) { 5127360784Sdim TargetInfo::BranchProtectionInfo BPI; 5128360784Sdim StringRef Error; 5129360784Sdim (void)CGM.getTarget().validateBranchProtection(Attr.BranchProtection, 5130360784Sdim BPI, Error); 5131360784Sdim assert(Error.empty()); 5132360784Sdim Scope = BPI.SignReturnAddr; 5133360784Sdim Key = BPI.SignKey; 5134360784Sdim BranchTargetEnforcement = BPI.BranchTargetEnforcement; 5135360784Sdim } 5136360784Sdim } 5137360784Sdim 5138360784Sdim auto *Fn = cast<llvm::Function>(GV); 5139360784Sdim if (Scope != CodeGenOptions::SignReturnAddressScope::None) { 5140344779Sdim Fn->addFnAttr("sign-return-address", 5141360784Sdim Scope == CodeGenOptions::SignReturnAddressScope::All 5142344779Sdim ? "all" 5143344779Sdim : "non-leaf"); 5144344779Sdim 5145344779Sdim Fn->addFnAttr("sign-return-address-key", 5146344779Sdim Key == CodeGenOptions::SignReturnAddressKeyValue::AKey 5147344779Sdim ? "a_key" 5148344779Sdim : "b_key"); 5149344779Sdim } 5150344779Sdim 5151360784Sdim if (BranchTargetEnforcement) 5152344779Sdim Fn->addFnAttr("branch-target-enforcement"); 5153344779Sdim } 5154276479Sdim}; 5155327952Sdim 5156327952Sdimclass WindowsAArch64TargetCodeGenInfo : public AArch64TargetCodeGenInfo { 5157327952Sdimpublic: 5158327952Sdim WindowsAArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind K) 5159327952Sdim : AArch64TargetCodeGenInfo(CGT, K) {} 5160327952Sdim 5161344779Sdim void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 5162344779Sdim CodeGen::CodeGenModule &CGM) const override; 5163344779Sdim 5164327952Sdim void getDependentLibraryOption(llvm::StringRef Lib, 5165327952Sdim llvm::SmallString<24> &Opt) const override { 5166327952Sdim Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib); 5167327952Sdim } 5168327952Sdim 5169327952Sdim void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value, 5170327952Sdim llvm::SmallString<32> &Opt) const override { 5171327952Sdim Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\""; 5172327952Sdim } 5173327952Sdim}; 5174344779Sdim 5175344779Sdimvoid WindowsAArch64TargetCodeGenInfo::setTargetAttributes( 5176344779Sdim const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const { 5177344779Sdim AArch64TargetCodeGenInfo::setTargetAttributes(D, GV, CGM); 5178344779Sdim if (GV->isDeclaration()) 5179344779Sdim return; 5180344779Sdim addStackProbeTargetAttributes(D, GV, CGM); 5181276479Sdim} 5182344779Sdim} 5183276479Sdim 5184280031SdimABIArgInfo AArch64ABIInfo::classifyArgumentType(QualType Ty) const { 5185280031Sdim Ty = useFirstFieldIfTransparentUnion(Ty); 5186276479Sdim 5187276479Sdim // Handle illegal vector types here. 5188276479Sdim if (isIllegalVectorType(Ty)) { 5189276479Sdim uint64_t Size = getContext().getTypeSize(Ty); 5190309124Sdim // Android promotes <2 x i8> to i16, not i32 5191309124Sdim if (isAndroid() && (Size <= 16)) { 5192309124Sdim llvm::Type *ResType = llvm::Type::getInt16Ty(getVMContext()); 5193309124Sdim return ABIArgInfo::getDirect(ResType); 5194309124Sdim } 5195276479Sdim if (Size <= 32) { 5196276479Sdim llvm::Type *ResType = llvm::Type::getInt32Ty(getVMContext()); 5197276479Sdim return ABIArgInfo::getDirect(ResType); 5198276479Sdim } 5199276479Sdim if (Size == 64) { 5200276479Sdim llvm::Type *ResType = 5201276479Sdim llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 2); 5202276479Sdim return ABIArgInfo::getDirect(ResType); 5203276479Sdim } 5204276479Sdim if (Size == 128) { 5205276479Sdim llvm::Type *ResType = 5206276479Sdim llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 4); 5207276479Sdim return ABIArgInfo::getDirect(ResType); 5208276479Sdim } 5209296417Sdim return getNaturalAlignIndirect(Ty, /*ByVal=*/false); 5210276479Sdim } 5211276479Sdim 5212276479Sdim if (!isAggregateTypeForABI(Ty)) { 5213276479Sdim // Treat an enum type as its underlying type. 5214276479Sdim if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 5215276479Sdim Ty = EnumTy->getDecl()->getIntegerType(); 5216276479Sdim 5217276479Sdim return (Ty->isPromotableIntegerType() && isDarwinPCS() 5218341825Sdim ? ABIArgInfo::getExtend(Ty) 5219276479Sdim : ABIArgInfo::getDirect()); 5220276479Sdim } 5221276479Sdim 5222276479Sdim // Structures with either a non-trivial destructor or a non-trivial 5223276479Sdim // copy constructor are always indirect. 5224276479Sdim if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) { 5225296417Sdim return getNaturalAlignIndirect(Ty, /*ByVal=*/RAA == 5226296417Sdim CGCXXABI::RAA_DirectInMemory); 5227276479Sdim } 5228276479Sdim 5229276479Sdim // Empty records are always ignored on Darwin, but actually passed in C++ mode 5230276479Sdim // elsewhere for GNU compatibility. 5231321369Sdim uint64_t Size = getContext().getTypeSize(Ty); 5232321369Sdim bool IsEmpty = isEmptyRecord(getContext(), Ty, true); 5233321369Sdim if (IsEmpty || Size == 0) { 5234276479Sdim if (!getContext().getLangOpts().CPlusPlus || isDarwinPCS()) 5235276479Sdim return ABIArgInfo::getIgnore(); 5236276479Sdim 5237321369Sdim // GNU C mode. The only argument that gets ignored is an empty one with size 5238321369Sdim // 0. 5239321369Sdim if (IsEmpty && Size == 0) 5240321369Sdim return ABIArgInfo::getIgnore(); 5241276479Sdim return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); 5242276479Sdim } 5243276479Sdim 5244276479Sdim // Homogeneous Floating-point Aggregates (HFAs) need to be expanded. 5245276479Sdim const Type *Base = nullptr; 5246276479Sdim uint64_t Members = 0; 5247280031Sdim if (isHomogeneousAggregate(Ty, Base, Members)) { 5248280031Sdim return ABIArgInfo::getDirect( 5249280031Sdim llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members)); 5250276479Sdim } 5251276479Sdim 5252276479Sdim // Aggregates <= 16 bytes are passed directly in registers or on the stack. 5253276479Sdim if (Size <= 128) { 5254314564Sdim // On RenderScript, coerce Aggregates <= 16 bytes to an integer array of 5255314564Sdim // same size and alignment. 5256314564Sdim if (getTarget().isRenderScriptTarget()) { 5257314564Sdim return coerceToIntArray(Ty, getContext(), getVMContext()); 5258314564Sdim } 5259341825Sdim unsigned Alignment; 5260341825Sdim if (Kind == AArch64ABIInfo::AAPCS) { 5261341825Sdim Alignment = getContext().getTypeUnadjustedAlign(Ty); 5262341825Sdim Alignment = Alignment < 128 ? 64 : 128; 5263341825Sdim } else { 5264360784Sdim Alignment = std::max(getContext().getTypeAlign(Ty), 5265360784Sdim (unsigned)getTarget().getPointerWidth(0)); 5266341825Sdim } 5267360784Sdim Size = llvm::alignTo(Size, Alignment); 5268276479Sdim 5269276479Sdim // We use a pair of i64 for 16-byte aggregate with 8-byte alignment. 5270276479Sdim // For aggregates with 16-byte alignment, we use i128. 5271360784Sdim llvm::Type *BaseTy = llvm::Type::getIntNTy(getVMContext(), Alignment); 5272360784Sdim return ABIArgInfo::getDirect( 5273360784Sdim Size == Alignment ? BaseTy 5274360784Sdim : llvm::ArrayType::get(BaseTy, Size / Alignment)); 5275276479Sdim } 5276276479Sdim 5277296417Sdim return getNaturalAlignIndirect(Ty, /*ByVal=*/false); 5278276479Sdim} 5279276479Sdim 5280360784SdimABIArgInfo AArch64ABIInfo::classifyReturnType(QualType RetTy, 5281360784Sdim bool IsVariadic) const { 5282276479Sdim if (RetTy->isVoidType()) 5283276479Sdim return ABIArgInfo::getIgnore(); 5284276479Sdim 5285276479Sdim // Large vector types should be returned via memory. 5286276479Sdim if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128) 5287296417Sdim return getNaturalAlignIndirect(RetTy); 5288276479Sdim 5289276479Sdim if (!isAggregateTypeForABI(RetTy)) { 5290276479Sdim // Treat an enum type as its underlying type. 5291276479Sdim if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 5292276479Sdim RetTy = EnumTy->getDecl()->getIntegerType(); 5293276479Sdim 5294276479Sdim return (RetTy->isPromotableIntegerType() && isDarwinPCS() 5295341825Sdim ? ABIArgInfo::getExtend(RetTy) 5296276479Sdim : ABIArgInfo::getDirect()); 5297276479Sdim } 5298276479Sdim 5299321369Sdim uint64_t Size = getContext().getTypeSize(RetTy); 5300321369Sdim if (isEmptyRecord(getContext(), RetTy, true) || Size == 0) 5301276479Sdim return ABIArgInfo::getIgnore(); 5302276479Sdim 5303276479Sdim const Type *Base = nullptr; 5304280031Sdim uint64_t Members = 0; 5305360784Sdim if (isHomogeneousAggregate(RetTy, Base, Members) && 5306360784Sdim !(getTarget().getTriple().getArch() == llvm::Triple::aarch64_32 && 5307360784Sdim IsVariadic)) 5308276479Sdim // Homogeneous Floating-point Aggregates (HFAs) are returned directly. 5309276479Sdim return ABIArgInfo::getDirect(); 5310276479Sdim 5311276479Sdim // Aggregates <= 16 bytes are returned directly in registers or on the stack. 5312276479Sdim if (Size <= 128) { 5313314564Sdim // On RenderScript, coerce Aggregates <= 16 bytes to an integer array of 5314314564Sdim // same size and alignment. 5315314564Sdim if (getTarget().isRenderScriptTarget()) { 5316314564Sdim return coerceToIntArray(RetTy, getContext(), getVMContext()); 5317314564Sdim } 5318288943Sdim unsigned Alignment = getContext().getTypeAlign(RetTy); 5319321369Sdim Size = llvm::alignTo(Size, 64); // round up to multiple of 8 bytes 5320288943Sdim 5321288943Sdim // We use a pair of i64 for 16-byte aggregate with 8-byte alignment. 5322288943Sdim // For aggregates with 16-byte alignment, we use i128. 5323288943Sdim if (Alignment < 128 && Size == 128) { 5324288943Sdim llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext()); 5325288943Sdim return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64)); 5326288943Sdim } 5327276479Sdim return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size)); 5328276479Sdim } 5329276479Sdim 5330296417Sdim return getNaturalAlignIndirect(RetTy); 5331276479Sdim} 5332276479Sdim 5333276479Sdim/// isIllegalVectorType - check whether the vector type is legal for AArch64. 5334276479Sdimbool AArch64ABIInfo::isIllegalVectorType(QualType Ty) const { 5335276479Sdim if (const VectorType *VT = Ty->getAs<VectorType>()) { 5336276479Sdim // Check whether VT is legal. 5337276479Sdim unsigned NumElements = VT->getNumElements(); 5338276479Sdim uint64_t Size = getContext().getTypeSize(VT); 5339309124Sdim // NumElements should be power of 2. 5340309124Sdim if (!llvm::isPowerOf2_32(NumElements)) 5341276479Sdim return true; 5342360784Sdim 5343360784Sdim // arm64_32 has to be compatible with the ARM logic here, which allows huge 5344360784Sdim // vectors for some reason. 5345360784Sdim llvm::Triple Triple = getTarget().getTriple(); 5346360784Sdim if (Triple.getArch() == llvm::Triple::aarch64_32 && 5347360784Sdim Triple.isOSBinFormatMachO()) 5348360784Sdim return Size <= 32; 5349360784Sdim 5350276479Sdim return Size != 64 && (Size != 128 || NumElements == 1); 5351276479Sdim } 5352276479Sdim return false; 5353276479Sdim} 5354276479Sdim 5355321369Sdimbool AArch64ABIInfo::isLegalVectorTypeForSwift(CharUnits totalSize, 5356321369Sdim llvm::Type *eltTy, 5357321369Sdim unsigned elts) const { 5358321369Sdim if (!llvm::isPowerOf2_32(elts)) 5359321369Sdim return false; 5360321369Sdim if (totalSize.getQuantity() != 8 && 5361321369Sdim (totalSize.getQuantity() != 16 || elts == 1)) 5362321369Sdim return false; 5363321369Sdim return true; 5364321369Sdim} 5365321369Sdim 5366280031Sdimbool AArch64ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const { 5367280031Sdim // Homogeneous aggregates for AAPCS64 must have base types of a floating 5368280031Sdim // point type or a short-vector type. This is the same as the 32-bit ABI, 5369280031Sdim // but with the difference that any floating-point type is allowed, 5370280031Sdim // including __fp16. 5371280031Sdim if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) { 5372280031Sdim if (BT->isFloatingPoint()) 5373280031Sdim return true; 5374280031Sdim } else if (const VectorType *VT = Ty->getAs<VectorType>()) { 5375280031Sdim unsigned VecSize = getContext().getTypeSize(VT); 5376280031Sdim if (VecSize == 64 || VecSize == 128) 5377280031Sdim return true; 5378280031Sdim } 5379280031Sdim return false; 5380280031Sdim} 5381280031Sdim 5382280031Sdimbool AArch64ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base, 5383280031Sdim uint64_t Members) const { 5384280031Sdim return Members <= 4; 5385280031Sdim} 5386280031Sdim 5387296417SdimAddress AArch64ABIInfo::EmitAAPCSVAArg(Address VAListAddr, 5388280031Sdim QualType Ty, 5389280031Sdim CodeGenFunction &CGF) const { 5390280031Sdim ABIArgInfo AI = classifyArgumentType(Ty); 5391280031Sdim bool IsIndirect = AI.isIndirect(); 5392280031Sdim 5393280031Sdim llvm::Type *BaseTy = CGF.ConvertType(Ty); 5394280031Sdim if (IsIndirect) 5395280031Sdim BaseTy = llvm::PointerType::getUnqual(BaseTy); 5396280031Sdim else if (AI.getCoerceToType()) 5397280031Sdim BaseTy = AI.getCoerceToType(); 5398280031Sdim 5399280031Sdim unsigned NumRegs = 1; 5400280031Sdim if (llvm::ArrayType *ArrTy = dyn_cast<llvm::ArrayType>(BaseTy)) { 5401280031Sdim BaseTy = ArrTy->getElementType(); 5402280031Sdim NumRegs = ArrTy->getNumElements(); 5403280031Sdim } 5404280031Sdim bool IsFPR = BaseTy->isFloatingPointTy() || BaseTy->isVectorTy(); 5405280031Sdim 5406276479Sdim // The AArch64 va_list type and handling is specified in the Procedure Call 5407276479Sdim // Standard, section B.4: 5408276479Sdim // 5409276479Sdim // struct { 5410276479Sdim // void *__stack; 5411276479Sdim // void *__gr_top; 5412276479Sdim // void *__vr_top; 5413276479Sdim // int __gr_offs; 5414276479Sdim // int __vr_offs; 5415276479Sdim // }; 5416276479Sdim 5417276479Sdim llvm::BasicBlock *MaybeRegBlock = CGF.createBasicBlock("vaarg.maybe_reg"); 5418276479Sdim llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg"); 5419276479Sdim llvm::BasicBlock *OnStackBlock = CGF.createBasicBlock("vaarg.on_stack"); 5420276479Sdim llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end"); 5421276479Sdim 5422353358Sdim CharUnits TySize = getContext().getTypeSizeInChars(Ty); 5423353358Sdim CharUnits TyAlign = getContext().getTypeUnadjustedAlignInChars(Ty); 5424296417Sdim 5425296417Sdim Address reg_offs_p = Address::invalid(); 5426296417Sdim llvm::Value *reg_offs = nullptr; 5427276479Sdim int reg_top_index; 5428353358Sdim int RegSize = IsIndirect ? 8 : TySize.getQuantity(); 5429280031Sdim if (!IsFPR) { 5430276479Sdim // 3 is the field number of __gr_offs 5431353358Sdim reg_offs_p = CGF.Builder.CreateStructGEP(VAListAddr, 3, "gr_offs_p"); 5432276479Sdim reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "gr_offs"); 5433276479Sdim reg_top_index = 1; // field number for __gr_top 5434309124Sdim RegSize = llvm::alignTo(RegSize, 8); 5435276479Sdim } else { 5436276479Sdim // 4 is the field number of __vr_offs. 5437353358Sdim reg_offs_p = CGF.Builder.CreateStructGEP(VAListAddr, 4, "vr_offs_p"); 5438276479Sdim reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "vr_offs"); 5439276479Sdim reg_top_index = 2; // field number for __vr_top 5440280031Sdim RegSize = 16 * NumRegs; 5441276479Sdim } 5442276479Sdim 5443276479Sdim //======================================= 5444276479Sdim // Find out where argument was passed 5445276479Sdim //======================================= 5446276479Sdim 5447276479Sdim // If reg_offs >= 0 we're already using the stack for this type of 5448276479Sdim // argument. We don't want to keep updating reg_offs (in case it overflows, 5449276479Sdim // though anyone passing 2GB of arguments, each at most 16 bytes, deserves 5450276479Sdim // whatever they get). 5451276479Sdim llvm::Value *UsingStack = nullptr; 5452276479Sdim UsingStack = CGF.Builder.CreateICmpSGE( 5453276479Sdim reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, 0)); 5454276479Sdim 5455276479Sdim CGF.Builder.CreateCondBr(UsingStack, OnStackBlock, MaybeRegBlock); 5456276479Sdim 5457276479Sdim // Otherwise, at least some kind of argument could go in these registers, the 5458276479Sdim // question is whether this particular type is too big. 5459276479Sdim CGF.EmitBlock(MaybeRegBlock); 5460276479Sdim 5461276479Sdim // Integer arguments may need to correct register alignment (for example a 5462276479Sdim // "struct { __int128 a; };" gets passed in x_2N, x_{2N+1}). In this case we 5463276479Sdim // align __gr_offs to calculate the potential address. 5464296417Sdim if (!IsFPR && !IsIndirect && TyAlign.getQuantity() > 8) { 5465296417Sdim int Align = TyAlign.getQuantity(); 5466276479Sdim 5467276479Sdim reg_offs = CGF.Builder.CreateAdd( 5468276479Sdim reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, Align - 1), 5469276479Sdim "align_regoffs"); 5470276479Sdim reg_offs = CGF.Builder.CreateAnd( 5471276479Sdim reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, -Align), 5472276479Sdim "aligned_regoffs"); 5473276479Sdim } 5474276479Sdim 5475276479Sdim // Update the gr_offs/vr_offs pointer for next call to va_arg on this va_list. 5476296417Sdim // The fact that this is done unconditionally reflects the fact that 5477296417Sdim // allocating an argument to the stack also uses up all the remaining 5478296417Sdim // registers of the appropriate kind. 5479276479Sdim llvm::Value *NewOffset = nullptr; 5480276479Sdim NewOffset = CGF.Builder.CreateAdd( 5481276479Sdim reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs"); 5482276479Sdim CGF.Builder.CreateStore(NewOffset, reg_offs_p); 5483276479Sdim 5484276479Sdim // Now we're in a position to decide whether this argument really was in 5485276479Sdim // registers or not. 5486276479Sdim llvm::Value *InRegs = nullptr; 5487276479Sdim InRegs = CGF.Builder.CreateICmpSLE( 5488276479Sdim NewOffset, llvm::ConstantInt::get(CGF.Int32Ty, 0), "inreg"); 5489276479Sdim 5490276479Sdim CGF.Builder.CreateCondBr(InRegs, InRegBlock, OnStackBlock); 5491276479Sdim 5492276479Sdim //======================================= 5493276479Sdim // Argument was in registers 5494276479Sdim //======================================= 5495276479Sdim 5496276479Sdim // Now we emit the code for if the argument was originally passed in 5497276479Sdim // registers. First start the appropriate block: 5498276479Sdim CGF.EmitBlock(InRegBlock); 5499276479Sdim 5500296417Sdim llvm::Value *reg_top = nullptr; 5501353358Sdim Address reg_top_p = 5502353358Sdim CGF.Builder.CreateStructGEP(VAListAddr, reg_top_index, "reg_top_p"); 5503276479Sdim reg_top = CGF.Builder.CreateLoad(reg_top_p, "reg_top"); 5504296417Sdim Address BaseAddr(CGF.Builder.CreateInBoundsGEP(reg_top, reg_offs), 5505296417Sdim CharUnits::fromQuantity(IsFPR ? 16 : 8)); 5506296417Sdim Address RegAddr = Address::invalid(); 5507296417Sdim llvm::Type *MemTy = CGF.ConvertTypeForMem(Ty); 5508276479Sdim 5509276479Sdim if (IsIndirect) { 5510276479Sdim // If it's been passed indirectly (actually a struct), whatever we find from 5511276479Sdim // stored registers or on the stack will actually be a struct **. 5512276479Sdim MemTy = llvm::PointerType::getUnqual(MemTy); 5513276479Sdim } 5514276479Sdim 5515276479Sdim const Type *Base = nullptr; 5516280031Sdim uint64_t NumMembers = 0; 5517280031Sdim bool IsHFA = isHomogeneousAggregate(Ty, Base, NumMembers); 5518276479Sdim if (IsHFA && NumMembers > 1) { 5519276479Sdim // Homogeneous aggregates passed in registers will have their elements split 5520276479Sdim // and stored 16-bytes apart regardless of size (they're notionally in qN, 5521276479Sdim // qN+1, ...). We reload and store into a temporary local variable 5522276479Sdim // contiguously. 5523276479Sdim assert(!IsIndirect && "Homogeneous aggregates should be passed directly"); 5524296417Sdim auto BaseTyInfo = getContext().getTypeInfoInChars(QualType(Base, 0)); 5525276479Sdim llvm::Type *BaseTy = CGF.ConvertType(QualType(Base, 0)); 5526276479Sdim llvm::Type *HFATy = llvm::ArrayType::get(BaseTy, NumMembers); 5527296417Sdim Address Tmp = CGF.CreateTempAlloca(HFATy, 5528296417Sdim std::max(TyAlign, BaseTyInfo.second)); 5529296417Sdim 5530296417Sdim // On big-endian platforms, the value will be right-aligned in its slot. 5531276479Sdim int Offset = 0; 5532296417Sdim if (CGF.CGM.getDataLayout().isBigEndian() && 5533296417Sdim BaseTyInfo.first.getQuantity() < 16) 5534296417Sdim Offset = 16 - BaseTyInfo.first.getQuantity(); 5535276479Sdim 5536276479Sdim for (unsigned i = 0; i < NumMembers; ++i) { 5537296417Sdim CharUnits BaseOffset = CharUnits::fromQuantity(16 * i + Offset); 5538296417Sdim Address LoadAddr = 5539296417Sdim CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, BaseOffset); 5540296417Sdim LoadAddr = CGF.Builder.CreateElementBitCast(LoadAddr, BaseTy); 5541276479Sdim 5542353358Sdim Address StoreAddr = CGF.Builder.CreateConstArrayGEP(Tmp, i); 5543296417Sdim 5544276479Sdim llvm::Value *Elem = CGF.Builder.CreateLoad(LoadAddr); 5545276479Sdim CGF.Builder.CreateStore(Elem, StoreAddr); 5546276479Sdim } 5547276479Sdim 5548296417Sdim RegAddr = CGF.Builder.CreateElementBitCast(Tmp, MemTy); 5549276479Sdim } else { 5550296417Sdim // Otherwise the object is contiguous in memory. 5551296417Sdim 5552296417Sdim // It might be right-aligned in its slot. 5553296417Sdim CharUnits SlotSize = BaseAddr.getAlignment(); 5554296417Sdim if (CGF.CGM.getDataLayout().isBigEndian() && !IsIndirect && 5555276479Sdim (IsHFA || !isAggregateTypeForABI(Ty)) && 5556353358Sdim TySize < SlotSize) { 5557353358Sdim CharUnits Offset = SlotSize - TySize; 5558296417Sdim BaseAddr = CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, Offset); 5559276479Sdim } 5560276479Sdim 5561296417Sdim RegAddr = CGF.Builder.CreateElementBitCast(BaseAddr, MemTy); 5562276479Sdim } 5563276479Sdim 5564276479Sdim CGF.EmitBranch(ContBlock); 5565276479Sdim 5566276479Sdim //======================================= 5567276479Sdim // Argument was on the stack 5568276479Sdim //======================================= 5569276479Sdim CGF.EmitBlock(OnStackBlock); 5570276479Sdim 5571353358Sdim Address stack_p = CGF.Builder.CreateStructGEP(VAListAddr, 0, "stack_p"); 5572296417Sdim llvm::Value *OnStackPtr = CGF.Builder.CreateLoad(stack_p, "stack"); 5573276479Sdim 5574296417Sdim // Again, stack arguments may need realignment. In this case both integer and 5575276479Sdim // floating-point ones might be affected. 5576296417Sdim if (!IsIndirect && TyAlign.getQuantity() > 8) { 5577296417Sdim int Align = TyAlign.getQuantity(); 5578276479Sdim 5579296417Sdim OnStackPtr = CGF.Builder.CreatePtrToInt(OnStackPtr, CGF.Int64Ty); 5580276479Sdim 5581296417Sdim OnStackPtr = CGF.Builder.CreateAdd( 5582296417Sdim OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, Align - 1), 5583276479Sdim "align_stack"); 5584296417Sdim OnStackPtr = CGF.Builder.CreateAnd( 5585296417Sdim OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, -Align), 5586276479Sdim "align_stack"); 5587276479Sdim 5588296417Sdim OnStackPtr = CGF.Builder.CreateIntToPtr(OnStackPtr, CGF.Int8PtrTy); 5589276479Sdim } 5590296417Sdim Address OnStackAddr(OnStackPtr, 5591296417Sdim std::max(CharUnits::fromQuantity(8), TyAlign)); 5592276479Sdim 5593296417Sdim // All stack slots are multiples of 8 bytes. 5594296417Sdim CharUnits StackSlotSize = CharUnits::fromQuantity(8); 5595296417Sdim CharUnits StackSize; 5596276479Sdim if (IsIndirect) 5597296417Sdim StackSize = StackSlotSize; 5598276479Sdim else 5599353358Sdim StackSize = TySize.alignTo(StackSlotSize); 5600276479Sdim 5601296417Sdim llvm::Value *StackSizeC = CGF.Builder.getSize(StackSize); 5602276479Sdim llvm::Value *NewStack = 5603296417Sdim CGF.Builder.CreateInBoundsGEP(OnStackPtr, StackSizeC, "new_stack"); 5604276479Sdim 5605276479Sdim // Write the new value of __stack for the next call to va_arg 5606276479Sdim CGF.Builder.CreateStore(NewStack, stack_p); 5607276479Sdim 5608276479Sdim if (CGF.CGM.getDataLayout().isBigEndian() && !isAggregateTypeForABI(Ty) && 5609353358Sdim TySize < StackSlotSize) { 5610353358Sdim CharUnits Offset = StackSlotSize - TySize; 5611296417Sdim OnStackAddr = CGF.Builder.CreateConstInBoundsByteGEP(OnStackAddr, Offset); 5612276479Sdim } 5613276479Sdim 5614296417Sdim OnStackAddr = CGF.Builder.CreateElementBitCast(OnStackAddr, MemTy); 5615276479Sdim 5616276479Sdim CGF.EmitBranch(ContBlock); 5617276479Sdim 5618276479Sdim //======================================= 5619276479Sdim // Tidy up 5620276479Sdim //======================================= 5621276479Sdim CGF.EmitBlock(ContBlock); 5622276479Sdim 5623296417Sdim Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock, 5624296417Sdim OnStackAddr, OnStackBlock, "vaargs.addr"); 5625276479Sdim 5626276479Sdim if (IsIndirect) 5627296417Sdim return Address(CGF.Builder.CreateLoad(ResAddr, "vaarg.addr"), 5628353358Sdim TyAlign); 5629276479Sdim 5630276479Sdim return ResAddr; 5631276479Sdim} 5632276479Sdim 5633296417SdimAddress AArch64ABIInfo::EmitDarwinVAArg(Address VAListAddr, QualType Ty, 5634296417Sdim CodeGenFunction &CGF) const { 5635296417Sdim // The backend's lowering doesn't support va_arg for aggregates or 5636296417Sdim // illegal vector types. Lower VAArg here for these cases and use 5637296417Sdim // the LLVM va_arg instruction for everything else. 5638276479Sdim if (!isAggregateTypeForABI(Ty) && !isIllegalVectorType(Ty)) 5639309124Sdim return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect()); 5640276479Sdim 5641360784Sdim uint64_t PointerSize = getTarget().getPointerWidth(0) / 8; 5642360784Sdim CharUnits SlotSize = CharUnits::fromQuantity(PointerSize); 5643276479Sdim 5644296417Sdim // Empty records are ignored for parameter passing purposes. 5645296417Sdim if (isEmptyRecord(getContext(), Ty, true)) { 5646296417Sdim Address Addr(CGF.Builder.CreateLoad(VAListAddr, "ap.cur"), SlotSize); 5647296417Sdim Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty)); 5648296417Sdim return Addr; 5649276479Sdim } 5650276479Sdim 5651296417Sdim // The size of the actual thing passed, which might end up just 5652296417Sdim // being a pointer for indirect types. 5653296417Sdim auto TyInfo = getContext().getTypeInfoInChars(Ty); 5654276479Sdim 5655296417Sdim // Arguments bigger than 16 bytes which aren't homogeneous 5656296417Sdim // aggregates should be passed indirectly. 5657296417Sdim bool IsIndirect = false; 5658296417Sdim if (TyInfo.first.getQuantity() > 16) { 5659296417Sdim const Type *Base = nullptr; 5660296417Sdim uint64_t Members = 0; 5661296417Sdim IsIndirect = !isHomogeneousAggregate(Ty, Base, Members); 5662276479Sdim } 5663276479Sdim 5664296417Sdim return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, 5665296417Sdim TyInfo, SlotSize, /*AllowHigherAlign*/ true); 5666276479Sdim} 5667276479Sdim 5668321369SdimAddress AArch64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr, 5669321369Sdim QualType Ty) const { 5670321369Sdim return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false, 5671321369Sdim CGF.getContext().getTypeInfoInChars(Ty), 5672321369Sdim CharUnits::fromQuantity(8), 5673321369Sdim /*allowHigherAlign*/ false); 5674321369Sdim} 5675321369Sdim 5676276479Sdim//===----------------------------------------------------------------------===// 5677202379Srdivacky// ARM ABI Implementation 5678210299Sed//===----------------------------------------------------------------------===// 5679202379Srdivacky 5680202379Srdivackynamespace { 5681202379Srdivacky 5682309124Sdimclass ARMABIInfo : public SwiftABIInfo { 5683202379Srdivackypublic: 5684202379Srdivacky enum ABIKind { 5685202379Srdivacky APCS = 0, 5686202379Srdivacky AAPCS = 1, 5687296417Sdim AAPCS_VFP = 2, 5688296417Sdim AAPCS16_VFP = 3, 5689202379Srdivacky }; 5690202379Srdivacky 5691202379Srdivackyprivate: 5692202379Srdivacky ABIKind Kind; 5693202379Srdivacky 5694202379Srdivackypublic: 5695309124Sdim ARMABIInfo(CodeGenTypes &CGT, ABIKind _Kind) 5696309124Sdim : SwiftABIInfo(CGT), Kind(_Kind) { 5697280031Sdim setCCs(); 5698249423Sdim } 5699202379Srdivacky 5700226633Sdim bool isEABI() const { 5701276479Sdim switch (getTarget().getTriple().getEnvironment()) { 5702276479Sdim case llvm::Triple::Android: 5703276479Sdim case llvm::Triple::EABI: 5704276479Sdim case llvm::Triple::EABIHF: 5705276479Sdim case llvm::Triple::GNUEABI: 5706276479Sdim case llvm::Triple::GNUEABIHF: 5707309124Sdim case llvm::Triple::MuslEABI: 5708309124Sdim case llvm::Triple::MuslEABIHF: 5709276479Sdim return true; 5710276479Sdim default: 5711276479Sdim return false; 5712276479Sdim } 5713226633Sdim } 5714226633Sdim 5715276479Sdim bool isEABIHF() const { 5716276479Sdim switch (getTarget().getTriple().getEnvironment()) { 5717276479Sdim case llvm::Triple::EABIHF: 5718276479Sdim case llvm::Triple::GNUEABIHF: 5719309124Sdim case llvm::Triple::MuslEABIHF: 5720276479Sdim return true; 5721276479Sdim default: 5722276479Sdim return false; 5723276479Sdim } 5724276479Sdim } 5725276479Sdim 5726202379Srdivacky ABIKind getABIKind() const { return Kind; } 5727202379Srdivacky 5728261991Sdimprivate: 5729353358Sdim ABIArgInfo classifyReturnType(QualType RetTy, bool isVariadic, 5730353358Sdim unsigned functionCallConv) const; 5731353358Sdim ABIArgInfo classifyArgumentType(QualType RetTy, bool isVariadic, 5732353358Sdim unsigned functionCallConv) const; 5733344779Sdim ABIArgInfo classifyHomogeneousAggregate(QualType Ty, const Type *Base, 5734344779Sdim uint64_t Members) const; 5735344779Sdim ABIArgInfo coerceIllegalVector(QualType Ty) const; 5736243830Sdim bool isIllegalVectorType(QualType Ty) const; 5737353358Sdim bool containsAnyFP16Vectors(QualType Ty) const; 5738202379Srdivacky 5739280031Sdim bool isHomogeneousAggregateBaseType(QualType Ty) const override; 5740280031Sdim bool isHomogeneousAggregateSmallEnough(const Type *Ty, 5741280031Sdim uint64_t Members) const override; 5742280031Sdim 5743353358Sdim bool isEffectivelyAAPCS_VFP(unsigned callConvention, bool acceptHalf) const; 5744353358Sdim 5745276479Sdim void computeInfo(CGFunctionInfo &FI) const override; 5746202379Srdivacky 5747296417Sdim Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 5748296417Sdim QualType Ty) const override; 5749249423Sdim 5750249423Sdim llvm::CallingConv::ID getLLVMDefaultCC() const; 5751249423Sdim llvm::CallingConv::ID getABIDefaultCC() const; 5752280031Sdim void setCCs(); 5753309124Sdim 5754341825Sdim bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars, 5755309124Sdim bool asReturnValue) const override { 5756309124Sdim return occupiesMoreThan(CGT, scalars, /*total*/ 4); 5757309124Sdim } 5758314564Sdim bool isSwiftErrorInRegister() const override { 5759314564Sdim return true; 5760314564Sdim } 5761321369Sdim bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy, 5762321369Sdim unsigned elts) const override; 5763202379Srdivacky}; 5764202379Srdivacky 5765202379Srdivackyclass ARMTargetCodeGenInfo : public TargetCodeGenInfo { 5766202379Srdivackypublic: 5767212904Sdim ARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K) 5768212904Sdim :TargetCodeGenInfo(new ARMABIInfo(CGT, K)) {} 5769204793Srdivacky 5770226633Sdim const ARMABIInfo &getABIInfo() const { 5771226633Sdim return static_cast<const ARMABIInfo&>(TargetCodeGenInfo::getABIInfo()); 5772226633Sdim } 5773226633Sdim 5774276479Sdim int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override { 5775204793Srdivacky return 13; 5776204793Srdivacky } 5777223017Sdim 5778276479Sdim StringRef getARCRetainAutoreleasedReturnValueMarker() const override { 5779327952Sdim return "mov\tr7, r7\t\t// marker for objc_retainAutoreleaseReturnValue"; 5780224145Sdim } 5781224145Sdim 5782223017Sdim bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 5783276479Sdim llvm::Value *Address) const override { 5784234353Sdim llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4); 5785223017Sdim 5786223017Sdim // 0-15 are the 16 integer registers. 5787234353Sdim AssignToArrayRange(CGF.Builder, Address, Four8, 0, 15); 5788223017Sdim return false; 5789223017Sdim } 5790226633Sdim 5791276479Sdim unsigned getSizeOfUnwindException() const override { 5792226633Sdim if (getABIInfo().isEABI()) return 88; 5793226633Sdim return TargetCodeGenInfo::getSizeOfUnwindException(); 5794226633Sdim } 5795261991Sdim 5796288943Sdim void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 5797341825Sdim CodeGen::CodeGenModule &CGM) const override { 5798341825Sdim if (GV->isDeclaration()) 5799327952Sdim return; 5800296417Sdim const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D); 5801261991Sdim if (!FD) 5802261991Sdim return; 5803261991Sdim 5804261991Sdim const ARMInterruptAttr *Attr = FD->getAttr<ARMInterruptAttr>(); 5805261991Sdim if (!Attr) 5806261991Sdim return; 5807261991Sdim 5808261991Sdim const char *Kind; 5809261991Sdim switch (Attr->getInterrupt()) { 5810261991Sdim case ARMInterruptAttr::Generic: Kind = ""; break; 5811261991Sdim case ARMInterruptAttr::IRQ: Kind = "IRQ"; break; 5812261991Sdim case ARMInterruptAttr::FIQ: Kind = "FIQ"; break; 5813261991Sdim case ARMInterruptAttr::SWI: Kind = "SWI"; break; 5814261991Sdim case ARMInterruptAttr::ABORT: Kind = "ABORT"; break; 5815261991Sdim case ARMInterruptAttr::UNDEF: Kind = "UNDEF"; break; 5816261991Sdim } 5817261991Sdim 5818261991Sdim llvm::Function *Fn = cast<llvm::Function>(GV); 5819261991Sdim 5820261991Sdim Fn->addFnAttr("interrupt", Kind); 5821261991Sdim 5822296417Sdim ARMABIInfo::ABIKind ABI = cast<ARMABIInfo>(getABIInfo()).getABIKind(); 5823296417Sdim if (ABI == ARMABIInfo::APCS) 5824261991Sdim return; 5825261991Sdim 5826261991Sdim // AAPCS guarantees that sp will be 8-byte aligned on any public interface, 5827261991Sdim // however this is not necessarily true on taking any interrupt. Instruct 5828261991Sdim // the backend to perform a realignment as part of the function prologue. 5829261991Sdim llvm::AttrBuilder B; 5830261991Sdim B.addStackAlignmentAttr(8); 5831321369Sdim Fn->addAttributes(llvm::AttributeList::FunctionIndex, B); 5832261991Sdim } 5833202379Srdivacky}; 5834202379Srdivacky 5835288943Sdimclass WindowsARMTargetCodeGenInfo : public ARMTargetCodeGenInfo { 5836288943Sdimpublic: 5837288943Sdim WindowsARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K) 5838288943Sdim : ARMTargetCodeGenInfo(CGT, K) {} 5839288943Sdim 5840288943Sdim void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 5841341825Sdim CodeGen::CodeGenModule &CGM) const override; 5842309124Sdim 5843309124Sdim void getDependentLibraryOption(llvm::StringRef Lib, 5844309124Sdim llvm::SmallString<24> &Opt) const override { 5845309124Sdim Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib); 5846309124Sdim } 5847309124Sdim 5848309124Sdim void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value, 5849309124Sdim llvm::SmallString<32> &Opt) const override { 5850309124Sdim Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\""; 5851309124Sdim } 5852288943Sdim}; 5853288943Sdim 5854288943Sdimvoid WindowsARMTargetCodeGenInfo::setTargetAttributes( 5855341825Sdim const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const { 5856341825Sdim ARMTargetCodeGenInfo::setTargetAttributes(D, GV, CGM); 5857341825Sdim if (GV->isDeclaration()) 5858327952Sdim return; 5859341825Sdim addStackProbeTargetAttributes(D, GV, CGM); 5860288943Sdim} 5861288943Sdim} 5862288943Sdim 5863212904Sdimvoid ARMABIInfo::computeInfo(CGFunctionInfo &FI) const { 5864341825Sdim if (!::classifyReturnType(getCXXABI(), FI, *this)) 5865353358Sdim FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), FI.isVariadic(), 5866353358Sdim FI.getCallingConvention()); 5867276479Sdim 5868288943Sdim for (auto &I : FI.arguments()) 5869353358Sdim I.info = classifyArgumentType(I.type, FI.isVariadic(), 5870353358Sdim FI.getCallingConvention()); 5871276479Sdim 5872353358Sdim 5873221345Sdim // Always honor user-specified calling convention. 5874221345Sdim if (FI.getCallingConvention() != llvm::CallingConv::C) 5875221345Sdim return; 5876221345Sdim 5877249423Sdim llvm::CallingConv::ID cc = getRuntimeCC(); 5878249423Sdim if (cc != llvm::CallingConv::C) 5879288943Sdim FI.setEffectiveCallingConvention(cc); 5880249423Sdim} 5881249423Sdim 5882249423Sdim/// Return the default calling convention that LLVM will use. 5883249423Sdimllvm::CallingConv::ID ARMABIInfo::getLLVMDefaultCC() const { 5884249423Sdim // The default calling convention that LLVM will infer. 5885309124Sdim if (isEABIHF() || getTarget().getTriple().isWatchABI()) 5886249423Sdim return llvm::CallingConv::ARM_AAPCS_VFP; 5887243830Sdim else if (isEABI()) 5888249423Sdim return llvm::CallingConv::ARM_AAPCS; 5889210299Sed else 5890249423Sdim return llvm::CallingConv::ARM_APCS; 5891249423Sdim} 5892210299Sed 5893249423Sdim/// Return the calling convention that our ABI would like us to use 5894249423Sdim/// as the C calling convention. 5895249423Sdimllvm::CallingConv::ID ARMABIInfo::getABIDefaultCC() const { 5896202379Srdivacky switch (getABIKind()) { 5897249423Sdim case APCS: return llvm::CallingConv::ARM_APCS; 5898249423Sdim case AAPCS: return llvm::CallingConv::ARM_AAPCS; 5899249423Sdim case AAPCS_VFP: return llvm::CallingConv::ARM_AAPCS_VFP; 5900296417Sdim case AAPCS16_VFP: return llvm::CallingConv::ARM_AAPCS_VFP; 5901202379Srdivacky } 5902249423Sdim llvm_unreachable("bad ABI kind"); 5903202379Srdivacky} 5904202379Srdivacky 5905280031Sdimvoid ARMABIInfo::setCCs() { 5906249423Sdim assert(getRuntimeCC() == llvm::CallingConv::C); 5907249423Sdim 5908249423Sdim // Don't muddy up the IR with a ton of explicit annotations if 5909249423Sdim // they'd just match what LLVM will infer from the triple. 5910249423Sdim llvm::CallingConv::ID abiCC = getABIDefaultCC(); 5911249423Sdim if (abiCC != getLLVMDefaultCC()) 5912249423Sdim RuntimeCC = abiCC; 5913226633Sdim} 5914226633Sdim 5915344779SdimABIArgInfo ARMABIInfo::coerceIllegalVector(QualType Ty) const { 5916344779Sdim uint64_t Size = getContext().getTypeSize(Ty); 5917344779Sdim if (Size <= 32) { 5918344779Sdim llvm::Type *ResType = 5919344779Sdim llvm::Type::getInt32Ty(getVMContext()); 5920344779Sdim return ABIArgInfo::getDirect(ResType); 5921344779Sdim } 5922344779Sdim if (Size == 64 || Size == 128) { 5923344779Sdim llvm::Type *ResType = llvm::VectorType::get( 5924344779Sdim llvm::Type::getInt32Ty(getVMContext()), Size / 32); 5925344779Sdim return ABIArgInfo::getDirect(ResType); 5926344779Sdim } 5927344779Sdim return getNaturalAlignIndirect(Ty, /*ByVal=*/false); 5928344779Sdim} 5929344779Sdim 5930344779SdimABIArgInfo ARMABIInfo::classifyHomogeneousAggregate(QualType Ty, 5931344779Sdim const Type *Base, 5932344779Sdim uint64_t Members) const { 5933344779Sdim assert(Base && "Base class should be set for homogeneous aggregate"); 5934344779Sdim // Base can be a floating-point or a vector. 5935344779Sdim if (const VectorType *VT = Base->getAs<VectorType>()) { 5936344779Sdim // FP16 vectors should be converted to integer vectors 5937353358Sdim if (!getTarget().hasLegalHalfType() && containsAnyFP16Vectors(Ty)) { 5938344779Sdim uint64_t Size = getContext().getTypeSize(VT); 5939344779Sdim llvm::Type *NewVecTy = llvm::VectorType::get( 5940344779Sdim llvm::Type::getInt32Ty(getVMContext()), Size / 32); 5941344779Sdim llvm::Type *Ty = llvm::ArrayType::get(NewVecTy, Members); 5942344779Sdim return ABIArgInfo::getDirect(Ty, 0, nullptr, false); 5943344779Sdim } 5944344779Sdim } 5945344779Sdim return ABIArgInfo::getDirect(nullptr, 0, nullptr, false); 5946344779Sdim} 5947344779Sdim 5948353358SdimABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty, bool isVariadic, 5949353358Sdim unsigned functionCallConv) const { 5950243830Sdim // 6.1.2.1 The following argument types are VFP CPRCs: 5951243830Sdim // A single-precision floating-point type (including promoted 5952243830Sdim // half-precision types); A double-precision floating-point type; 5953243830Sdim // A 64-bit or 128-bit containerized vector type; Homogeneous Aggregate 5954243830Sdim // with a Base Type of a single- or double-precision floating-point type, 5955243830Sdim // 64-bit containerized vectors or 128-bit containerized vectors with one 5956243830Sdim // to four Elements. 5957353358Sdim // Variadic functions should always marshal to the base standard. 5958353358Sdim bool IsAAPCS_VFP = 5959353358Sdim !isVariadic && isEffectivelyAAPCS_VFP(functionCallConv, /* AAPCS16 */ false); 5960243830Sdim 5961280031Sdim Ty = useFirstFieldIfTransparentUnion(Ty); 5962280031Sdim 5963243830Sdim // Handle illegal vector types here. 5964344779Sdim if (isIllegalVectorType(Ty)) 5965344779Sdim return coerceIllegalVector(Ty); 5966243830Sdim 5967341825Sdim // _Float16 and __fp16 get passed as if it were an int or float, but with 5968341825Sdim // the top 16 bits unspecified. This is not done for OpenCL as it handles the 5969341825Sdim // half type natively, and does not need to interwork with AAPCS code. 5970341825Sdim if ((Ty->isFloat16Type() || Ty->isHalfType()) && 5971341825Sdim !getContext().getLangOpts().NativeHalfArgsAndReturns) { 5972353358Sdim llvm::Type *ResType = IsAAPCS_VFP ? 5973296417Sdim llvm::Type::getFloatTy(getVMContext()) : 5974296417Sdim llvm::Type::getInt32Ty(getVMContext()); 5975296417Sdim return ABIArgInfo::getDirect(ResType); 5976296417Sdim } 5977296417Sdim 5978212904Sdim if (!isAggregateTypeForABI(Ty)) { 5979203955Srdivacky // Treat an enum type as its underlying type. 5980276479Sdim if (const EnumType *EnumTy = Ty->getAs<EnumType>()) { 5981203955Srdivacky Ty = EnumTy->getDecl()->getIntegerType(); 5982276479Sdim } 5983203955Srdivacky 5984341825Sdim return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty) 5985280031Sdim : ABIArgInfo::getDirect()); 5986203955Srdivacky } 5987202379Srdivacky 5988276479Sdim if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) { 5989296417Sdim return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory); 5990276479Sdim } 5991261991Sdim 5992202379Srdivacky // Ignore empty records. 5993212904Sdim if (isEmptyRecord(getContext(), Ty, true)) 5994202379Srdivacky return ABIArgInfo::getIgnore(); 5995202379Srdivacky 5996353358Sdim if (IsAAPCS_VFP) { 5997243830Sdim // Homogeneous Aggregates need to be expanded when we can fit the aggregate 5998243830Sdim // into VFP registers. 5999276479Sdim const Type *Base = nullptr; 6000243830Sdim uint64_t Members = 0; 6001344779Sdim if (isHomogeneousAggregate(Ty, Base, Members)) 6002344779Sdim return classifyHomogeneousAggregate(Ty, Base, Members); 6003296417Sdim } else if (getABIKind() == ARMABIInfo::AAPCS16_VFP) { 6004296417Sdim // WatchOS does have homogeneous aggregates. Note that we intentionally use 6005296417Sdim // this convention even for a variadic function: the backend will use GPRs 6006296417Sdim // if needed. 6007296417Sdim const Type *Base = nullptr; 6008296417Sdim uint64_t Members = 0; 6009296417Sdim if (isHomogeneousAggregate(Ty, Base, Members)) { 6010296417Sdim assert(Base && Members <= 4 && "unexpected homogeneous aggregate"); 6011296417Sdim llvm::Type *Ty = 6012296417Sdim llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members); 6013296417Sdim return ABIArgInfo::getDirect(Ty, 0, nullptr, false); 6014296417Sdim } 6015226633Sdim } 6016226633Sdim 6017296417Sdim if (getABIKind() == ARMABIInfo::AAPCS16_VFP && 6018296417Sdim getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(16)) { 6019296417Sdim // WatchOS is adopting the 64-bit AAPCS rule on composite types: if they're 6020296417Sdim // bigger than 128-bits, they get placed in space allocated by the caller, 6021296417Sdim // and a pointer is passed. 6022296417Sdim return ABIArgInfo::getIndirect( 6023296417Sdim CharUnits::fromQuantity(getContext().getTypeAlign(Ty) / 8), false); 6024296417Sdim } 6025296417Sdim 6026239462Sdim // Support byval for ARM. 6027243830Sdim // The ABI alignment for APCS is 4-byte and for AAPCS at least 4-byte and at 6028243830Sdim // most 8-byte. We realign the indirect argument if type alignment is bigger 6029243830Sdim // than ABI alignment. 6030243830Sdim uint64_t ABIAlign = 4; 6031341825Sdim uint64_t TyAlign; 6032243830Sdim if (getABIKind() == ARMABIInfo::AAPCS_VFP || 6033341825Sdim getABIKind() == ARMABIInfo::AAPCS) { 6034341825Sdim TyAlign = getContext().getTypeUnadjustedAlignInChars(Ty).getQuantity(); 6035243830Sdim ABIAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8); 6036341825Sdim } else { 6037341825Sdim TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity(); 6038341825Sdim } 6039243830Sdim if (getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(64)) { 6040296417Sdim assert(getABIKind() != ARMABIInfo::AAPCS16_VFP && "unexpected byval"); 6041296417Sdim return ABIArgInfo::getIndirect(CharUnits::fromQuantity(ABIAlign), 6042296417Sdim /*ByVal=*/true, 6043296417Sdim /*Realign=*/TyAlign > ABIAlign); 6044239462Sdim } 6045239462Sdim 6046314564Sdim // On RenderScript, coerce Aggregates <= 64 bytes to an integer array of 6047314564Sdim // same size and alignment. 6048314564Sdim if (getTarget().isRenderScriptTarget()) { 6049314564Sdim return coerceToIntArray(Ty, getContext(), getVMContext()); 6050314564Sdim } 6051314564Sdim 6052218893Sdim // Otherwise, pass by coercing to a structure of the appropriate size. 6053226633Sdim llvm::Type* ElemTy; 6054202379Srdivacky unsigned SizeRegs; 6055239462Sdim // FIXME: Try to match the types of the arguments more accurately where 6056239462Sdim // we can. 6057341825Sdim if (TyAlign <= 4) { 6058239462Sdim ElemTy = llvm::Type::getInt32Ty(getVMContext()); 6059239462Sdim SizeRegs = (getContext().getTypeSize(Ty) + 31) / 32; 6060239462Sdim } else { 6061226633Sdim ElemTy = llvm::Type::getInt64Ty(getVMContext()); 6062226633Sdim SizeRegs = (getContext().getTypeSize(Ty) + 63) / 64; 6063202379Srdivacky } 6064221345Sdim 6065280031Sdim return ABIArgInfo::getDirect(llvm::ArrayType::get(ElemTy, SizeRegs)); 6066202379Srdivacky} 6067202379Srdivacky 6068212904Sdimstatic bool isIntegerLikeType(QualType Ty, ASTContext &Context, 6069202379Srdivacky llvm::LLVMContext &VMContext) { 6070202379Srdivacky // APCS, C Language Calling Conventions, Non-Simple Return Values: A structure 6071202379Srdivacky // is called integer-like if its size is less than or equal to one word, and 6072202379Srdivacky // the offset of each of its addressable sub-fields is zero. 6073202379Srdivacky 6074202379Srdivacky uint64_t Size = Context.getTypeSize(Ty); 6075202379Srdivacky 6076202379Srdivacky // Check that the type fits in a word. 6077202379Srdivacky if (Size > 32) 6078202379Srdivacky return false; 6079202379Srdivacky 6080202379Srdivacky // FIXME: Handle vector types! 6081202379Srdivacky if (Ty->isVectorType()) 6082202379Srdivacky return false; 6083202379Srdivacky 6084202379Srdivacky // Float types are never treated as "integer like". 6085202379Srdivacky if (Ty->isRealFloatingType()) 6086202379Srdivacky return false; 6087202379Srdivacky 6088202379Srdivacky // If this is a builtin or pointer type then it is ok. 6089202379Srdivacky if (Ty->getAs<BuiltinType>() || Ty->isPointerType()) 6090202379Srdivacky return true; 6091202379Srdivacky 6092203955Srdivacky // Small complex integer types are "integer like". 6093203955Srdivacky if (const ComplexType *CT = Ty->getAs<ComplexType>()) 6094203955Srdivacky return isIntegerLikeType(CT->getElementType(), Context, VMContext); 6095202379Srdivacky 6096202379Srdivacky // Single element and zero sized arrays should be allowed, by the definition 6097202379Srdivacky // above, but they are not. 6098202379Srdivacky 6099202379Srdivacky // Otherwise, it must be a record type. 6100202379Srdivacky const RecordType *RT = Ty->getAs<RecordType>(); 6101202379Srdivacky if (!RT) return false; 6102202379Srdivacky 6103202379Srdivacky // Ignore records with flexible arrays. 6104202379Srdivacky const RecordDecl *RD = RT->getDecl(); 6105202379Srdivacky if (RD->hasFlexibleArrayMember()) 6106202379Srdivacky return false; 6107202379Srdivacky 6108202379Srdivacky // Check that all sub-fields are at offset 0, and are themselves "integer 6109202379Srdivacky // like". 6110202379Srdivacky const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD); 6111202379Srdivacky 6112202379Srdivacky bool HadField = false; 6113202379Srdivacky unsigned idx = 0; 6114202379Srdivacky for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 6115202379Srdivacky i != e; ++i, ++idx) { 6116202379Srdivacky const FieldDecl *FD = *i; 6117202379Srdivacky 6118203955Srdivacky // Bit-fields are not addressable, we only need to verify they are "integer 6119203955Srdivacky // like". We still have to disallow a subsequent non-bitfield, for example: 6120203955Srdivacky // struct { int : 0; int x } 6121203955Srdivacky // is non-integer like according to gcc. 6122203955Srdivacky if (FD->isBitField()) { 6123203955Srdivacky if (!RD->isUnion()) 6124203955Srdivacky HadField = true; 6125202379Srdivacky 6126203955Srdivacky if (!isIntegerLikeType(FD->getType(), Context, VMContext)) 6127203955Srdivacky return false; 6128202379Srdivacky 6129203955Srdivacky continue; 6130202379Srdivacky } 6131202379Srdivacky 6132203955Srdivacky // Check if this field is at offset 0. 6133203955Srdivacky if (Layout.getFieldOffset(idx) != 0) 6134203955Srdivacky return false; 6135203955Srdivacky 6136202379Srdivacky if (!isIntegerLikeType(FD->getType(), Context, VMContext)) 6137202379Srdivacky return false; 6138212904Sdim 6139203955Srdivacky // Only allow at most one field in a structure. This doesn't match the 6140203955Srdivacky // wording above, but follows gcc in situations with a field following an 6141203955Srdivacky // empty structure. 6142202379Srdivacky if (!RD->isUnion()) { 6143202379Srdivacky if (HadField) 6144202379Srdivacky return false; 6145202379Srdivacky 6146202379Srdivacky HadField = true; 6147202379Srdivacky } 6148202379Srdivacky } 6149202379Srdivacky 6150202379Srdivacky return true; 6151202379Srdivacky} 6152202379Srdivacky 6153353358SdimABIArgInfo ARMABIInfo::classifyReturnType(QualType RetTy, bool isVariadic, 6154353358Sdim unsigned functionCallConv) const { 6155280031Sdim 6156353358Sdim // Variadic functions should always marshal to the base standard. 6157353358Sdim bool IsAAPCS_VFP = 6158353358Sdim !isVariadic && isEffectivelyAAPCS_VFP(functionCallConv, /* AAPCS16 */ true); 6159353358Sdim 6160202379Srdivacky if (RetTy->isVoidType()) 6161202379Srdivacky return ABIArgInfo::getIgnore(); 6162202379Srdivacky 6163344779Sdim if (const VectorType *VT = RetTy->getAs<VectorType>()) { 6164344779Sdim // Large vector types should be returned via memory. 6165344779Sdim if (getContext().getTypeSize(RetTy) > 128) 6166344779Sdim return getNaturalAlignIndirect(RetTy); 6167344779Sdim // FP16 vectors should be converted to integer vectors 6168344779Sdim if (!getTarget().hasLegalHalfType() && 6169344779Sdim (VT->getElementType()->isFloat16Type() || 6170344779Sdim VT->getElementType()->isHalfType())) 6171344779Sdim return coerceIllegalVector(RetTy); 6172276479Sdim } 6173218893Sdim 6174341825Sdim // _Float16 and __fp16 get returned as if it were an int or float, but with 6175341825Sdim // the top 16 bits unspecified. This is not done for OpenCL as it handles the 6176341825Sdim // half type natively, and does not need to interwork with AAPCS code. 6177341825Sdim if ((RetTy->isFloat16Type() || RetTy->isHalfType()) && 6178341825Sdim !getContext().getLangOpts().NativeHalfArgsAndReturns) { 6179353358Sdim llvm::Type *ResType = IsAAPCS_VFP ? 6180296417Sdim llvm::Type::getFloatTy(getVMContext()) : 6181296417Sdim llvm::Type::getInt32Ty(getVMContext()); 6182296417Sdim return ABIArgInfo::getDirect(ResType); 6183296417Sdim } 6184296417Sdim 6185212904Sdim if (!isAggregateTypeForABI(RetTy)) { 6186203955Srdivacky // Treat an enum type as its underlying type. 6187203955Srdivacky if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 6188203955Srdivacky RetTy = EnumTy->getDecl()->getIntegerType(); 6189203955Srdivacky 6190341825Sdim return RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy) 6191280031Sdim : ABIArgInfo::getDirect(); 6192203955Srdivacky } 6193202379Srdivacky 6194202379Srdivacky // Are we following APCS? 6195202379Srdivacky if (getABIKind() == APCS) { 6196212904Sdim if (isEmptyRecord(getContext(), RetTy, false)) 6197202379Srdivacky return ABIArgInfo::getIgnore(); 6198202379Srdivacky 6199203955Srdivacky // Complex types are all returned as packed integers. 6200203955Srdivacky // 6201203955Srdivacky // FIXME: Consider using 2 x vector types if the back end handles them 6202203955Srdivacky // correctly. 6203203955Srdivacky if (RetTy->isAnyComplexType()) 6204280031Sdim return ABIArgInfo::getDirect(llvm::IntegerType::get( 6205280031Sdim getVMContext(), getContext().getTypeSize(RetTy))); 6206203955Srdivacky 6207202379Srdivacky // Integer like structures are returned in r0. 6208212904Sdim if (isIntegerLikeType(RetTy, getContext(), getVMContext())) { 6209202379Srdivacky // Return in the smallest viable integer type. 6210212904Sdim uint64_t Size = getContext().getTypeSize(RetTy); 6211202379Srdivacky if (Size <= 8) 6212212904Sdim return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); 6213202379Srdivacky if (Size <= 16) 6214212904Sdim return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 6215212904Sdim return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 6216202379Srdivacky } 6217202379Srdivacky 6218202379Srdivacky // Otherwise return in memory. 6219296417Sdim return getNaturalAlignIndirect(RetTy); 6220202379Srdivacky } 6221202379Srdivacky 6222202379Srdivacky // Otherwise this is an AAPCS variant. 6223202379Srdivacky 6224212904Sdim if (isEmptyRecord(getContext(), RetTy, true)) 6225202379Srdivacky return ABIArgInfo::getIgnore(); 6226202379Srdivacky 6227234353Sdim // Check for homogeneous aggregates with AAPCS-VFP. 6228353358Sdim if (IsAAPCS_VFP) { 6229276479Sdim const Type *Base = nullptr; 6230296417Sdim uint64_t Members = 0; 6231344779Sdim if (isHomogeneousAggregate(RetTy, Base, Members)) 6232344779Sdim return classifyHomogeneousAggregate(RetTy, Base, Members); 6233234353Sdim } 6234234353Sdim 6235202379Srdivacky // Aggregates <= 4 bytes are returned in r0; other aggregates 6236202379Srdivacky // are returned indirectly. 6237212904Sdim uint64_t Size = getContext().getTypeSize(RetTy); 6238202379Srdivacky if (Size <= 32) { 6239314564Sdim // On RenderScript, coerce Aggregates <= 4 bytes to an integer array of 6240314564Sdim // same size and alignment. 6241314564Sdim if (getTarget().isRenderScriptTarget()) { 6242314564Sdim return coerceToIntArray(RetTy, getContext(), getVMContext()); 6243314564Sdim } 6244276479Sdim if (getDataLayout().isBigEndian()) 6245276479Sdim // Return in 32 bit integer integer type (as if loaded by LDR, AAPCS 5.4) 6246276479Sdim return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 6247276479Sdim 6248202379Srdivacky // Return in the smallest viable integer type. 6249202379Srdivacky if (Size <= 8) 6250212904Sdim return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); 6251202379Srdivacky if (Size <= 16) 6252212904Sdim return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 6253212904Sdim return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 6254296417Sdim } else if (Size <= 128 && getABIKind() == AAPCS16_VFP) { 6255296417Sdim llvm::Type *Int32Ty = llvm::Type::getInt32Ty(getVMContext()); 6256296417Sdim llvm::Type *CoerceTy = 6257309124Sdim llvm::ArrayType::get(Int32Ty, llvm::alignTo(Size, 32) / 32); 6258296417Sdim return ABIArgInfo::getDirect(CoerceTy); 6259202379Srdivacky } 6260202379Srdivacky 6261296417Sdim return getNaturalAlignIndirect(RetTy); 6262202379Srdivacky} 6263202379Srdivacky 6264243830Sdim/// isIllegalVector - check whether Ty is an illegal vector type. 6265243830Sdimbool ARMABIInfo::isIllegalVectorType(QualType Ty) const { 6266296417Sdim if (const VectorType *VT = Ty->getAs<VectorType> ()) { 6267344779Sdim // On targets that don't support FP16, FP16 is expanded into float, and we 6268344779Sdim // don't want the ABI to depend on whether or not FP16 is supported in 6269344779Sdim // hardware. Thus return false to coerce FP16 vectors into integer vectors. 6270344779Sdim if (!getTarget().hasLegalHalfType() && 6271344779Sdim (VT->getElementType()->isFloat16Type() || 6272344779Sdim VT->getElementType()->isHalfType())) 6273344779Sdim return true; 6274296417Sdim if (isAndroid()) { 6275296417Sdim // Android shipped using Clang 3.1, which supported a slightly different 6276296417Sdim // vector ABI. The primary differences were that 3-element vector types 6277296417Sdim // were legal, and so were sub 32-bit vectors (i.e. <2 x i8>). This path 6278296417Sdim // accepts that legacy behavior for Android only. 6279296417Sdim // Check whether VT is legal. 6280296417Sdim unsigned NumElements = VT->getNumElements(); 6281296417Sdim // NumElements should be power of 2 or equal to 3. 6282296417Sdim if (!llvm::isPowerOf2_32(NumElements) && NumElements != 3) 6283296417Sdim return true; 6284296417Sdim } else { 6285296417Sdim // Check whether VT is legal. 6286296417Sdim unsigned NumElements = VT->getNumElements(); 6287296417Sdim uint64_t Size = getContext().getTypeSize(VT); 6288296417Sdim // NumElements should be power of 2. 6289296417Sdim if (!llvm::isPowerOf2_32(NumElements)) 6290296417Sdim return true; 6291296417Sdim // Size should be greater than 32 bits. 6292296417Sdim return Size <= 32; 6293296417Sdim } 6294243830Sdim } 6295243830Sdim return false; 6296243830Sdim} 6297243830Sdim 6298353358Sdim/// Return true if a type contains any 16-bit floating point vectors 6299353358Sdimbool ARMABIInfo::containsAnyFP16Vectors(QualType Ty) const { 6300353358Sdim if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) { 6301353358Sdim uint64_t NElements = AT->getSize().getZExtValue(); 6302353358Sdim if (NElements == 0) 6303353358Sdim return false; 6304353358Sdim return containsAnyFP16Vectors(AT->getElementType()); 6305353358Sdim } else if (const RecordType *RT = Ty->getAs<RecordType>()) { 6306353358Sdim const RecordDecl *RD = RT->getDecl(); 6307353358Sdim 6308353358Sdim // If this is a C++ record, check the bases first. 6309353358Sdim if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) 6310353358Sdim if (llvm::any_of(CXXRD->bases(), [this](const CXXBaseSpecifier &B) { 6311353358Sdim return containsAnyFP16Vectors(B.getType()); 6312353358Sdim })) 6313353358Sdim return true; 6314353358Sdim 6315353358Sdim if (llvm::any_of(RD->fields(), [this](FieldDecl *FD) { 6316353358Sdim return FD && containsAnyFP16Vectors(FD->getType()); 6317353358Sdim })) 6318353358Sdim return true; 6319353358Sdim 6320353358Sdim return false; 6321353358Sdim } else { 6322353358Sdim if (const VectorType *VT = Ty->getAs<VectorType>()) 6323353358Sdim return (VT->getElementType()->isFloat16Type() || 6324353358Sdim VT->getElementType()->isHalfType()); 6325353358Sdim return false; 6326353358Sdim } 6327353358Sdim} 6328353358Sdim 6329321369Sdimbool ARMABIInfo::isLegalVectorTypeForSwift(CharUnits vectorSize, 6330321369Sdim llvm::Type *eltTy, 6331321369Sdim unsigned numElts) const { 6332321369Sdim if (!llvm::isPowerOf2_32(numElts)) 6333321369Sdim return false; 6334321369Sdim unsigned size = getDataLayout().getTypeStoreSizeInBits(eltTy); 6335321369Sdim if (size > 64) 6336321369Sdim return false; 6337321369Sdim if (vectorSize.getQuantity() != 8 && 6338321369Sdim (vectorSize.getQuantity() != 16 || numElts == 1)) 6339321369Sdim return false; 6340321369Sdim return true; 6341321369Sdim} 6342321369Sdim 6343280031Sdimbool ARMABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const { 6344280031Sdim // Homogeneous aggregates for AAPCS-VFP must have base types of float, 6345280031Sdim // double, or 64-bit or 128-bit vectors. 6346280031Sdim if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) { 6347280031Sdim if (BT->getKind() == BuiltinType::Float || 6348280031Sdim BT->getKind() == BuiltinType::Double || 6349280031Sdim BT->getKind() == BuiltinType::LongDouble) 6350280031Sdim return true; 6351280031Sdim } else if (const VectorType *VT = Ty->getAs<VectorType>()) { 6352280031Sdim unsigned VecSize = getContext().getTypeSize(VT); 6353280031Sdim if (VecSize == 64 || VecSize == 128) 6354280031Sdim return true; 6355280031Sdim } 6356280031Sdim return false; 6357280031Sdim} 6358280031Sdim 6359280031Sdimbool ARMABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base, 6360280031Sdim uint64_t Members) const { 6361280031Sdim return Members <= 4; 6362280031Sdim} 6363280031Sdim 6364353358Sdimbool ARMABIInfo::isEffectivelyAAPCS_VFP(unsigned callConvention, 6365353358Sdim bool acceptHalf) const { 6366353358Sdim // Give precedence to user-specified calling conventions. 6367353358Sdim if (callConvention != llvm::CallingConv::C) 6368353358Sdim return (callConvention == llvm::CallingConv::ARM_AAPCS_VFP); 6369353358Sdim else 6370353358Sdim return (getABIKind() == AAPCS_VFP) || 6371353358Sdim (acceptHalf && (getABIKind() == AAPCS16_VFP)); 6372353358Sdim} 6373353358Sdim 6374296417SdimAddress ARMABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 6375296417Sdim QualType Ty) const { 6376296417Sdim CharUnits SlotSize = CharUnits::fromQuantity(4); 6377202379Srdivacky 6378296417Sdim // Empty records are ignored for parameter passing purposes. 6379261991Sdim if (isEmptyRecord(getContext(), Ty, true)) { 6380296417Sdim Address Addr(CGF.Builder.CreateLoad(VAListAddr), SlotSize); 6381296417Sdim Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty)); 6382296417Sdim return Addr; 6383261991Sdim } 6384261991Sdim 6385353358Sdim CharUnits TySize = getContext().getTypeSizeInChars(Ty); 6386353358Sdim CharUnits TyAlignForABI = getContext().getTypeUnadjustedAlignInChars(Ty); 6387243830Sdim 6388243830Sdim // Use indirect if size of the illegal vector is bigger than 16 bytes. 6389296417Sdim bool IsIndirect = false; 6390296417Sdim const Type *Base = nullptr; 6391296417Sdim uint64_t Members = 0; 6392353358Sdim if (TySize > CharUnits::fromQuantity(16) && isIllegalVectorType(Ty)) { 6393243830Sdim IsIndirect = true; 6394243830Sdim 6395296417Sdim // ARMv7k passes structs bigger than 16 bytes indirectly, in space 6396296417Sdim // allocated by the caller. 6397353358Sdim } else if (TySize > CharUnits::fromQuantity(16) && 6398296417Sdim getABIKind() == ARMABIInfo::AAPCS16_VFP && 6399296417Sdim !isHomogeneousAggregate(Ty, Base, Members)) { 6400296417Sdim IsIndirect = true; 6401202379Srdivacky 6402296417Sdim // Otherwise, bound the type's ABI alignment. 6403296417Sdim // The ABI alignment for 64-bit or 128-bit vectors is 8 for AAPCS and 4 for 6404296417Sdim // APCS. For AAPCS, the ABI alignment is at least 4-byte and at most 8-byte. 6405296417Sdim // Our callers should be prepared to handle an under-aligned address. 6406296417Sdim } else if (getABIKind() == ARMABIInfo::AAPCS_VFP || 6407296417Sdim getABIKind() == ARMABIInfo::AAPCS) { 6408296417Sdim TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4)); 6409296417Sdim TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(8)); 6410296417Sdim } else if (getABIKind() == ARMABIInfo::AAPCS16_VFP) { 6411296417Sdim // ARMv7k allows type alignment up to 16 bytes. 6412296417Sdim TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4)); 6413296417Sdim TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(16)); 6414296417Sdim } else { 6415296417Sdim TyAlignForABI = CharUnits::fromQuantity(4); 6416243830Sdim } 6417243830Sdim 6418353358Sdim std::pair<CharUnits, CharUnits> TyInfo = { TySize, TyAlignForABI }; 6419296417Sdim return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, TyInfo, 6420296417Sdim SlotSize, /*AllowHigherAlign*/ true); 6421202379Srdivacky} 6422202379Srdivacky 6423210299Sed//===----------------------------------------------------------------------===// 6424239462Sdim// NVPTX ABI Implementation 6425221345Sdim//===----------------------------------------------------------------------===// 6426221345Sdim 6427221345Sdimnamespace { 6428221345Sdim 6429239462Sdimclass NVPTXABIInfo : public ABIInfo { 6430221345Sdimpublic: 6431239462Sdim NVPTXABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {} 6432221345Sdim 6433221345Sdim ABIArgInfo classifyReturnType(QualType RetTy) const; 6434221345Sdim ABIArgInfo classifyArgumentType(QualType Ty) const; 6435221345Sdim 6436276479Sdim void computeInfo(CGFunctionInfo &FI) const override; 6437296417Sdim Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 6438296417Sdim QualType Ty) const override; 6439221345Sdim}; 6440221345Sdim 6441239462Sdimclass NVPTXTargetCodeGenInfo : public TargetCodeGenInfo { 6442221345Sdimpublic: 6443239462Sdim NVPTXTargetCodeGenInfo(CodeGenTypes &CGT) 6444239462Sdim : TargetCodeGenInfo(new NVPTXABIInfo(CGT)) {} 6445276479Sdim 6446288943Sdim void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 6447341825Sdim CodeGen::CodeGenModule &M) const override; 6448341825Sdim bool shouldEmitStaticExternCAliases() const override; 6449327952Sdim 6450249423Sdimprivate: 6451276479Sdim // Adds a NamedMDNode with F, Name, and Operand as operands, and adds the 6452276479Sdim // resulting MDNode to the nvvm.annotations MDNode. 6453276479Sdim static void addNVVMMetadata(llvm::Function *F, StringRef Name, int Operand); 6454221345Sdim}; 6455221345Sdim 6456353358Sdim/// Checks if the type is unsupported directly by the current target. 6457353358Sdimstatic bool isUnsupportedType(ASTContext &Context, QualType T) { 6458353358Sdim if (!Context.getTargetInfo().hasFloat16Type() && T->isFloat16Type()) 6459353358Sdim return true; 6460353358Sdim if (!Context.getTargetInfo().hasFloat128Type() && 6461353358Sdim (T->isFloat128Type() || 6462353358Sdim (T->isRealFloatingType() && Context.getTypeSize(T) == 128))) 6463353358Sdim return true; 6464353358Sdim if (!Context.getTargetInfo().hasInt128Type() && T->isIntegerType() && 6465353358Sdim Context.getTypeSize(T) > 64) 6466353358Sdim return true; 6467353358Sdim if (const auto *AT = T->getAsArrayTypeUnsafe()) 6468353358Sdim return isUnsupportedType(Context, AT->getElementType()); 6469353358Sdim const auto *RT = T->getAs<RecordType>(); 6470353358Sdim if (!RT) 6471353358Sdim return false; 6472353358Sdim const RecordDecl *RD = RT->getDecl(); 6473353358Sdim 6474353358Sdim // If this is a C++ record, check the bases first. 6475353358Sdim if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) 6476353358Sdim for (const CXXBaseSpecifier &I : CXXRD->bases()) 6477353358Sdim if (isUnsupportedType(Context, I.getType())) 6478353358Sdim return true; 6479353358Sdim 6480353358Sdim for (const FieldDecl *I : RD->fields()) 6481353358Sdim if (isUnsupportedType(Context, I->getType())) 6482353358Sdim return true; 6483353358Sdim return false; 6484353358Sdim} 6485353358Sdim 6486353358Sdim/// Coerce the given type into an array with maximum allowed size of elements. 6487353358Sdimstatic ABIArgInfo coerceToIntArrayWithLimit(QualType Ty, ASTContext &Context, 6488353358Sdim llvm::LLVMContext &LLVMContext, 6489353358Sdim unsigned MaxSize) { 6490353358Sdim // Alignment and Size are measured in bits. 6491353358Sdim const uint64_t Size = Context.getTypeSize(Ty); 6492353358Sdim const uint64_t Alignment = Context.getTypeAlign(Ty); 6493353358Sdim const unsigned Div = std::min<unsigned>(MaxSize, Alignment); 6494353358Sdim llvm::Type *IntType = llvm::Type::getIntNTy(LLVMContext, Div); 6495353358Sdim const uint64_t NumElements = (Size + Div - 1) / Div; 6496353358Sdim return ABIArgInfo::getDirect(llvm::ArrayType::get(IntType, NumElements)); 6497353358Sdim} 6498353358Sdim 6499239462SdimABIArgInfo NVPTXABIInfo::classifyReturnType(QualType RetTy) const { 6500221345Sdim if (RetTy->isVoidType()) 6501221345Sdim return ABIArgInfo::getIgnore(); 6502261991Sdim 6503353358Sdim if (getContext().getLangOpts().OpenMP && 6504353358Sdim getContext().getLangOpts().OpenMPIsDevice && 6505353358Sdim isUnsupportedType(getContext(), RetTy)) 6506353358Sdim return coerceToIntArrayWithLimit(RetTy, getContext(), getVMContext(), 64); 6507353358Sdim 6508261991Sdim // note: this is different from default ABI 6509261991Sdim if (!RetTy->isScalarType()) 6510261991Sdim return ABIArgInfo::getDirect(); 6511261991Sdim 6512261991Sdim // Treat an enum type as its underlying type. 6513261991Sdim if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 6514261991Sdim RetTy = EnumTy->getDecl()->getIntegerType(); 6515261991Sdim 6516341825Sdim return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy) 6517341825Sdim : ABIArgInfo::getDirect()); 6518221345Sdim} 6519221345Sdim 6520239462SdimABIArgInfo NVPTXABIInfo::classifyArgumentType(QualType Ty) const { 6521261991Sdim // Treat an enum type as its underlying type. 6522261991Sdim if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 6523261991Sdim Ty = EnumTy->getDecl()->getIntegerType(); 6524221345Sdim 6525280031Sdim // Return aggregates type as indirect by value 6526280031Sdim if (isAggregateTypeForABI(Ty)) 6527296417Sdim return getNaturalAlignIndirect(Ty, /* byval */ true); 6528280031Sdim 6529341825Sdim return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty) 6530341825Sdim : ABIArgInfo::getDirect()); 6531221345Sdim} 6532221345Sdim 6533239462Sdimvoid NVPTXABIInfo::computeInfo(CGFunctionInfo &FI) const { 6534276479Sdim if (!getCXXABI().classifyReturnType(FI)) 6535276479Sdim FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 6536276479Sdim for (auto &I : FI.arguments()) 6537276479Sdim I.info = classifyArgumentType(I.type); 6538221345Sdim 6539221345Sdim // Always honor user-specified calling convention. 6540221345Sdim if (FI.getCallingConvention() != llvm::CallingConv::C) 6541221345Sdim return; 6542221345Sdim 6543249423Sdim FI.setEffectiveCallingConvention(getRuntimeCC()); 6544221345Sdim} 6545221345Sdim 6546296417SdimAddress NVPTXABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 6547296417Sdim QualType Ty) const { 6548239462Sdim llvm_unreachable("NVPTX does not support varargs"); 6549221345Sdim} 6550221345Sdim 6551327952Sdimvoid NVPTXTargetCodeGenInfo::setTargetAttributes( 6552341825Sdim const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const { 6553341825Sdim if (GV->isDeclaration()) 6554327952Sdim return; 6555296417Sdim const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D); 6556226633Sdim if (!FD) return; 6557226633Sdim 6558226633Sdim llvm::Function *F = cast<llvm::Function>(GV); 6559226633Sdim 6560226633Sdim // Perform special handling in OpenCL mode 6561234353Sdim if (M.getLangOpts().OpenCL) { 6562249423Sdim // Use OpenCL function attributes to check for kernel functions 6563226633Sdim // By default, all functions are device functions 6564226633Sdim if (FD->hasAttr<OpenCLKernelAttr>()) { 6565249423Sdim // OpenCL __kernel functions get kernel metadata 6566276479Sdim // Create !{<func-ref>, metadata !"kernel", i32 1} node 6567276479Sdim addNVVMMetadata(F, "kernel", 1); 6568226633Sdim // And kernel functions are not subject to inlining 6569249423Sdim F->addFnAttr(llvm::Attribute::NoInline); 6570226633Sdim } 6571226633Sdim } 6572226633Sdim 6573226633Sdim // Perform special handling in CUDA mode. 6574234353Sdim if (M.getLangOpts().CUDA) { 6575249423Sdim // CUDA __global__ functions get a kernel metadata entry. Since 6576226633Sdim // __global__ functions cannot be called from the device, we do not 6577226633Sdim // need to set the noinline attribute. 6578276479Sdim if (FD->hasAttr<CUDAGlobalAttr>()) { 6579276479Sdim // Create !{<func-ref>, metadata !"kernel", i32 1} node 6580276479Sdim addNVVMMetadata(F, "kernel", 1); 6581276479Sdim } 6582288943Sdim if (CUDALaunchBoundsAttr *Attr = FD->getAttr<CUDALaunchBoundsAttr>()) { 6583276479Sdim // Create !{<func-ref>, metadata !"maxntidx", i32 <val>} node 6584288943Sdim llvm::APSInt MaxThreads(32); 6585288943Sdim MaxThreads = Attr->getMaxThreads()->EvaluateKnownConstInt(M.getContext()); 6586288943Sdim if (MaxThreads > 0) 6587288943Sdim addNVVMMetadata(F, "maxntidx", MaxThreads.getExtValue()); 6588288943Sdim 6589288943Sdim // min blocks is an optional argument for CUDALaunchBoundsAttr. If it was 6590288943Sdim // not specified in __launch_bounds__ or if the user specified a 0 value, 6591288943Sdim // we don't have to add a PTX directive. 6592288943Sdim if (Attr->getMinBlocks()) { 6593288943Sdim llvm::APSInt MinBlocks(32); 6594288943Sdim MinBlocks = Attr->getMinBlocks()->EvaluateKnownConstInt(M.getContext()); 6595288943Sdim if (MinBlocks > 0) 6596288943Sdim // Create !{<func-ref>, metadata !"minctasm", i32 <val>} node 6597288943Sdim addNVVMMetadata(F, "minctasm", MinBlocks.getExtValue()); 6598276479Sdim } 6599276479Sdim } 6600226633Sdim } 6601221345Sdim} 6602221345Sdim 6603276479Sdimvoid NVPTXTargetCodeGenInfo::addNVVMMetadata(llvm::Function *F, StringRef Name, 6604276479Sdim int Operand) { 6605249423Sdim llvm::Module *M = F->getParent(); 6606249423Sdim llvm::LLVMContext &Ctx = M->getContext(); 6607249423Sdim 6608249423Sdim // Get "nvvm.annotations" metadata node 6609249423Sdim llvm::NamedMDNode *MD = M->getOrInsertNamedMetadata("nvvm.annotations"); 6610249423Sdim 6611280031Sdim llvm::Metadata *MDVals[] = { 6612280031Sdim llvm::ConstantAsMetadata::get(F), llvm::MDString::get(Ctx, Name), 6613280031Sdim llvm::ConstantAsMetadata::get( 6614280031Sdim llvm::ConstantInt::get(llvm::Type::getInt32Ty(Ctx), Operand))}; 6615249423Sdim // Append metadata to nvvm.annotations 6616249423Sdim MD->addOperand(llvm::MDNode::get(Ctx, MDVals)); 6617226633Sdim} 6618341825Sdim 6619341825Sdimbool NVPTXTargetCodeGenInfo::shouldEmitStaticExternCAliases() const { 6620341825Sdim return false; 6621249423Sdim} 6622341825Sdim} 6623249423Sdim 6624221345Sdim//===----------------------------------------------------------------------===// 6625251662Sdim// SystemZ ABI Implementation 6626251662Sdim//===----------------------------------------------------------------------===// 6627251662Sdim 6628251662Sdimnamespace { 6629251662Sdim 6630309124Sdimclass SystemZABIInfo : public SwiftABIInfo { 6631288943Sdim bool HasVector; 6632288943Sdim 6633251662Sdimpublic: 6634288943Sdim SystemZABIInfo(CodeGenTypes &CGT, bool HV) 6635309124Sdim : SwiftABIInfo(CGT), HasVector(HV) {} 6636251662Sdim 6637251662Sdim bool isPromotableIntegerType(QualType Ty) const; 6638251662Sdim bool isCompoundType(QualType Ty) const; 6639288943Sdim bool isVectorArgumentType(QualType Ty) const; 6640251662Sdim bool isFPArgumentType(QualType Ty) const; 6641288943Sdim QualType GetSingleElementType(QualType Ty) const; 6642251662Sdim 6643251662Sdim ABIArgInfo classifyReturnType(QualType RetTy) const; 6644251662Sdim ABIArgInfo classifyArgumentType(QualType ArgTy) const; 6645251662Sdim 6646276479Sdim void computeInfo(CGFunctionInfo &FI) const override { 6647276479Sdim if (!getCXXABI().classifyReturnType(FI)) 6648276479Sdim FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 6649276479Sdim for (auto &I : FI.arguments()) 6650276479Sdim I.info = classifyArgumentType(I.type); 6651251662Sdim } 6652251662Sdim 6653296417Sdim Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 6654296417Sdim QualType Ty) const override; 6655309124Sdim 6656341825Sdim bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars, 6657309124Sdim bool asReturnValue) const override { 6658309124Sdim return occupiesMoreThan(CGT, scalars, /*total*/ 4); 6659309124Sdim } 6660314564Sdim bool isSwiftErrorInRegister() const override { 6661327952Sdim return false; 6662314564Sdim } 6663251662Sdim}; 6664251662Sdim 6665251662Sdimclass SystemZTargetCodeGenInfo : public TargetCodeGenInfo { 6666251662Sdimpublic: 6667288943Sdim SystemZTargetCodeGenInfo(CodeGenTypes &CGT, bool HasVector) 6668288943Sdim : TargetCodeGenInfo(new SystemZABIInfo(CGT, HasVector)) {} 6669251662Sdim}; 6670251662Sdim 6671251662Sdim} 6672251662Sdim 6673251662Sdimbool SystemZABIInfo::isPromotableIntegerType(QualType Ty) const { 6674251662Sdim // Treat an enum type as its underlying type. 6675251662Sdim if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 6676251662Sdim Ty = EnumTy->getDecl()->getIntegerType(); 6677251662Sdim 6678251662Sdim // Promotable integer types are required to be promoted by the ABI. 6679251662Sdim if (Ty->isPromotableIntegerType()) 6680251662Sdim return true; 6681251662Sdim 6682251662Sdim // 32-bit values must also be promoted. 6683251662Sdim if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) 6684251662Sdim switch (BT->getKind()) { 6685251662Sdim case BuiltinType::Int: 6686251662Sdim case BuiltinType::UInt: 6687251662Sdim return true; 6688251662Sdim default: 6689251662Sdim return false; 6690251662Sdim } 6691251662Sdim return false; 6692251662Sdim} 6693251662Sdim 6694251662Sdimbool SystemZABIInfo::isCompoundType(QualType Ty) const { 6695288943Sdim return (Ty->isAnyComplexType() || 6696288943Sdim Ty->isVectorType() || 6697288943Sdim isAggregateTypeForABI(Ty)); 6698251662Sdim} 6699251662Sdim 6700288943Sdimbool SystemZABIInfo::isVectorArgumentType(QualType Ty) const { 6701288943Sdim return (HasVector && 6702288943Sdim Ty->isVectorType() && 6703288943Sdim getContext().getTypeSize(Ty) <= 128); 6704288943Sdim} 6705288943Sdim 6706251662Sdimbool SystemZABIInfo::isFPArgumentType(QualType Ty) const { 6707251662Sdim if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) 6708251662Sdim switch (BT->getKind()) { 6709251662Sdim case BuiltinType::Float: 6710251662Sdim case BuiltinType::Double: 6711251662Sdim return true; 6712251662Sdim default: 6713251662Sdim return false; 6714251662Sdim } 6715251662Sdim 6716288943Sdim return false; 6717288943Sdim} 6718288943Sdim 6719288943SdimQualType SystemZABIInfo::GetSingleElementType(QualType Ty) const { 6720251662Sdim if (const RecordType *RT = Ty->getAsStructureType()) { 6721251662Sdim const RecordDecl *RD = RT->getDecl(); 6722288943Sdim QualType Found; 6723251662Sdim 6724251662Sdim // If this is a C++ record, check the bases first. 6725251662Sdim if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) 6726276479Sdim for (const auto &I : CXXRD->bases()) { 6727276479Sdim QualType Base = I.getType(); 6728251662Sdim 6729251662Sdim // Empty bases don't affect things either way. 6730251662Sdim if (isEmptyRecord(getContext(), Base, true)) 6731251662Sdim continue; 6732251662Sdim 6733288943Sdim if (!Found.isNull()) 6734288943Sdim return Ty; 6735288943Sdim Found = GetSingleElementType(Base); 6736251662Sdim } 6737251662Sdim 6738251662Sdim // Check the fields. 6739276479Sdim for (const auto *FD : RD->fields()) { 6740288943Sdim // For compatibility with GCC, ignore empty bitfields in C++ mode. 6741251662Sdim // Unlike isSingleElementStruct(), empty structure and array fields 6742251662Sdim // do count. So do anonymous bitfields that aren't zero-sized. 6743288943Sdim if (getContext().getLangOpts().CPlusPlus && 6744341825Sdim FD->isZeroLengthBitField(getContext())) 6745288943Sdim continue; 6746251662Sdim 6747251662Sdim // Unlike isSingleElementStruct(), arrays do not count. 6748288943Sdim // Nested structures still do though. 6749288943Sdim if (!Found.isNull()) 6750288943Sdim return Ty; 6751288943Sdim Found = GetSingleElementType(FD->getType()); 6752251662Sdim } 6753251662Sdim 6754251662Sdim // Unlike isSingleElementStruct(), trailing padding is allowed. 6755251662Sdim // An 8-byte aligned struct s { float f; } is passed as a double. 6756288943Sdim if (!Found.isNull()) 6757288943Sdim return Found; 6758251662Sdim } 6759251662Sdim 6760288943Sdim return Ty; 6761251662Sdim} 6762251662Sdim 6763296417SdimAddress SystemZABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 6764296417Sdim QualType Ty) const { 6765251662Sdim // Assume that va_list type is correct; should be pointer to LLVM type: 6766251662Sdim // struct { 6767251662Sdim // i64 __gpr; 6768251662Sdim // i64 __fpr; 6769251662Sdim // i8 *__overflow_arg_area; 6770251662Sdim // i8 *__reg_save_area; 6771251662Sdim // }; 6772251662Sdim 6773288943Sdim // Every non-vector argument occupies 8 bytes and is passed by preference 6774288943Sdim // in either GPRs or FPRs. Vector arguments occupy 8 or 16 bytes and are 6775288943Sdim // always passed on the stack. 6776296417Sdim Ty = getContext().getCanonicalType(Ty); 6777296417Sdim auto TyInfo = getContext().getTypeInfoInChars(Ty); 6778288943Sdim llvm::Type *ArgTy = CGF.ConvertTypeForMem(Ty); 6779296417Sdim llvm::Type *DirectTy = ArgTy; 6780251662Sdim ABIArgInfo AI = classifyArgumentType(Ty); 6781251662Sdim bool IsIndirect = AI.isIndirect(); 6782288943Sdim bool InFPRs = false; 6783288943Sdim bool IsVector = false; 6784296417Sdim CharUnits UnpaddedSize; 6785296417Sdim CharUnits DirectAlign; 6786251662Sdim if (IsIndirect) { 6787296417Sdim DirectTy = llvm::PointerType::getUnqual(DirectTy); 6788296417Sdim UnpaddedSize = DirectAlign = CharUnits::fromQuantity(8); 6789288943Sdim } else { 6790288943Sdim if (AI.getCoerceToType()) 6791288943Sdim ArgTy = AI.getCoerceToType(); 6792288943Sdim InFPRs = ArgTy->isFloatTy() || ArgTy->isDoubleTy(); 6793288943Sdim IsVector = ArgTy->isVectorTy(); 6794296417Sdim UnpaddedSize = TyInfo.first; 6795296417Sdim DirectAlign = TyInfo.second; 6796288943Sdim } 6797296417Sdim CharUnits PaddedSize = CharUnits::fromQuantity(8); 6798296417Sdim if (IsVector && UnpaddedSize > PaddedSize) 6799296417Sdim PaddedSize = CharUnits::fromQuantity(16); 6800296417Sdim assert((UnpaddedSize <= PaddedSize) && "Invalid argument size."); 6801251662Sdim 6802296417Sdim CharUnits Padding = (PaddedSize - UnpaddedSize); 6803251662Sdim 6804288943Sdim llvm::Type *IndexTy = CGF.Int64Ty; 6805296417Sdim llvm::Value *PaddedSizeV = 6806296417Sdim llvm::ConstantInt::get(IndexTy, PaddedSize.getQuantity()); 6807288943Sdim 6808288943Sdim if (IsVector) { 6809288943Sdim // Work out the address of a vector argument on the stack. 6810288943Sdim // Vector arguments are always passed in the high bits of a 6811288943Sdim // single (8 byte) or double (16 byte) stack slot. 6812296417Sdim Address OverflowArgAreaPtr = 6813353358Sdim CGF.Builder.CreateStructGEP(VAListAddr, 2, "overflow_arg_area_ptr"); 6814296417Sdim Address OverflowArgArea = 6815296417Sdim Address(CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area"), 6816296417Sdim TyInfo.second); 6817296417Sdim Address MemAddr = 6818296417Sdim CGF.Builder.CreateElementBitCast(OverflowArgArea, DirectTy, "mem_addr"); 6819288943Sdim 6820288943Sdim // Update overflow_arg_area_ptr pointer 6821288943Sdim llvm::Value *NewOverflowArgArea = 6822296417Sdim CGF.Builder.CreateGEP(OverflowArgArea.getPointer(), PaddedSizeV, 6823296417Sdim "overflow_arg_area"); 6824288943Sdim CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr); 6825288943Sdim 6826288943Sdim return MemAddr; 6827288943Sdim } 6828288943Sdim 6829296417Sdim assert(PaddedSize.getQuantity() == 8); 6830296417Sdim 6831296417Sdim unsigned MaxRegs, RegCountField, RegSaveIndex; 6832296417Sdim CharUnits RegPadding; 6833251662Sdim if (InFPRs) { 6834251662Sdim MaxRegs = 4; // Maximum of 4 FPR arguments 6835251662Sdim RegCountField = 1; // __fpr 6836251662Sdim RegSaveIndex = 16; // save offset for f0 6837296417Sdim RegPadding = CharUnits(); // floats are passed in the high bits of an FPR 6838251662Sdim } else { 6839251662Sdim MaxRegs = 5; // Maximum of 5 GPR arguments 6840251662Sdim RegCountField = 0; // __gpr 6841251662Sdim RegSaveIndex = 2; // save offset for r2 6842251662Sdim RegPadding = Padding; // values are passed in the low bits of a GPR 6843251662Sdim } 6844251662Sdim 6845353358Sdim Address RegCountPtr = 6846353358Sdim CGF.Builder.CreateStructGEP(VAListAddr, RegCountField, "reg_count_ptr"); 6847251662Sdim llvm::Value *RegCount = CGF.Builder.CreateLoad(RegCountPtr, "reg_count"); 6848251662Sdim llvm::Value *MaxRegsV = llvm::ConstantInt::get(IndexTy, MaxRegs); 6849251662Sdim llvm::Value *InRegs = CGF.Builder.CreateICmpULT(RegCount, MaxRegsV, 6850276479Sdim "fits_in_regs"); 6851251662Sdim 6852251662Sdim llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg"); 6853251662Sdim llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem"); 6854251662Sdim llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end"); 6855251662Sdim CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock); 6856251662Sdim 6857251662Sdim // Emit code to load the value if it was passed in registers. 6858251662Sdim CGF.EmitBlock(InRegBlock); 6859251662Sdim 6860251662Sdim // Work out the address of an argument register. 6861251662Sdim llvm::Value *ScaledRegCount = 6862251662Sdim CGF.Builder.CreateMul(RegCount, PaddedSizeV, "scaled_reg_count"); 6863251662Sdim llvm::Value *RegBase = 6864296417Sdim llvm::ConstantInt::get(IndexTy, RegSaveIndex * PaddedSize.getQuantity() 6865296417Sdim + RegPadding.getQuantity()); 6866251662Sdim llvm::Value *RegOffset = 6867251662Sdim CGF.Builder.CreateAdd(ScaledRegCount, RegBase, "reg_offset"); 6868296417Sdim Address RegSaveAreaPtr = 6869353358Sdim CGF.Builder.CreateStructGEP(VAListAddr, 3, "reg_save_area_ptr"); 6870251662Sdim llvm::Value *RegSaveArea = 6871251662Sdim CGF.Builder.CreateLoad(RegSaveAreaPtr, "reg_save_area"); 6872296417Sdim Address RawRegAddr(CGF.Builder.CreateGEP(RegSaveArea, RegOffset, 6873296417Sdim "raw_reg_addr"), 6874296417Sdim PaddedSize); 6875296417Sdim Address RegAddr = 6876296417Sdim CGF.Builder.CreateElementBitCast(RawRegAddr, DirectTy, "reg_addr"); 6877251662Sdim 6878251662Sdim // Update the register count 6879251662Sdim llvm::Value *One = llvm::ConstantInt::get(IndexTy, 1); 6880251662Sdim llvm::Value *NewRegCount = 6881251662Sdim CGF.Builder.CreateAdd(RegCount, One, "reg_count"); 6882251662Sdim CGF.Builder.CreateStore(NewRegCount, RegCountPtr); 6883251662Sdim CGF.EmitBranch(ContBlock); 6884251662Sdim 6885251662Sdim // Emit code to load the value if it was passed in memory. 6886251662Sdim CGF.EmitBlock(InMemBlock); 6887251662Sdim 6888251662Sdim // Work out the address of a stack argument. 6889353358Sdim Address OverflowArgAreaPtr = 6890353358Sdim CGF.Builder.CreateStructGEP(VAListAddr, 2, "overflow_arg_area_ptr"); 6891296417Sdim Address OverflowArgArea = 6892296417Sdim Address(CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area"), 6893296417Sdim PaddedSize); 6894296417Sdim Address RawMemAddr = 6895296417Sdim CGF.Builder.CreateConstByteGEP(OverflowArgArea, Padding, "raw_mem_addr"); 6896296417Sdim Address MemAddr = 6897296417Sdim CGF.Builder.CreateElementBitCast(RawMemAddr, DirectTy, "mem_addr"); 6898251662Sdim 6899251662Sdim // Update overflow_arg_area_ptr pointer 6900251662Sdim llvm::Value *NewOverflowArgArea = 6901296417Sdim CGF.Builder.CreateGEP(OverflowArgArea.getPointer(), PaddedSizeV, 6902296417Sdim "overflow_arg_area"); 6903251662Sdim CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr); 6904251662Sdim CGF.EmitBranch(ContBlock); 6905251662Sdim 6906251662Sdim // Return the appropriate result. 6907251662Sdim CGF.EmitBlock(ContBlock); 6908296417Sdim Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock, 6909296417Sdim MemAddr, InMemBlock, "va_arg.addr"); 6910251662Sdim 6911251662Sdim if (IsIndirect) 6912296417Sdim ResAddr = Address(CGF.Builder.CreateLoad(ResAddr, "indirect_arg"), 6913296417Sdim TyInfo.second); 6914251662Sdim 6915251662Sdim return ResAddr; 6916251662Sdim} 6917251662Sdim 6918251662SdimABIArgInfo SystemZABIInfo::classifyReturnType(QualType RetTy) const { 6919251662Sdim if (RetTy->isVoidType()) 6920251662Sdim return ABIArgInfo::getIgnore(); 6921288943Sdim if (isVectorArgumentType(RetTy)) 6922288943Sdim return ABIArgInfo::getDirect(); 6923251662Sdim if (isCompoundType(RetTy) || getContext().getTypeSize(RetTy) > 64) 6924296417Sdim return getNaturalAlignIndirect(RetTy); 6925341825Sdim return (isPromotableIntegerType(RetTy) ? ABIArgInfo::getExtend(RetTy) 6926341825Sdim : ABIArgInfo::getDirect()); 6927251662Sdim} 6928251662Sdim 6929251662SdimABIArgInfo SystemZABIInfo::classifyArgumentType(QualType Ty) const { 6930251662Sdim // Handle the generic C++ ABI. 6931261991Sdim if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) 6932296417Sdim return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory); 6933251662Sdim 6934251662Sdim // Integers and enums are extended to full register width. 6935251662Sdim if (isPromotableIntegerType(Ty)) 6936341825Sdim return ABIArgInfo::getExtend(Ty); 6937251662Sdim 6938288943Sdim // Handle vector types and vector-like structure types. Note that 6939288943Sdim // as opposed to float-like structure types, we do not allow any 6940288943Sdim // padding for vector-like structures, so verify the sizes match. 6941288943Sdim uint64_t Size = getContext().getTypeSize(Ty); 6942288943Sdim QualType SingleElementTy = GetSingleElementType(Ty); 6943288943Sdim if (isVectorArgumentType(SingleElementTy) && 6944288943Sdim getContext().getTypeSize(SingleElementTy) == Size) 6945288943Sdim return ABIArgInfo::getDirect(CGT.ConvertType(SingleElementTy)); 6946288943Sdim 6947251662Sdim // Values that are not 1, 2, 4 or 8 bytes in size are passed indirectly. 6948251662Sdim if (Size != 8 && Size != 16 && Size != 32 && Size != 64) 6949296417Sdim return getNaturalAlignIndirect(Ty, /*ByVal=*/false); 6950251662Sdim 6951251662Sdim // Handle small structures. 6952251662Sdim if (const RecordType *RT = Ty->getAs<RecordType>()) { 6953251662Sdim // Structures with flexible arrays have variable length, so really 6954251662Sdim // fail the size test above. 6955251662Sdim const RecordDecl *RD = RT->getDecl(); 6956251662Sdim if (RD->hasFlexibleArrayMember()) 6957296417Sdim return getNaturalAlignIndirect(Ty, /*ByVal=*/false); 6958251662Sdim 6959251662Sdim // The structure is passed as an unextended integer, a float, or a double. 6960251662Sdim llvm::Type *PassTy; 6961288943Sdim if (isFPArgumentType(SingleElementTy)) { 6962251662Sdim assert(Size == 32 || Size == 64); 6963251662Sdim if (Size == 32) 6964251662Sdim PassTy = llvm::Type::getFloatTy(getVMContext()); 6965251662Sdim else 6966251662Sdim PassTy = llvm::Type::getDoubleTy(getVMContext()); 6967251662Sdim } else 6968251662Sdim PassTy = llvm::IntegerType::get(getVMContext(), Size); 6969251662Sdim return ABIArgInfo::getDirect(PassTy); 6970251662Sdim } 6971251662Sdim 6972251662Sdim // Non-structure compounds are passed indirectly. 6973251662Sdim if (isCompoundType(Ty)) 6974296417Sdim return getNaturalAlignIndirect(Ty, /*ByVal=*/false); 6975251662Sdim 6976276479Sdim return ABIArgInfo::getDirect(nullptr); 6977251662Sdim} 6978251662Sdim 6979251662Sdim//===----------------------------------------------------------------------===// 6980202379Srdivacky// MSP430 ABI Implementation 6981210299Sed//===----------------------------------------------------------------------===// 6982202379Srdivacky 6983202379Srdivackynamespace { 6984202379Srdivacky 6985202379Srdivackyclass MSP430TargetCodeGenInfo : public TargetCodeGenInfo { 6986202379Srdivackypublic: 6987212904Sdim MSP430TargetCodeGenInfo(CodeGenTypes &CGT) 6988212904Sdim : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {} 6989288943Sdim void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 6990341825Sdim CodeGen::CodeGenModule &M) const override; 6991202379Srdivacky}; 6992202379Srdivacky 6993202379Srdivacky} 6994202379Srdivacky 6995327952Sdimvoid MSP430TargetCodeGenInfo::setTargetAttributes( 6996341825Sdim const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const { 6997341825Sdim if (GV->isDeclaration()) 6998327952Sdim return; 6999296417Sdim if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) { 7000344779Sdim const auto *InterruptAttr = FD->getAttr<MSP430InterruptAttr>(); 7001344779Sdim if (!InterruptAttr) 7002344779Sdim return; 7003202379Srdivacky 7004344779Sdim // Handle 'interrupt' attribute: 7005344779Sdim llvm::Function *F = cast<llvm::Function>(GV); 7006202379Srdivacky 7007344779Sdim // Step 1: Set ISR calling convention. 7008344779Sdim F->setCallingConv(llvm::CallingConv::MSP430_INTR); 7009202379Srdivacky 7010344779Sdim // Step 2: Add attributes goodness. 7011344779Sdim F->addFnAttr(llvm::Attribute::NoInline); 7012344779Sdim F->addFnAttr("interrupt", llvm::utostr(InterruptAttr->getNumber())); 7013202379Srdivacky } 7014202379Srdivacky} 7015202379Srdivacky 7016210299Sed//===----------------------------------------------------------------------===// 7017208600Srdivacky// MIPS ABI Implementation. This works for both little-endian and 7018208600Srdivacky// big-endian variants. 7019210299Sed//===----------------------------------------------------------------------===// 7020210299Sed 7021208600Srdivackynamespace { 7022223017Sdimclass MipsABIInfo : public ABIInfo { 7023234353Sdim bool IsO32; 7024239462Sdim unsigned MinABIStackAlignInBytes, StackAlignInBytes; 7025239462Sdim void CoerceToIntArgs(uint64_t TySize, 7026261991Sdim SmallVectorImpl<llvm::Type *> &ArgList) const; 7027239462Sdim llvm::Type* HandleAggregates(QualType Ty, uint64_t TySize) const; 7028234353Sdim llvm::Type* returnAggregateInRegs(QualType RetTy, uint64_t Size) const; 7029234353Sdim llvm::Type* getPaddingType(uint64_t Align, uint64_t Offset) const; 7030223017Sdimpublic: 7031234353Sdim MipsABIInfo(CodeGenTypes &CGT, bool _IsO32) : 7032239462Sdim ABIInfo(CGT), IsO32(_IsO32), MinABIStackAlignInBytes(IsO32 ? 4 : 8), 7033239462Sdim StackAlignInBytes(IsO32 ? 8 : 16) {} 7034223017Sdim 7035223017Sdim ABIArgInfo classifyReturnType(QualType RetTy) const; 7036234353Sdim ABIArgInfo classifyArgumentType(QualType RetTy, uint64_t &Offset) const; 7037276479Sdim void computeInfo(CGFunctionInfo &FI) const override; 7038296417Sdim Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 7039296417Sdim QualType Ty) const override; 7040341825Sdim ABIArgInfo extendType(QualType Ty) const; 7041223017Sdim}; 7042223017Sdim 7043208600Srdivackyclass MIPSTargetCodeGenInfo : public TargetCodeGenInfo { 7044226633Sdim unsigned SizeOfUnwindException; 7045208600Srdivackypublic: 7046234353Sdim MIPSTargetCodeGenInfo(CodeGenTypes &CGT, bool IsO32) 7047234353Sdim : TargetCodeGenInfo(new MipsABIInfo(CGT, IsO32)), 7048234353Sdim SizeOfUnwindException(IsO32 ? 24 : 32) {} 7049208600Srdivacky 7050276479Sdim int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override { 7051208600Srdivacky return 29; 7052208600Srdivacky } 7053208600Srdivacky 7054288943Sdim void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 7055341825Sdim CodeGen::CodeGenModule &CGM) const override { 7056296417Sdim const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D); 7057249423Sdim if (!FD) return; 7058249423Sdim llvm::Function *Fn = cast<llvm::Function>(GV); 7059327952Sdim 7060327952Sdim if (FD->hasAttr<MipsLongCallAttr>()) 7061327952Sdim Fn->addFnAttr("long-call"); 7062327952Sdim else if (FD->hasAttr<MipsShortCallAttr>()) 7063327952Sdim Fn->addFnAttr("short-call"); 7064327952Sdim 7065327952Sdim // Other attributes do not have a meaning for declarations. 7066341825Sdim if (GV->isDeclaration()) 7067327952Sdim return; 7068327952Sdim 7069249423Sdim if (FD->hasAttr<Mips16Attr>()) { 7070249423Sdim Fn->addFnAttr("mips16"); 7071249423Sdim } 7072249423Sdim else if (FD->hasAttr<NoMips16Attr>()) { 7073249423Sdim Fn->addFnAttr("nomips16"); 7074249423Sdim } 7075296417Sdim 7076321369Sdim if (FD->hasAttr<MicroMipsAttr>()) 7077321369Sdim Fn->addFnAttr("micromips"); 7078321369Sdim else if (FD->hasAttr<NoMicroMipsAttr>()) 7079321369Sdim Fn->addFnAttr("nomicromips"); 7080321369Sdim 7081296417Sdim const MipsInterruptAttr *Attr = FD->getAttr<MipsInterruptAttr>(); 7082296417Sdim if (!Attr) 7083296417Sdim return; 7084296417Sdim 7085296417Sdim const char *Kind; 7086296417Sdim switch (Attr->getInterrupt()) { 7087296417Sdim case MipsInterruptAttr::eic: Kind = "eic"; break; 7088296417Sdim case MipsInterruptAttr::sw0: Kind = "sw0"; break; 7089296417Sdim case MipsInterruptAttr::sw1: Kind = "sw1"; break; 7090296417Sdim case MipsInterruptAttr::hw0: Kind = "hw0"; break; 7091296417Sdim case MipsInterruptAttr::hw1: Kind = "hw1"; break; 7092296417Sdim case MipsInterruptAttr::hw2: Kind = "hw2"; break; 7093296417Sdim case MipsInterruptAttr::hw3: Kind = "hw3"; break; 7094296417Sdim case MipsInterruptAttr::hw4: Kind = "hw4"; break; 7095296417Sdim case MipsInterruptAttr::hw5: Kind = "hw5"; break; 7096296417Sdim } 7097296417Sdim 7098296417Sdim Fn->addFnAttr("interrupt", Kind); 7099296417Sdim 7100249423Sdim } 7101249423Sdim 7102208600Srdivacky bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 7103276479Sdim llvm::Value *Address) const override; 7104226633Sdim 7105276479Sdim unsigned getSizeOfUnwindException() const override { 7106226633Sdim return SizeOfUnwindException; 7107226633Sdim } 7108208600Srdivacky}; 7109208600Srdivacky} 7110208600Srdivacky 7111288943Sdimvoid MipsABIInfo::CoerceToIntArgs( 7112288943Sdim uint64_t TySize, SmallVectorImpl<llvm::Type *> &ArgList) const { 7113239462Sdim llvm::IntegerType *IntTy = 7114239462Sdim llvm::IntegerType::get(getVMContext(), MinABIStackAlignInBytes * 8); 7115239462Sdim 7116239462Sdim // Add (TySize / MinABIStackAlignInBytes) args of IntTy. 7117239462Sdim for (unsigned N = TySize / (MinABIStackAlignInBytes * 8); N; --N) 7118239462Sdim ArgList.push_back(IntTy); 7119239462Sdim 7120239462Sdim // If necessary, add one more integer type to ArgList. 7121239462Sdim unsigned R = TySize % (MinABIStackAlignInBytes * 8); 7122239462Sdim 7123239462Sdim if (R) 7124239462Sdim ArgList.push_back(llvm::IntegerType::get(getVMContext(), R)); 7125239462Sdim} 7126239462Sdim 7127234353Sdim// In N32/64, an aligned double precision floating point field is passed in 7128234353Sdim// a register. 7129239462Sdimllvm::Type* MipsABIInfo::HandleAggregates(QualType Ty, uint64_t TySize) const { 7130239462Sdim SmallVector<llvm::Type*, 8> ArgList, IntArgList; 7131234353Sdim 7132239462Sdim if (IsO32) { 7133239462Sdim CoerceToIntArgs(TySize, ArgList); 7134239462Sdim return llvm::StructType::get(getVMContext(), ArgList); 7135239462Sdim } 7136239462Sdim 7137234353Sdim if (Ty->isComplexType()) 7138234353Sdim return CGT.ConvertType(Ty); 7139234353Sdim 7140234353Sdim const RecordType *RT = Ty->getAs<RecordType>(); 7141234353Sdim 7142239462Sdim // Unions/vectors are passed in integer registers. 7143239462Sdim if (!RT || !RT->isStructureOrClassType()) { 7144239462Sdim CoerceToIntArgs(TySize, ArgList); 7145239462Sdim return llvm::StructType::get(getVMContext(), ArgList); 7146239462Sdim } 7147234353Sdim 7148234353Sdim const RecordDecl *RD = RT->getDecl(); 7149234353Sdim const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD); 7150239462Sdim assert(!(TySize % 8) && "Size of structure must be multiple of 8."); 7151288943Sdim 7152234353Sdim uint64_t LastOffset = 0; 7153234353Sdim unsigned idx = 0; 7154234353Sdim llvm::IntegerType *I64 = llvm::IntegerType::get(getVMContext(), 64); 7155234353Sdim 7156234353Sdim // Iterate over fields in the struct/class and check if there are any aligned 7157234353Sdim // double fields. 7158234353Sdim for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 7159234353Sdim i != e; ++i, ++idx) { 7160239462Sdim const QualType Ty = i->getType(); 7161234353Sdim const BuiltinType *BT = Ty->getAs<BuiltinType>(); 7162234353Sdim 7163234353Sdim if (!BT || BT->getKind() != BuiltinType::Double) 7164234353Sdim continue; 7165234353Sdim 7166234353Sdim uint64_t Offset = Layout.getFieldOffset(idx); 7167234353Sdim if (Offset % 64) // Ignore doubles that are not aligned. 7168234353Sdim continue; 7169234353Sdim 7170234353Sdim // Add ((Offset - LastOffset) / 64) args of type i64. 7171234353Sdim for (unsigned j = (Offset - LastOffset) / 64; j > 0; --j) 7172234353Sdim ArgList.push_back(I64); 7173234353Sdim 7174234353Sdim // Add double type. 7175234353Sdim ArgList.push_back(llvm::Type::getDoubleTy(getVMContext())); 7176234353Sdim LastOffset = Offset + 64; 7177234353Sdim } 7178234353Sdim 7179239462Sdim CoerceToIntArgs(TySize - LastOffset, IntArgList); 7180239462Sdim ArgList.append(IntArgList.begin(), IntArgList.end()); 7181234353Sdim 7182234353Sdim return llvm::StructType::get(getVMContext(), ArgList); 7183234353Sdim} 7184234353Sdim 7185261991Sdimllvm::Type *MipsABIInfo::getPaddingType(uint64_t OrigOffset, 7186261991Sdim uint64_t Offset) const { 7187261991Sdim if (OrigOffset + MinABIStackAlignInBytes > Offset) 7188276479Sdim return nullptr; 7189234353Sdim 7190261991Sdim return llvm::IntegerType::get(getVMContext(), (Offset - OrigOffset) * 8); 7191234353Sdim} 7192234353Sdim 7193234353SdimABIArgInfo 7194234353SdimMipsABIInfo::classifyArgumentType(QualType Ty, uint64_t &Offset) const { 7195280031Sdim Ty = useFirstFieldIfTransparentUnion(Ty); 7196280031Sdim 7197234353Sdim uint64_t OrigOffset = Offset; 7198239462Sdim uint64_t TySize = getContext().getTypeSize(Ty); 7199234353Sdim uint64_t Align = getContext().getTypeAlign(Ty) / 8; 7200234353Sdim 7201239462Sdim Align = std::min(std::max(Align, (uint64_t)MinABIStackAlignInBytes), 7202239462Sdim (uint64_t)StackAlignInBytes); 7203309124Sdim unsigned CurrOffset = llvm::alignTo(Offset, Align); 7204309124Sdim Offset = CurrOffset + llvm::alignTo(TySize, Align * 8) / 8; 7205239462Sdim 7206239462Sdim if (isAggregateTypeForABI(Ty) || Ty->isVectorType()) { 7207223017Sdim // Ignore empty aggregates. 7208234353Sdim if (TySize == 0) 7209223017Sdim return ABIArgInfo::getIgnore(); 7210223017Sdim 7211261991Sdim if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) { 7212239462Sdim Offset = OrigOffset + MinABIStackAlignInBytes; 7213296417Sdim return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory); 7214234353Sdim } 7215226633Sdim 7216239462Sdim // If we have reached here, aggregates are passed directly by coercing to 7217239462Sdim // another structure type. Padding is inserted if the offset of the 7218239462Sdim // aggregate is unaligned. 7219277320Sdim ABIArgInfo ArgInfo = 7220277320Sdim ABIArgInfo::getDirect(HandleAggregates(Ty, TySize), 0, 7221277320Sdim getPaddingType(OrigOffset, CurrOffset)); 7222277320Sdim ArgInfo.setInReg(true); 7223277320Sdim return ArgInfo; 7224223017Sdim } 7225223017Sdim 7226223017Sdim // Treat an enum type as its underlying type. 7227223017Sdim if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 7228223017Sdim Ty = EnumTy->getDecl()->getIntegerType(); 7229223017Sdim 7230277320Sdim // All integral types are promoted to the GPR width. 7231277320Sdim if (Ty->isIntegralOrEnumerationType()) 7232341825Sdim return extendType(Ty); 7233234353Sdim 7234261991Sdim return ABIArgInfo::getDirect( 7235276479Sdim nullptr, 0, IsO32 ? nullptr : getPaddingType(OrigOffset, CurrOffset)); 7236223017Sdim} 7237223017Sdim 7238234353Sdimllvm::Type* 7239234353SdimMipsABIInfo::returnAggregateInRegs(QualType RetTy, uint64_t Size) const { 7240234353Sdim const RecordType *RT = RetTy->getAs<RecordType>(); 7241239462Sdim SmallVector<llvm::Type*, 8> RTList; 7242234353Sdim 7243234353Sdim if (RT && RT->isStructureOrClassType()) { 7244234353Sdim const RecordDecl *RD = RT->getDecl(); 7245234353Sdim const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD); 7246234353Sdim unsigned FieldCnt = Layout.getFieldCount(); 7247234353Sdim 7248234353Sdim // N32/64 returns struct/classes in floating point registers if the 7249234353Sdim // following conditions are met: 7250234353Sdim // 1. The size of the struct/class is no larger than 128-bit. 7251234353Sdim // 2. The struct/class has one or two fields all of which are floating 7252234353Sdim // point types. 7253288943Sdim // 3. The offset of the first field is zero (this follows what gcc does). 7254234353Sdim // 7255234353Sdim // Any other composite results are returned in integer registers. 7256234353Sdim // 7257234353Sdim if (FieldCnt && (FieldCnt <= 2) && !Layout.getFieldOffset(0)) { 7258234353Sdim RecordDecl::field_iterator b = RD->field_begin(), e = RD->field_end(); 7259234353Sdim for (; b != e; ++b) { 7260239462Sdim const BuiltinType *BT = b->getType()->getAs<BuiltinType>(); 7261234353Sdim 7262234353Sdim if (!BT || !BT->isFloatingPoint()) 7263234353Sdim break; 7264234353Sdim 7265239462Sdim RTList.push_back(CGT.ConvertType(b->getType())); 7266234353Sdim } 7267234353Sdim 7268234353Sdim if (b == e) 7269234353Sdim return llvm::StructType::get(getVMContext(), RTList, 7270234353Sdim RD->hasAttr<PackedAttr>()); 7271234353Sdim 7272234353Sdim RTList.clear(); 7273234353Sdim } 7274234353Sdim } 7275234353Sdim 7276239462Sdim CoerceToIntArgs(Size, RTList); 7277234353Sdim return llvm::StructType::get(getVMContext(), RTList); 7278234353Sdim} 7279234353Sdim 7280223017SdimABIArgInfo MipsABIInfo::classifyReturnType(QualType RetTy) const { 7281234353Sdim uint64_t Size = getContext().getTypeSize(RetTy); 7282234353Sdim 7283277320Sdim if (RetTy->isVoidType()) 7284223017Sdim return ABIArgInfo::getIgnore(); 7285223017Sdim 7286277320Sdim // O32 doesn't treat zero-sized structs differently from other structs. 7287277320Sdim // However, N32/N64 ignores zero sized return values. 7288277320Sdim if (!IsO32 && Size == 0) 7289277320Sdim return ABIArgInfo::getIgnore(); 7290277320Sdim 7291239462Sdim if (isAggregateTypeForABI(RetTy) || RetTy->isVectorType()) { 7292234353Sdim if (Size <= 128) { 7293234353Sdim if (RetTy->isAnyComplexType()) 7294234353Sdim return ABIArgInfo::getDirect(); 7295223017Sdim 7296277320Sdim // O32 returns integer vectors in registers and N32/N64 returns all small 7297280031Sdim // aggregates in registers. 7298277320Sdim if (!IsO32 || 7299277320Sdim (RetTy->isVectorType() && !RetTy->hasFloatingRepresentation())) { 7300277320Sdim ABIArgInfo ArgInfo = 7301277320Sdim ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size)); 7302277320Sdim ArgInfo.setInReg(true); 7303277320Sdim return ArgInfo; 7304277320Sdim } 7305234353Sdim } 7306234353Sdim 7307296417Sdim return getNaturalAlignIndirect(RetTy); 7308223017Sdim } 7309223017Sdim 7310223017Sdim // Treat an enum type as its underlying type. 7311223017Sdim if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 7312223017Sdim RetTy = EnumTy->getDecl()->getIntegerType(); 7313223017Sdim 7314341825Sdim if (RetTy->isPromotableIntegerType()) 7315341825Sdim return ABIArgInfo::getExtend(RetTy); 7316341825Sdim 7317341825Sdim if ((RetTy->isUnsignedIntegerOrEnumerationType() || 7318341825Sdim RetTy->isSignedIntegerOrEnumerationType()) && Size == 32 && !IsO32) 7319341825Sdim return ABIArgInfo::getSignExtend(RetTy); 7320341825Sdim 7321341825Sdim return ABIArgInfo::getDirect(); 7322223017Sdim} 7323223017Sdim 7324223017Sdimvoid MipsABIInfo::computeInfo(CGFunctionInfo &FI) const { 7325234353Sdim ABIArgInfo &RetInfo = FI.getReturnInfo(); 7326276479Sdim if (!getCXXABI().classifyReturnType(FI)) 7327276479Sdim RetInfo = classifyReturnType(FI.getReturnType()); 7328234353Sdim 7329288943Sdim // Check if a pointer to an aggregate is passed as a hidden argument. 7330239462Sdim uint64_t Offset = RetInfo.isIndirect() ? MinABIStackAlignInBytes : 0; 7331234353Sdim 7332276479Sdim for (auto &I : FI.arguments()) 7333276479Sdim I.info = classifyArgumentType(I.type, Offset); 7334223017Sdim} 7335223017Sdim 7336296417SdimAddress MipsABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 7337296417Sdim QualType OrigTy) const { 7338296417Sdim QualType Ty = OrigTy; 7339277320Sdim 7340280031Sdim // Integer arguments are promoted to 32-bit on O32 and 64-bit on N32/N64. 7341280031Sdim // Pointers are also promoted in the same way but this only matters for N32. 7342277320Sdim unsigned SlotSizeInBits = IsO32 ? 32 : 64; 7343280031Sdim unsigned PtrWidth = getTarget().getPointerWidth(0); 7344296417Sdim bool DidPromote = false; 7345280031Sdim if ((Ty->isIntegerType() && 7346296417Sdim getContext().getIntWidth(Ty) < SlotSizeInBits) || 7347280031Sdim (Ty->isPointerType() && PtrWidth < SlotSizeInBits)) { 7348296417Sdim DidPromote = true; 7349296417Sdim Ty = getContext().getIntTypeForBitwidth(SlotSizeInBits, 7350296417Sdim Ty->isSignedIntegerType()); 7351277320Sdim } 7352288943Sdim 7353296417Sdim auto TyInfo = getContext().getTypeInfoInChars(Ty); 7354226633Sdim 7355296417Sdim // The alignment of things in the argument area is never larger than 7356296417Sdim // StackAlignInBytes. 7357296417Sdim TyInfo.second = 7358296417Sdim std::min(TyInfo.second, CharUnits::fromQuantity(StackAlignInBytes)); 7359296417Sdim 7360296417Sdim // MinABIStackAlignInBytes is the size of argument slots on the stack. 7361296417Sdim CharUnits ArgSlotSize = CharUnits::fromQuantity(MinABIStackAlignInBytes); 7362296417Sdim 7363296417Sdim Address Addr = emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false, 7364296417Sdim TyInfo, ArgSlotSize, /*AllowHigherAlign*/ true); 7365296417Sdim 7366296417Sdim 7367296417Sdim // If there was a promotion, "unpromote" into a temporary. 7368296417Sdim // TODO: can we just use a pointer into a subset of the original slot? 7369296417Sdim if (DidPromote) { 7370296417Sdim Address Temp = CGF.CreateMemTemp(OrigTy, "vaarg.promotion-temp"); 7371296417Sdim llvm::Value *Promoted = CGF.Builder.CreateLoad(Addr); 7372296417Sdim 7373296417Sdim // Truncate down to the right width. 7374296417Sdim llvm::Type *IntTy = (OrigTy->isIntegerType() ? Temp.getElementType() 7375296417Sdim : CGF.IntPtrTy); 7376296417Sdim llvm::Value *V = CGF.Builder.CreateTrunc(Promoted, IntTy); 7377296417Sdim if (OrigTy->isPointerType()) 7378296417Sdim V = CGF.Builder.CreateIntToPtr(V, Temp.getElementType()); 7379296417Sdim 7380296417Sdim CGF.Builder.CreateStore(V, Temp); 7381296417Sdim Addr = Temp; 7382226633Sdim } 7383226633Sdim 7384296417Sdim return Addr; 7385223017Sdim} 7386223017Sdim 7387341825SdimABIArgInfo MipsABIInfo::extendType(QualType Ty) const { 7388288943Sdim int TySize = getContext().getTypeSize(Ty); 7389288943Sdim 7390288943Sdim // MIPS64 ABI requires unsigned 32 bit integers to be sign extended. 7391288943Sdim if (Ty->isUnsignedIntegerOrEnumerationType() && TySize == 32) 7392341825Sdim return ABIArgInfo::getSignExtend(Ty); 7393288943Sdim 7394341825Sdim return ABIArgInfo::getExtend(Ty); 7395288943Sdim} 7396288943Sdim 7397208600Srdivackybool 7398208600SrdivackyMIPSTargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 7399208600Srdivacky llvm::Value *Address) const { 7400208600Srdivacky // This information comes from gcc's implementation, which seems to 7401208600Srdivacky // as canonical as it gets. 7402208600Srdivacky 7403208600Srdivacky // Everything on MIPS is 4 bytes. Double-precision FP registers 7404208600Srdivacky // are aliased to pairs of single-precision FP registers. 7405234353Sdim llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4); 7406208600Srdivacky 7407208600Srdivacky // 0-31 are the general purpose registers, $0 - $31. 7408208600Srdivacky // 32-63 are the floating-point registers, $f0 - $f31. 7409208600Srdivacky // 64 and 65 are the multiply/divide registers, $hi and $lo. 7410208600Srdivacky // 66 is the (notional, I think) register for signal-handler return. 7411234353Sdim AssignToArrayRange(CGF.Builder, Address, Four8, 0, 65); 7412208600Srdivacky 7413208600Srdivacky // 67-74 are the floating-point status registers, $fcc0 - $fcc7. 7414208600Srdivacky // They are one bit wide and ignored here. 7415208600Srdivacky 7416208600Srdivacky // 80-111 are the coprocessor 0 registers, $c0r0 - $c0r31. 7417208600Srdivacky // (coprocessor 1 is the FP unit) 7418208600Srdivacky // 112-143 are the coprocessor 2 registers, $c2r0 - $c2r31. 7419208600Srdivacky // 144-175 are the coprocessor 3 registers, $c3r0 - $c3r31. 7420208600Srdivacky // 176-181 are the DSP accumulator registers. 7421234353Sdim AssignToArrayRange(CGF.Builder, Address, Four8, 80, 181); 7422208600Srdivacky return false; 7423208600Srdivacky} 7424208600Srdivacky 7425226633Sdim//===----------------------------------------------------------------------===// 7426321369Sdim// AVR ABI Implementation. 7427321369Sdim//===----------------------------------------------------------------------===// 7428321369Sdim 7429321369Sdimnamespace { 7430321369Sdimclass AVRTargetCodeGenInfo : public TargetCodeGenInfo { 7431321369Sdimpublic: 7432321369Sdim AVRTargetCodeGenInfo(CodeGenTypes &CGT) 7433321369Sdim : TargetCodeGenInfo(new DefaultABIInfo(CGT)) { } 7434321369Sdim 7435321369Sdim void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 7436341825Sdim CodeGen::CodeGenModule &CGM) const override { 7437341825Sdim if (GV->isDeclaration()) 7438327952Sdim return; 7439321369Sdim const auto *FD = dyn_cast_or_null<FunctionDecl>(D); 7440321369Sdim if (!FD) return; 7441321369Sdim auto *Fn = cast<llvm::Function>(GV); 7442321369Sdim 7443321369Sdim if (FD->getAttr<AVRInterruptAttr>()) 7444321369Sdim Fn->addFnAttr("interrupt"); 7445321369Sdim 7446321369Sdim if (FD->getAttr<AVRSignalAttr>()) 7447321369Sdim Fn->addFnAttr("signal"); 7448321369Sdim } 7449321369Sdim}; 7450321369Sdim} 7451321369Sdim 7452321369Sdim//===----------------------------------------------------------------------===// 7453226633Sdim// TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults. 7454288943Sdim// Currently subclassed only to implement custom OpenCL C function attribute 7455226633Sdim// handling. 7456226633Sdim//===----------------------------------------------------------------------===// 7457208600Srdivacky 7458226633Sdimnamespace { 7459226633Sdim 7460226633Sdimclass TCETargetCodeGenInfo : public DefaultTargetCodeGenInfo { 7461226633Sdimpublic: 7462226633Sdim TCETargetCodeGenInfo(CodeGenTypes &CGT) 7463226633Sdim : DefaultTargetCodeGenInfo(CGT) {} 7464226633Sdim 7465288943Sdim void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 7466341825Sdim CodeGen::CodeGenModule &M) const override; 7467226633Sdim}; 7468226633Sdim 7469288943Sdimvoid TCETargetCodeGenInfo::setTargetAttributes( 7470341825Sdim const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const { 7471341825Sdim if (GV->isDeclaration()) 7472327952Sdim return; 7473296417Sdim const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D); 7474226633Sdim if (!FD) return; 7475226633Sdim 7476226633Sdim llvm::Function *F = cast<llvm::Function>(GV); 7477288943Sdim 7478234353Sdim if (M.getLangOpts().OpenCL) { 7479226633Sdim if (FD->hasAttr<OpenCLKernelAttr>()) { 7480226633Sdim // OpenCL C Kernel functions are not subject to inlining 7481249423Sdim F->addFnAttr(llvm::Attribute::NoInline); 7482276479Sdim const ReqdWorkGroupSizeAttr *Attr = FD->getAttr<ReqdWorkGroupSizeAttr>(); 7483276479Sdim if (Attr) { 7484226633Sdim // Convert the reqd_work_group_size() attributes to metadata. 7485226633Sdim llvm::LLVMContext &Context = F->getContext(); 7486288943Sdim llvm::NamedMDNode *OpenCLMetadata = 7487288943Sdim M.getModule().getOrInsertNamedMetadata( 7488288943Sdim "opencl.kernel_wg_size_info"); 7489226633Sdim 7490280031Sdim SmallVector<llvm::Metadata *, 5> Operands; 7491280031Sdim Operands.push_back(llvm::ConstantAsMetadata::get(F)); 7492226633Sdim 7493280031Sdim Operands.push_back( 7494280031Sdim llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue( 7495280031Sdim M.Int32Ty, llvm::APInt(32, Attr->getXDim())))); 7496280031Sdim Operands.push_back( 7497280031Sdim llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue( 7498280031Sdim M.Int32Ty, llvm::APInt(32, Attr->getYDim())))); 7499280031Sdim Operands.push_back( 7500280031Sdim llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue( 7501280031Sdim M.Int32Ty, llvm::APInt(32, Attr->getZDim())))); 7502226633Sdim 7503288943Sdim // Add a boolean constant operand for "required" (true) or "hint" 7504288943Sdim // (false) for implementing the work_group_size_hint attr later. 7505288943Sdim // Currently always true as the hint is not yet implemented. 7506280031Sdim Operands.push_back( 7507280031Sdim llvm::ConstantAsMetadata::get(llvm::ConstantInt::getTrue(Context))); 7508226633Sdim OpenCLMetadata->addOperand(llvm::MDNode::get(Context, Operands)); 7509226633Sdim } 7510226633Sdim } 7511226633Sdim } 7512226633Sdim} 7513226633Sdim 7514226633Sdim} 7515226633Sdim 7516234353Sdim//===----------------------------------------------------------------------===// 7517234353Sdim// Hexagon ABI Implementation 7518234353Sdim//===----------------------------------------------------------------------===// 7519234353Sdim 7520234353Sdimnamespace { 7521234353Sdim 7522234353Sdimclass HexagonABIInfo : public ABIInfo { 7523234353Sdim 7524234353Sdim 7525234353Sdimpublic: 7526234353Sdim HexagonABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {} 7527234353Sdim 7528234353Sdimprivate: 7529234353Sdim 7530234353Sdim ABIArgInfo classifyReturnType(QualType RetTy) const; 7531234353Sdim ABIArgInfo classifyArgumentType(QualType RetTy) const; 7532234353Sdim 7533276479Sdim void computeInfo(CGFunctionInfo &FI) const override; 7534234353Sdim 7535296417Sdim Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 7536296417Sdim QualType Ty) const override; 7537234353Sdim}; 7538234353Sdim 7539234353Sdimclass HexagonTargetCodeGenInfo : public TargetCodeGenInfo { 7540234353Sdimpublic: 7541234353Sdim HexagonTargetCodeGenInfo(CodeGenTypes &CGT) 7542234353Sdim :TargetCodeGenInfo(new HexagonABIInfo(CGT)) {} 7543234353Sdim 7544276479Sdim int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override { 7545234353Sdim return 29; 7546234353Sdim } 7547234353Sdim}; 7548234353Sdim 7549234353Sdim} 7550234353Sdim 7551234353Sdimvoid HexagonABIInfo::computeInfo(CGFunctionInfo &FI) const { 7552276479Sdim if (!getCXXABI().classifyReturnType(FI)) 7553276479Sdim FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 7554276479Sdim for (auto &I : FI.arguments()) 7555276479Sdim I.info = classifyArgumentType(I.type); 7556234353Sdim} 7557234353Sdim 7558234353SdimABIArgInfo HexagonABIInfo::classifyArgumentType(QualType Ty) const { 7559234353Sdim if (!isAggregateTypeForABI(Ty)) { 7560234353Sdim // Treat an enum type as its underlying type. 7561234353Sdim if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 7562234353Sdim Ty = EnumTy->getDecl()->getIntegerType(); 7563234353Sdim 7564341825Sdim return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty) 7565341825Sdim : ABIArgInfo::getDirect()); 7566234353Sdim } 7567234353Sdim 7568321369Sdim if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) 7569321369Sdim return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory); 7570321369Sdim 7571234353Sdim // Ignore empty records. 7572234353Sdim if (isEmptyRecord(getContext(), Ty, true)) 7573234353Sdim return ABIArgInfo::getIgnore(); 7574234353Sdim 7575234353Sdim uint64_t Size = getContext().getTypeSize(Ty); 7576234353Sdim if (Size > 64) 7577296417Sdim return getNaturalAlignIndirect(Ty, /*ByVal=*/true); 7578234353Sdim // Pass in the smallest viable integer type. 7579234353Sdim else if (Size > 32) 7580234353Sdim return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext())); 7581234353Sdim else if (Size > 16) 7582234353Sdim return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 7583234353Sdim else if (Size > 8) 7584234353Sdim return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 7585234353Sdim else 7586234353Sdim return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); 7587234353Sdim} 7588234353Sdim 7589234353SdimABIArgInfo HexagonABIInfo::classifyReturnType(QualType RetTy) const { 7590234353Sdim if (RetTy->isVoidType()) 7591234353Sdim return ABIArgInfo::getIgnore(); 7592234353Sdim 7593234353Sdim // Large vector types should be returned via memory. 7594234353Sdim if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 64) 7595296417Sdim return getNaturalAlignIndirect(RetTy); 7596234353Sdim 7597234353Sdim if (!isAggregateTypeForABI(RetTy)) { 7598234353Sdim // Treat an enum type as its underlying type. 7599234353Sdim if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 7600234353Sdim RetTy = EnumTy->getDecl()->getIntegerType(); 7601234353Sdim 7602341825Sdim return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy) 7603341825Sdim : ABIArgInfo::getDirect()); 7604234353Sdim } 7605234353Sdim 7606234353Sdim if (isEmptyRecord(getContext(), RetTy, true)) 7607234353Sdim return ABIArgInfo::getIgnore(); 7608234353Sdim 7609234353Sdim // Aggregates <= 8 bytes are returned in r0; other aggregates 7610234353Sdim // are returned indirectly. 7611234353Sdim uint64_t Size = getContext().getTypeSize(RetTy); 7612234353Sdim if (Size <= 64) { 7613234353Sdim // Return in the smallest viable integer type. 7614234353Sdim if (Size <= 8) 7615234353Sdim return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); 7616234353Sdim if (Size <= 16) 7617234353Sdim return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 7618234353Sdim if (Size <= 32) 7619234353Sdim return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 7620234353Sdim return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext())); 7621234353Sdim } 7622234353Sdim 7623296417Sdim return getNaturalAlignIndirect(RetTy, /*ByVal=*/true); 7624234353Sdim} 7625234353Sdim 7626296417SdimAddress HexagonABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 7627296417Sdim QualType Ty) const { 7628296417Sdim // FIXME: Someone needs to audit that this handle alignment correctly. 7629296417Sdim return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false, 7630296417Sdim getContext().getTypeInfoInChars(Ty), 7631296417Sdim CharUnits::fromQuantity(4), 7632296417Sdim /*AllowHigherAlign*/ true); 7633234353Sdim} 7634234353Sdim 7635280031Sdim//===----------------------------------------------------------------------===// 7636309124Sdim// Lanai ABI Implementation 7637309124Sdim//===----------------------------------------------------------------------===// 7638309124Sdim 7639309124Sdimnamespace { 7640309124Sdimclass LanaiABIInfo : public DefaultABIInfo { 7641309124Sdimpublic: 7642309124Sdim LanaiABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {} 7643309124Sdim 7644309124Sdim bool shouldUseInReg(QualType Ty, CCState &State) const; 7645309124Sdim 7646309124Sdim void computeInfo(CGFunctionInfo &FI) const override { 7647360784Sdim CCState State(FI); 7648309124Sdim // Lanai uses 4 registers to pass arguments unless the function has the 7649309124Sdim // regparm attribute set. 7650309124Sdim if (FI.getHasRegParm()) { 7651309124Sdim State.FreeRegs = FI.getRegParm(); 7652309124Sdim } else { 7653309124Sdim State.FreeRegs = 4; 7654309124Sdim } 7655309124Sdim 7656309124Sdim if (!getCXXABI().classifyReturnType(FI)) 7657309124Sdim FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 7658309124Sdim for (auto &I : FI.arguments()) 7659309124Sdim I.info = classifyArgumentType(I.type, State); 7660309124Sdim } 7661309124Sdim 7662309124Sdim ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const; 7663309124Sdim ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const; 7664309124Sdim}; 7665309124Sdim} // end anonymous namespace 7666309124Sdim 7667309124Sdimbool LanaiABIInfo::shouldUseInReg(QualType Ty, CCState &State) const { 7668309124Sdim unsigned Size = getContext().getTypeSize(Ty); 7669309124Sdim unsigned SizeInRegs = llvm::alignTo(Size, 32U) / 32U; 7670309124Sdim 7671309124Sdim if (SizeInRegs == 0) 7672309124Sdim return false; 7673309124Sdim 7674309124Sdim if (SizeInRegs > State.FreeRegs) { 7675309124Sdim State.FreeRegs = 0; 7676309124Sdim return false; 7677309124Sdim } 7678309124Sdim 7679309124Sdim State.FreeRegs -= SizeInRegs; 7680309124Sdim 7681309124Sdim return true; 7682309124Sdim} 7683309124Sdim 7684309124SdimABIArgInfo LanaiABIInfo::getIndirectResult(QualType Ty, bool ByVal, 7685309124Sdim CCState &State) const { 7686309124Sdim if (!ByVal) { 7687309124Sdim if (State.FreeRegs) { 7688309124Sdim --State.FreeRegs; // Non-byval indirects just use one pointer. 7689309124Sdim return getNaturalAlignIndirectInReg(Ty); 7690309124Sdim } 7691309124Sdim return getNaturalAlignIndirect(Ty, false); 7692309124Sdim } 7693309124Sdim 7694309124Sdim // Compute the byval alignment. 7695309124Sdim const unsigned MinABIStackAlignInBytes = 4; 7696309124Sdim unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8; 7697309124Sdim return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true, 7698309124Sdim /*Realign=*/TypeAlign > 7699309124Sdim MinABIStackAlignInBytes); 7700309124Sdim} 7701309124Sdim 7702309124SdimABIArgInfo LanaiABIInfo::classifyArgumentType(QualType Ty, 7703309124Sdim CCState &State) const { 7704309124Sdim // Check with the C++ ABI first. 7705309124Sdim const RecordType *RT = Ty->getAs<RecordType>(); 7706309124Sdim if (RT) { 7707309124Sdim CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI()); 7708309124Sdim if (RAA == CGCXXABI::RAA_Indirect) { 7709309124Sdim return getIndirectResult(Ty, /*ByVal=*/false, State); 7710309124Sdim } else if (RAA == CGCXXABI::RAA_DirectInMemory) { 7711309124Sdim return getNaturalAlignIndirect(Ty, /*ByRef=*/true); 7712309124Sdim } 7713309124Sdim } 7714309124Sdim 7715309124Sdim if (isAggregateTypeForABI(Ty)) { 7716309124Sdim // Structures with flexible arrays are always indirect. 7717309124Sdim if (RT && RT->getDecl()->hasFlexibleArrayMember()) 7718309124Sdim return getIndirectResult(Ty, /*ByVal=*/true, State); 7719309124Sdim 7720309124Sdim // Ignore empty structs/unions. 7721309124Sdim if (isEmptyRecord(getContext(), Ty, true)) 7722309124Sdim return ABIArgInfo::getIgnore(); 7723309124Sdim 7724309124Sdim llvm::LLVMContext &LLVMContext = getVMContext(); 7725309124Sdim unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32; 7726309124Sdim if (SizeInRegs <= State.FreeRegs) { 7727309124Sdim llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext); 7728309124Sdim SmallVector<llvm::Type *, 3> Elements(SizeInRegs, Int32); 7729309124Sdim llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements); 7730309124Sdim State.FreeRegs -= SizeInRegs; 7731309124Sdim return ABIArgInfo::getDirectInReg(Result); 7732309124Sdim } else { 7733309124Sdim State.FreeRegs = 0; 7734309124Sdim } 7735309124Sdim return getIndirectResult(Ty, true, State); 7736309124Sdim } 7737309124Sdim 7738309124Sdim // Treat an enum type as its underlying type. 7739309124Sdim if (const auto *EnumTy = Ty->getAs<EnumType>()) 7740309124Sdim Ty = EnumTy->getDecl()->getIntegerType(); 7741309124Sdim 7742309124Sdim bool InReg = shouldUseInReg(Ty, State); 7743309124Sdim if (Ty->isPromotableIntegerType()) { 7744309124Sdim if (InReg) 7745309124Sdim return ABIArgInfo::getDirectInReg(); 7746341825Sdim return ABIArgInfo::getExtend(Ty); 7747309124Sdim } 7748309124Sdim if (InReg) 7749309124Sdim return ABIArgInfo::getDirectInReg(); 7750309124Sdim return ABIArgInfo::getDirect(); 7751309124Sdim} 7752309124Sdim 7753309124Sdimnamespace { 7754309124Sdimclass LanaiTargetCodeGenInfo : public TargetCodeGenInfo { 7755309124Sdimpublic: 7756309124Sdim LanaiTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT) 7757309124Sdim : TargetCodeGenInfo(new LanaiABIInfo(CGT)) {} 7758309124Sdim}; 7759309124Sdim} 7760309124Sdim 7761309124Sdim//===----------------------------------------------------------------------===// 7762280031Sdim// AMDGPU ABI Implementation 7763280031Sdim//===----------------------------------------------------------------------===// 7764234353Sdim 7765280031Sdimnamespace { 7766280031Sdim 7767314564Sdimclass AMDGPUABIInfo final : public DefaultABIInfo { 7768327952Sdimprivate: 7769327952Sdim static const unsigned MaxNumRegsForArgsRet = 16; 7770327952Sdim 7771327952Sdim unsigned numRegsForType(QualType Ty) const; 7772327952Sdim 7773327952Sdim bool isHomogeneousAggregateBaseType(QualType Ty) const override; 7774327952Sdim bool isHomogeneousAggregateSmallEnough(const Type *Base, 7775327952Sdim uint64_t Members) const override; 7776327952Sdim 7777360784Sdim // Coerce HIP pointer arguments from generic pointers to global ones. 7778360784Sdim llvm::Type *coerceKernelArgumentType(llvm::Type *Ty, unsigned FromAS, 7779360784Sdim unsigned ToAS) const { 7780360784Sdim // Structure types. 7781360784Sdim if (auto STy = dyn_cast<llvm::StructType>(Ty)) { 7782360784Sdim SmallVector<llvm::Type *, 8> EltTys; 7783360784Sdim bool Changed = false; 7784360784Sdim for (auto T : STy->elements()) { 7785360784Sdim auto NT = coerceKernelArgumentType(T, FromAS, ToAS); 7786360784Sdim EltTys.push_back(NT); 7787360784Sdim Changed |= (NT != T); 7788360784Sdim } 7789360784Sdim // Skip if there is no change in element types. 7790360784Sdim if (!Changed) 7791360784Sdim return STy; 7792360784Sdim if (STy->hasName()) 7793360784Sdim return llvm::StructType::create( 7794360784Sdim EltTys, (STy->getName() + ".coerce").str(), STy->isPacked()); 7795360784Sdim return llvm::StructType::get(getVMContext(), EltTys, STy->isPacked()); 7796360784Sdim } 7797360784Sdim // Arrary types. 7798360784Sdim if (auto ATy = dyn_cast<llvm::ArrayType>(Ty)) { 7799360784Sdim auto T = ATy->getElementType(); 7800360784Sdim auto NT = coerceKernelArgumentType(T, FromAS, ToAS); 7801360784Sdim // Skip if there is no change in that element type. 7802360784Sdim if (NT == T) 7803360784Sdim return ATy; 7804360784Sdim return llvm::ArrayType::get(NT, ATy->getNumElements()); 7805360784Sdim } 7806360784Sdim // Single value types. 7807360784Sdim if (Ty->isPointerTy() && Ty->getPointerAddressSpace() == FromAS) 7808360784Sdim return llvm::PointerType::get( 7809360784Sdim cast<llvm::PointerType>(Ty)->getElementType(), ToAS); 7810360784Sdim return Ty; 7811360784Sdim } 7812360784Sdim 7813314564Sdimpublic: 7814327952Sdim explicit AMDGPUABIInfo(CodeGen::CodeGenTypes &CGT) : 7815327952Sdim DefaultABIInfo(CGT) {} 7816314564Sdim 7817327952Sdim ABIArgInfo classifyReturnType(QualType RetTy) const; 7818327952Sdim ABIArgInfo classifyKernelArgumentType(QualType Ty) const; 7819327952Sdim ABIArgInfo classifyArgumentType(QualType Ty, unsigned &NumRegsLeft) const; 7820314564Sdim 7821314564Sdim void computeInfo(CGFunctionInfo &FI) const override; 7822360784Sdim Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 7823360784Sdim QualType Ty) const override; 7824314564Sdim}; 7825314564Sdim 7826327952Sdimbool AMDGPUABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const { 7827327952Sdim return true; 7828327952Sdim} 7829327952Sdim 7830327952Sdimbool AMDGPUABIInfo::isHomogeneousAggregateSmallEnough( 7831327952Sdim const Type *Base, uint64_t Members) const { 7832327952Sdim uint32_t NumRegs = (getContext().getTypeSize(Base) + 31) / 32; 7833327952Sdim 7834327952Sdim // Homogeneous Aggregates may occupy at most 16 registers. 7835327952Sdim return Members * NumRegs <= MaxNumRegsForArgsRet; 7836327952Sdim} 7837327952Sdim 7838327952Sdim/// Estimate number of registers the type will use when passed in registers. 7839327952Sdimunsigned AMDGPUABIInfo::numRegsForType(QualType Ty) const { 7840327952Sdim unsigned NumRegs = 0; 7841327952Sdim 7842327952Sdim if (const VectorType *VT = Ty->getAs<VectorType>()) { 7843327952Sdim // Compute from the number of elements. The reported size is based on the 7844327952Sdim // in-memory size, which includes the padding 4th element for 3-vectors. 7845327952Sdim QualType EltTy = VT->getElementType(); 7846327952Sdim unsigned EltSize = getContext().getTypeSize(EltTy); 7847327952Sdim 7848327952Sdim // 16-bit element vectors should be passed as packed. 7849327952Sdim if (EltSize == 16) 7850327952Sdim return (VT->getNumElements() + 1) / 2; 7851327952Sdim 7852327952Sdim unsigned EltNumRegs = (EltSize + 31) / 32; 7853327952Sdim return EltNumRegs * VT->getNumElements(); 7854327952Sdim } 7855327952Sdim 7856327952Sdim if (const RecordType *RT = Ty->getAs<RecordType>()) { 7857327952Sdim const RecordDecl *RD = RT->getDecl(); 7858327952Sdim assert(!RD->hasFlexibleArrayMember()); 7859327952Sdim 7860327952Sdim for (const FieldDecl *Field : RD->fields()) { 7861327952Sdim QualType FieldTy = Field->getType(); 7862327952Sdim NumRegs += numRegsForType(FieldTy); 7863327952Sdim } 7864327952Sdim 7865327952Sdim return NumRegs; 7866327952Sdim } 7867327952Sdim 7868327952Sdim return (getContext().getTypeSize(Ty) + 31) / 32; 7869327952Sdim} 7870327952Sdim 7871314564Sdimvoid AMDGPUABIInfo::computeInfo(CGFunctionInfo &FI) const { 7872327952Sdim llvm::CallingConv::ID CC = FI.getCallingConvention(); 7873327952Sdim 7874314564Sdim if (!getCXXABI().classifyReturnType(FI)) 7875314564Sdim FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 7876314564Sdim 7877327952Sdim unsigned NumRegsLeft = MaxNumRegsForArgsRet; 7878327952Sdim for (auto &Arg : FI.arguments()) { 7879327952Sdim if (CC == llvm::CallingConv::AMDGPU_KERNEL) { 7880327952Sdim Arg.info = classifyKernelArgumentType(Arg.type); 7881327952Sdim } else { 7882327952Sdim Arg.info = classifyArgumentType(Arg.type, NumRegsLeft); 7883327952Sdim } 7884327952Sdim } 7885314564Sdim} 7886314564Sdim 7887360784SdimAddress AMDGPUABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 7888360784Sdim QualType Ty) const { 7889360784Sdim llvm_unreachable("AMDGPU does not support varargs"); 7890360784Sdim} 7891360784Sdim 7892327952SdimABIArgInfo AMDGPUABIInfo::classifyReturnType(QualType RetTy) const { 7893327952Sdim if (isAggregateTypeForABI(RetTy)) { 7894327952Sdim // Records with non-trivial destructors/copy-constructors should not be 7895327952Sdim // returned by value. 7896327952Sdim if (!getRecordArgABI(RetTy, getCXXABI())) { 7897327952Sdim // Ignore empty structs/unions. 7898327952Sdim if (isEmptyRecord(getContext(), RetTy, true)) 7899327952Sdim return ABIArgInfo::getIgnore(); 7900327952Sdim 7901327952Sdim // Lower single-element structs to just return a regular value. 7902327952Sdim if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext())) 7903327952Sdim return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0))); 7904327952Sdim 7905327952Sdim if (const RecordType *RT = RetTy->getAs<RecordType>()) { 7906327952Sdim const RecordDecl *RD = RT->getDecl(); 7907327952Sdim if (RD->hasFlexibleArrayMember()) 7908327952Sdim return DefaultABIInfo::classifyReturnType(RetTy); 7909327952Sdim } 7910327952Sdim 7911327952Sdim // Pack aggregates <= 4 bytes into single VGPR or pair. 7912327952Sdim uint64_t Size = getContext().getTypeSize(RetTy); 7913327952Sdim if (Size <= 16) 7914327952Sdim return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 7915327952Sdim 7916327952Sdim if (Size <= 32) 7917327952Sdim return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 7918327952Sdim 7919327952Sdim if (Size <= 64) { 7920327952Sdim llvm::Type *I32Ty = llvm::Type::getInt32Ty(getVMContext()); 7921327952Sdim return ABIArgInfo::getDirect(llvm::ArrayType::get(I32Ty, 2)); 7922327952Sdim } 7923327952Sdim 7924327952Sdim if (numRegsForType(RetTy) <= MaxNumRegsForArgsRet) 7925327952Sdim return ABIArgInfo::getDirect(); 7926327952Sdim } 7927314564Sdim } 7928314564Sdim 7929327952Sdim // Otherwise just do the default thing. 7930327952Sdim return DefaultABIInfo::classifyReturnType(RetTy); 7931327952Sdim} 7932327952Sdim 7933327952Sdim/// For kernels all parameters are really passed in a special buffer. It doesn't 7934327952Sdim/// make sense to pass anything byval, so everything must be direct. 7935327952SdimABIArgInfo AMDGPUABIInfo::classifyKernelArgumentType(QualType Ty) const { 7936327952Sdim Ty = useFirstFieldIfTransparentUnion(Ty); 7937327952Sdim 7938327952Sdim // TODO: Can we omit empty structs? 7939327952Sdim 7940360784Sdim llvm::Type *LTy = nullptr; 7941327952Sdim if (const Type *SeltTy = isSingleElementStruct(Ty, getContext())) 7942360784Sdim LTy = CGT.ConvertType(QualType(SeltTy, 0)); 7943314564Sdim 7944360784Sdim if (getContext().getLangOpts().HIP) { 7945360784Sdim if (!LTy) 7946360784Sdim LTy = CGT.ConvertType(Ty); 7947360784Sdim LTy = coerceKernelArgumentType( 7948360784Sdim LTy, /*FromAS=*/getContext().getTargetAddressSpace(LangAS::Default), 7949360784Sdim /*ToAS=*/getContext().getTargetAddressSpace(LangAS::cuda_device)); 7950360784Sdim } 7951360784Sdim 7952314564Sdim // If we set CanBeFlattened to true, CodeGen will expand the struct to its 7953314564Sdim // individual elements, which confuses the Clover OpenCL backend; therefore we 7954314564Sdim // have to set it to false here. Other args of getDirect() are just defaults. 7955360784Sdim return ABIArgInfo::getDirect(LTy, 0, nullptr, false); 7956314564Sdim} 7957314564Sdim 7958327952SdimABIArgInfo AMDGPUABIInfo::classifyArgumentType(QualType Ty, 7959327952Sdim unsigned &NumRegsLeft) const { 7960327952Sdim assert(NumRegsLeft <= MaxNumRegsForArgsRet && "register estimate underflow"); 7961327952Sdim 7962327952Sdim Ty = useFirstFieldIfTransparentUnion(Ty); 7963327952Sdim 7964327952Sdim if (isAggregateTypeForABI(Ty)) { 7965327952Sdim // Records with non-trivial destructors/copy-constructors should not be 7966327952Sdim // passed by value. 7967327952Sdim if (auto RAA = getRecordArgABI(Ty, getCXXABI())) 7968327952Sdim return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory); 7969327952Sdim 7970327952Sdim // Ignore empty structs/unions. 7971327952Sdim if (isEmptyRecord(getContext(), Ty, true)) 7972327952Sdim return ABIArgInfo::getIgnore(); 7973327952Sdim 7974327952Sdim // Lower single-element structs to just pass a regular value. TODO: We 7975327952Sdim // could do reasonable-size multiple-element structs too, using getExpand(), 7976327952Sdim // though watch out for things like bitfields. 7977327952Sdim if (const Type *SeltTy = isSingleElementStruct(Ty, getContext())) 7978327952Sdim return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0))); 7979327952Sdim 7980327952Sdim if (const RecordType *RT = Ty->getAs<RecordType>()) { 7981327952Sdim const RecordDecl *RD = RT->getDecl(); 7982327952Sdim if (RD->hasFlexibleArrayMember()) 7983327952Sdim return DefaultABIInfo::classifyArgumentType(Ty); 7984327952Sdim } 7985327952Sdim 7986327952Sdim // Pack aggregates <= 8 bytes into single VGPR or pair. 7987327952Sdim uint64_t Size = getContext().getTypeSize(Ty); 7988327952Sdim if (Size <= 64) { 7989327952Sdim unsigned NumRegs = (Size + 31) / 32; 7990327952Sdim NumRegsLeft -= std::min(NumRegsLeft, NumRegs); 7991327952Sdim 7992327952Sdim if (Size <= 16) 7993327952Sdim return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 7994327952Sdim 7995327952Sdim if (Size <= 32) 7996327952Sdim return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 7997327952Sdim 7998327952Sdim // XXX: Should this be i64 instead, and should the limit increase? 7999327952Sdim llvm::Type *I32Ty = llvm::Type::getInt32Ty(getVMContext()); 8000327952Sdim return ABIArgInfo::getDirect(llvm::ArrayType::get(I32Ty, 2)); 8001327952Sdim } 8002327952Sdim 8003327952Sdim if (NumRegsLeft > 0) { 8004327952Sdim unsigned NumRegs = numRegsForType(Ty); 8005327952Sdim if (NumRegsLeft >= NumRegs) { 8006327952Sdim NumRegsLeft -= NumRegs; 8007327952Sdim return ABIArgInfo::getDirect(); 8008327952Sdim } 8009327952Sdim } 8010327952Sdim } 8011327952Sdim 8012327952Sdim // Otherwise just do the default thing. 8013327952Sdim ABIArgInfo ArgInfo = DefaultABIInfo::classifyArgumentType(Ty); 8014327952Sdim if (!ArgInfo.isIndirect()) { 8015327952Sdim unsigned NumRegs = numRegsForType(Ty); 8016327952Sdim NumRegsLeft -= std::min(NumRegs, NumRegsLeft); 8017327952Sdim } 8018327952Sdim 8019327952Sdim return ArgInfo; 8020327952Sdim} 8021327952Sdim 8022280031Sdimclass AMDGPUTargetCodeGenInfo : public TargetCodeGenInfo { 8023280031Sdimpublic: 8024280031Sdim AMDGPUTargetCodeGenInfo(CodeGenTypes &CGT) 8025314564Sdim : TargetCodeGenInfo(new AMDGPUABIInfo(CGT)) {} 8026288943Sdim void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 8027341825Sdim CodeGen::CodeGenModule &M) const override; 8028309124Sdim unsigned getOpenCLKernelCallingConv() const override; 8029314564Sdim 8030314564Sdim llvm::Constant *getNullPointer(const CodeGen::CodeGenModule &CGM, 8031314564Sdim llvm::PointerType *T, QualType QT) const override; 8032321369Sdim 8033327952Sdim LangAS getASTAllocaAddressSpace() const override { 8034327952Sdim return getLangASFromTargetAS( 8035327952Sdim getABIInfo().getDataLayout().getAllocaAddrSpace()); 8036321369Sdim } 8037327952Sdim LangAS getGlobalVarAddressSpace(CodeGenModule &CGM, 8038327952Sdim const VarDecl *D) const override; 8039353358Sdim llvm::SyncScope::ID getLLVMSyncScopeID(const LangOptions &LangOpts, 8040353358Sdim SyncScope Scope, 8041353358Sdim llvm::AtomicOrdering Ordering, 8042353358Sdim llvm::LLVMContext &Ctx) const override; 8043327952Sdim llvm::Function * 8044327952Sdim createEnqueuedBlockKernel(CodeGenFunction &CGF, 8045327952Sdim llvm::Function *BlockInvokeFunc, 8046327952Sdim llvm::Value *BlockLiteral) const override; 8047341825Sdim bool shouldEmitStaticExternCAliases() const override; 8048341825Sdim void setCUDAKernelCallingConvention(const FunctionType *&FT) const override; 8049280031Sdim}; 8050280031Sdim} 8051280031Sdim 8052353358Sdimstatic bool requiresAMDGPUProtectedVisibility(const Decl *D, 8053353358Sdim llvm::GlobalValue *GV) { 8054353358Sdim if (GV->getVisibility() != llvm::GlobalValue::HiddenVisibility) 8055353358Sdim return false; 8056353358Sdim 8057353358Sdim return D->hasAttr<OpenCLKernelAttr>() || 8058353358Sdim (isa<FunctionDecl>(D) && D->hasAttr<CUDAGlobalAttr>()) || 8059353358Sdim (isa<VarDecl>(D) && 8060353358Sdim (D->hasAttr<CUDADeviceAttr>() || D->hasAttr<CUDAConstantAttr>() || 8061353358Sdim D->hasAttr<HIPPinnedShadowAttr>())); 8062353358Sdim} 8063353358Sdim 8064353358Sdimstatic bool requiresAMDGPUDefaultVisibility(const Decl *D, 8065353358Sdim llvm::GlobalValue *GV) { 8066353358Sdim if (GV->getVisibility() != llvm::GlobalValue::HiddenVisibility) 8067353358Sdim return false; 8068353358Sdim 8069353358Sdim return isa<VarDecl>(D) && D->hasAttr<HIPPinnedShadowAttr>(); 8070353358Sdim} 8071353358Sdim 8072288943Sdimvoid AMDGPUTargetCodeGenInfo::setTargetAttributes( 8073341825Sdim const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const { 8074353358Sdim if (requiresAMDGPUDefaultVisibility(D, GV)) { 8075353358Sdim GV->setVisibility(llvm::GlobalValue::DefaultVisibility); 8076353358Sdim GV->setDSOLocal(false); 8077353358Sdim } else if (requiresAMDGPUProtectedVisibility(D, GV)) { 8078353358Sdim GV->setVisibility(llvm::GlobalValue::ProtectedVisibility); 8079353358Sdim GV->setDSOLocal(true); 8080353358Sdim } 8081353358Sdim 8082341825Sdim if (GV->isDeclaration()) 8083327952Sdim return; 8084296417Sdim const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D); 8085280031Sdim if (!FD) 8086280031Sdim return; 8087280031Sdim 8088314564Sdim llvm::Function *F = cast<llvm::Function>(GV); 8089314564Sdim 8090321369Sdim const auto *ReqdWGS = M.getLangOpts().OpenCL ? 8091321369Sdim FD->getAttr<ReqdWorkGroupSizeAttr>() : nullptr; 8092341825Sdim 8093360784Sdim 8094360784Sdim const bool IsOpenCLKernel = M.getLangOpts().OpenCL && 8095360784Sdim FD->hasAttr<OpenCLKernelAttr>(); 8096360784Sdim const bool IsHIPKernel = M.getLangOpts().HIP && 8097360784Sdim FD->hasAttr<CUDAGlobalAttr>(); 8098360784Sdim if ((IsOpenCLKernel || IsHIPKernel) && 8099341825Sdim (M.getTriple().getOS() == llvm::Triple::AMDHSA)) 8100353358Sdim F->addFnAttr("amdgpu-implicitarg-num-bytes", "56"); 8101341825Sdim 8102321369Sdim const auto *FlatWGS = FD->getAttr<AMDGPUFlatWorkGroupSizeAttr>(); 8103321369Sdim if (ReqdWGS || FlatWGS) { 8104353358Sdim unsigned Min = 0; 8105353358Sdim unsigned Max = 0; 8106353358Sdim if (FlatWGS) { 8107353358Sdim Min = FlatWGS->getMin() 8108353358Sdim ->EvaluateKnownConstInt(M.getContext()) 8109353358Sdim .getExtValue(); 8110353358Sdim Max = FlatWGS->getMax() 8111353358Sdim ->EvaluateKnownConstInt(M.getContext()) 8112353358Sdim .getExtValue(); 8113353358Sdim } 8114321369Sdim if (ReqdWGS && Min == 0 && Max == 0) 8115321369Sdim Min = Max = ReqdWGS->getXDim() * ReqdWGS->getYDim() * ReqdWGS->getZDim(); 8116314564Sdim 8117314564Sdim if (Min != 0) { 8118314564Sdim assert(Min <= Max && "Min must be less than or equal Max"); 8119314564Sdim 8120314564Sdim std::string AttrVal = llvm::utostr(Min) + "," + llvm::utostr(Max); 8121314564Sdim F->addFnAttr("amdgpu-flat-work-group-size", AttrVal); 8122314564Sdim } else 8123314564Sdim assert(Max == 0 && "Max must be zero"); 8124360784Sdim } else if (IsOpenCLKernel || IsHIPKernel) { 8125360784Sdim // By default, restrict the maximum size to a value specified by 8126360784Sdim // --gpu-max-threads-per-block=n or its default value. 8127360784Sdim std::string AttrVal = 8128360784Sdim std::string("1,") + llvm::utostr(M.getLangOpts().GPUMaxThreadsPerBlock); 8129360784Sdim F->addFnAttr("amdgpu-flat-work-group-size", AttrVal); 8130280031Sdim } 8131280031Sdim 8132314564Sdim if (const auto *Attr = FD->getAttr<AMDGPUWavesPerEUAttr>()) { 8133353358Sdim unsigned Min = 8134353358Sdim Attr->getMin()->EvaluateKnownConstInt(M.getContext()).getExtValue(); 8135353358Sdim unsigned Max = Attr->getMax() ? Attr->getMax() 8136353358Sdim ->EvaluateKnownConstInt(M.getContext()) 8137353358Sdim .getExtValue() 8138353358Sdim : 0; 8139314564Sdim 8140314564Sdim if (Min != 0) { 8141314564Sdim assert((Max == 0 || Min <= Max) && "Min must be less than or equal Max"); 8142314564Sdim 8143314564Sdim std::string AttrVal = llvm::utostr(Min); 8144314564Sdim if (Max != 0) 8145314564Sdim AttrVal = AttrVal + "," + llvm::utostr(Max); 8146314564Sdim F->addFnAttr("amdgpu-waves-per-eu", AttrVal); 8147314564Sdim } else 8148314564Sdim assert(Max == 0 && "Max must be zero"); 8149314564Sdim } 8150314564Sdim 8151314564Sdim if (const auto *Attr = FD->getAttr<AMDGPUNumSGPRAttr>()) { 8152280031Sdim unsigned NumSGPR = Attr->getNumSGPR(); 8153314564Sdim 8154280031Sdim if (NumSGPR != 0) 8155314564Sdim F->addFnAttr("amdgpu-num-sgpr", llvm::utostr(NumSGPR)); 8156280031Sdim } 8157314564Sdim 8158314564Sdim if (const auto *Attr = FD->getAttr<AMDGPUNumVGPRAttr>()) { 8159314564Sdim uint32_t NumVGPR = Attr->getNumVGPR(); 8160314564Sdim 8161314564Sdim if (NumVGPR != 0) 8162314564Sdim F->addFnAttr("amdgpu-num-vgpr", llvm::utostr(NumVGPR)); 8163314564Sdim } 8164280031Sdim} 8165280031Sdim 8166309124Sdimunsigned AMDGPUTargetCodeGenInfo::getOpenCLKernelCallingConv() const { 8167309124Sdim return llvm::CallingConv::AMDGPU_KERNEL; 8168309124Sdim} 8169309124Sdim 8170314564Sdim// Currently LLVM assumes null pointers always have value 0, 8171314564Sdim// which results in incorrectly transformed IR. Therefore, instead of 8172314564Sdim// emitting null pointers in private and local address spaces, a null 8173314564Sdim// pointer in generic address space is emitted which is casted to a 8174314564Sdim// pointer in local or private address space. 8175314564Sdimllvm::Constant *AMDGPUTargetCodeGenInfo::getNullPointer( 8176314564Sdim const CodeGen::CodeGenModule &CGM, llvm::PointerType *PT, 8177314564Sdim QualType QT) const { 8178314564Sdim if (CGM.getContext().getTargetNullPointerValue(QT) == 0) 8179314564Sdim return llvm::ConstantPointerNull::get(PT); 8180314564Sdim 8181314564Sdim auto &Ctx = CGM.getContext(); 8182314564Sdim auto NPT = llvm::PointerType::get(PT->getElementType(), 8183314564Sdim Ctx.getTargetAddressSpace(LangAS::opencl_generic)); 8184314564Sdim return llvm::ConstantExpr::getAddrSpaceCast( 8185314564Sdim llvm::ConstantPointerNull::get(NPT), PT); 8186314564Sdim} 8187314564Sdim 8188327952SdimLangAS 8189321369SdimAMDGPUTargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM, 8190321369Sdim const VarDecl *D) const { 8191321369Sdim assert(!CGM.getLangOpts().OpenCL && 8192321369Sdim !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) && 8193321369Sdim "Address space agnostic languages only"); 8194327952Sdim LangAS DefaultGlobalAS = getLangASFromTargetAS( 8195327952Sdim CGM.getContext().getTargetAddressSpace(LangAS::opencl_global)); 8196321369Sdim if (!D) 8197321369Sdim return DefaultGlobalAS; 8198321369Sdim 8199327952Sdim LangAS AddrSpace = D->getType().getAddressSpace(); 8200327952Sdim assert(AddrSpace == LangAS::Default || isTargetAddressSpace(AddrSpace)); 8201321369Sdim if (AddrSpace != LangAS::Default) 8202321369Sdim return AddrSpace; 8203321369Sdim 8204321369Sdim if (CGM.isTypeConstant(D->getType(), false)) { 8205321369Sdim if (auto ConstAS = CGM.getTarget().getConstantAddressSpace()) 8206321369Sdim return ConstAS.getValue(); 8207321369Sdim } 8208321369Sdim return DefaultGlobalAS; 8209321369Sdim} 8210321369Sdim 8211327952Sdimllvm::SyncScope::ID 8212353358SdimAMDGPUTargetCodeGenInfo::getLLVMSyncScopeID(const LangOptions &LangOpts, 8213353358Sdim SyncScope Scope, 8214353358Sdim llvm::AtomicOrdering Ordering, 8215353358Sdim llvm::LLVMContext &Ctx) const { 8216353358Sdim std::string Name; 8217353358Sdim switch (Scope) { 8218327952Sdim case SyncScope::OpenCLWorkGroup: 8219327952Sdim Name = "workgroup"; 8220327952Sdim break; 8221327952Sdim case SyncScope::OpenCLDevice: 8222327952Sdim Name = "agent"; 8223327952Sdim break; 8224327952Sdim case SyncScope::OpenCLAllSVMDevices: 8225327952Sdim Name = ""; 8226327952Sdim break; 8227327952Sdim case SyncScope::OpenCLSubGroup: 8228353358Sdim Name = "wavefront"; 8229327952Sdim } 8230353358Sdim 8231353358Sdim if (Ordering != llvm::AtomicOrdering::SequentiallyConsistent) { 8232353358Sdim if (!Name.empty()) 8233353358Sdim Name = Twine(Twine(Name) + Twine("-")).str(); 8234353358Sdim 8235353358Sdim Name = Twine(Twine(Name) + Twine("one-as")).str(); 8236353358Sdim } 8237353358Sdim 8238353358Sdim return Ctx.getOrInsertSyncScopeID(Name); 8239327952Sdim} 8240327952Sdim 8241341825Sdimbool AMDGPUTargetCodeGenInfo::shouldEmitStaticExternCAliases() const { 8242341825Sdim return false; 8243341825Sdim} 8244341825Sdim 8245341825Sdimvoid AMDGPUTargetCodeGenInfo::setCUDAKernelCallingConvention( 8246341825Sdim const FunctionType *&FT) const { 8247341825Sdim FT = getABIInfo().getContext().adjustFunctionType( 8248341825Sdim FT, FT->getExtInfo().withCallingConv(CC_OpenCLKernel)); 8249341825Sdim} 8250341825Sdim 8251261991Sdim//===----------------------------------------------------------------------===// 8252309124Sdim// SPARC v8 ABI Implementation. 8253309124Sdim// Based on the SPARC Compliance Definition version 2.4.1. 8254309124Sdim// 8255309124Sdim// Ensures that complex values are passed in registers. 8256309124Sdim// 8257309124Sdimnamespace { 8258309124Sdimclass SparcV8ABIInfo : public DefaultABIInfo { 8259309124Sdimpublic: 8260309124Sdim SparcV8ABIInfo(CodeGenTypes &CGT) : DefaultABIInfo(CGT) {} 8261309124Sdim 8262309124Sdimprivate: 8263309124Sdim ABIArgInfo classifyReturnType(QualType RetTy) const; 8264309124Sdim void computeInfo(CGFunctionInfo &FI) const override; 8265309124Sdim}; 8266309124Sdim} // end anonymous namespace 8267309124Sdim 8268309124Sdim 8269309124SdimABIArgInfo 8270309124SdimSparcV8ABIInfo::classifyReturnType(QualType Ty) const { 8271309124Sdim if (Ty->isAnyComplexType()) { 8272309124Sdim return ABIArgInfo::getDirect(); 8273309124Sdim } 8274309124Sdim else { 8275309124Sdim return DefaultABIInfo::classifyReturnType(Ty); 8276309124Sdim } 8277309124Sdim} 8278309124Sdim 8279309124Sdimvoid SparcV8ABIInfo::computeInfo(CGFunctionInfo &FI) const { 8280309124Sdim 8281309124Sdim FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 8282309124Sdim for (auto &Arg : FI.arguments()) 8283309124Sdim Arg.info = classifyArgumentType(Arg.type); 8284309124Sdim} 8285309124Sdim 8286309124Sdimnamespace { 8287309124Sdimclass SparcV8TargetCodeGenInfo : public TargetCodeGenInfo { 8288309124Sdimpublic: 8289309124Sdim SparcV8TargetCodeGenInfo(CodeGenTypes &CGT) 8290309124Sdim : TargetCodeGenInfo(new SparcV8ABIInfo(CGT)) {} 8291309124Sdim}; 8292309124Sdim} // end anonymous namespace 8293309124Sdim 8294309124Sdim//===----------------------------------------------------------------------===// 8295261991Sdim// SPARC v9 ABI Implementation. 8296261991Sdim// Based on the SPARC Compliance Definition version 2.4.1. 8297261991Sdim// 8298261991Sdim// Function arguments a mapped to a nominal "parameter array" and promoted to 8299261991Sdim// registers depending on their type. Each argument occupies 8 or 16 bytes in 8300261991Sdim// the array, structs larger than 16 bytes are passed indirectly. 8301261991Sdim// 8302261991Sdim// One case requires special care: 8303261991Sdim// 8304261991Sdim// struct mixed { 8305261991Sdim// int i; 8306261991Sdim// float f; 8307261991Sdim// }; 8308261991Sdim// 8309261991Sdim// When a struct mixed is passed by value, it only occupies 8 bytes in the 8310261991Sdim// parameter array, but the int is passed in an integer register, and the float 8311261991Sdim// is passed in a floating point register. This is represented as two arguments 8312261991Sdim// with the LLVM IR inreg attribute: 8313261991Sdim// 8314261991Sdim// declare void f(i32 inreg %i, float inreg %f) 8315261991Sdim// 8316261991Sdim// The code generator will only allocate 4 bytes from the parameter array for 8317261991Sdim// the inreg arguments. All other arguments are allocated a multiple of 8 8318261991Sdim// bytes. 8319261991Sdim// 8320261991Sdimnamespace { 8321261991Sdimclass SparcV9ABIInfo : public ABIInfo { 8322261991Sdimpublic: 8323261991Sdim SparcV9ABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {} 8324261991Sdim 8325261991Sdimprivate: 8326261991Sdim ABIArgInfo classifyType(QualType RetTy, unsigned SizeLimit) const; 8327276479Sdim void computeInfo(CGFunctionInfo &FI) const override; 8328296417Sdim Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 8329296417Sdim QualType Ty) const override; 8330261991Sdim 8331261991Sdim // Coercion type builder for structs passed in registers. The coercion type 8332261991Sdim // serves two purposes: 8333261991Sdim // 8334261991Sdim // 1. Pad structs to a multiple of 64 bits, so they are passed 'left-aligned' 8335261991Sdim // in registers. 8336261991Sdim // 2. Expose aligned floating point elements as first-level elements, so the 8337261991Sdim // code generator knows to pass them in floating point registers. 8338261991Sdim // 8339261991Sdim // We also compute the InReg flag which indicates that the struct contains 8340261991Sdim // aligned 32-bit floats. 8341261991Sdim // 8342261991Sdim struct CoerceBuilder { 8343261991Sdim llvm::LLVMContext &Context; 8344261991Sdim const llvm::DataLayout &DL; 8345261991Sdim SmallVector<llvm::Type*, 8> Elems; 8346261991Sdim uint64_t Size; 8347261991Sdim bool InReg; 8348261991Sdim 8349261991Sdim CoerceBuilder(llvm::LLVMContext &c, const llvm::DataLayout &dl) 8350261991Sdim : Context(c), DL(dl), Size(0), InReg(false) {} 8351261991Sdim 8352261991Sdim // Pad Elems with integers until Size is ToSize. 8353261991Sdim void pad(uint64_t ToSize) { 8354261991Sdim assert(ToSize >= Size && "Cannot remove elements"); 8355261991Sdim if (ToSize == Size) 8356261991Sdim return; 8357261991Sdim 8358261991Sdim // Finish the current 64-bit word. 8359309124Sdim uint64_t Aligned = llvm::alignTo(Size, 64); 8360261991Sdim if (Aligned > Size && Aligned <= ToSize) { 8361261991Sdim Elems.push_back(llvm::IntegerType::get(Context, Aligned - Size)); 8362261991Sdim Size = Aligned; 8363261991Sdim } 8364261991Sdim 8365261991Sdim // Add whole 64-bit words. 8366261991Sdim while (Size + 64 <= ToSize) { 8367261991Sdim Elems.push_back(llvm::Type::getInt64Ty(Context)); 8368261991Sdim Size += 64; 8369261991Sdim } 8370261991Sdim 8371261991Sdim // Final in-word padding. 8372261991Sdim if (Size < ToSize) { 8373261991Sdim Elems.push_back(llvm::IntegerType::get(Context, ToSize - Size)); 8374261991Sdim Size = ToSize; 8375261991Sdim } 8376261991Sdim } 8377261991Sdim 8378261991Sdim // Add a floating point element at Offset. 8379261991Sdim void addFloat(uint64_t Offset, llvm::Type *Ty, unsigned Bits) { 8380261991Sdim // Unaligned floats are treated as integers. 8381261991Sdim if (Offset % Bits) 8382261991Sdim return; 8383261991Sdim // The InReg flag is only required if there are any floats < 64 bits. 8384261991Sdim if (Bits < 64) 8385261991Sdim InReg = true; 8386261991Sdim pad(Offset); 8387261991Sdim Elems.push_back(Ty); 8388261991Sdim Size = Offset + Bits; 8389261991Sdim } 8390261991Sdim 8391261991Sdim // Add a struct type to the coercion type, starting at Offset (in bits). 8392261991Sdim void addStruct(uint64_t Offset, llvm::StructType *StrTy) { 8393261991Sdim const llvm::StructLayout *Layout = DL.getStructLayout(StrTy); 8394261991Sdim for (unsigned i = 0, e = StrTy->getNumElements(); i != e; ++i) { 8395261991Sdim llvm::Type *ElemTy = StrTy->getElementType(i); 8396261991Sdim uint64_t ElemOffset = Offset + Layout->getElementOffsetInBits(i); 8397261991Sdim switch (ElemTy->getTypeID()) { 8398261991Sdim case llvm::Type::StructTyID: 8399261991Sdim addStruct(ElemOffset, cast<llvm::StructType>(ElemTy)); 8400261991Sdim break; 8401261991Sdim case llvm::Type::FloatTyID: 8402261991Sdim addFloat(ElemOffset, ElemTy, 32); 8403261991Sdim break; 8404261991Sdim case llvm::Type::DoubleTyID: 8405261991Sdim addFloat(ElemOffset, ElemTy, 64); 8406261991Sdim break; 8407261991Sdim case llvm::Type::FP128TyID: 8408261991Sdim addFloat(ElemOffset, ElemTy, 128); 8409261991Sdim break; 8410261991Sdim case llvm::Type::PointerTyID: 8411261991Sdim if (ElemOffset % 64 == 0) { 8412261991Sdim pad(ElemOffset); 8413261991Sdim Elems.push_back(ElemTy); 8414261991Sdim Size += 64; 8415261991Sdim } 8416261991Sdim break; 8417261991Sdim default: 8418261991Sdim break; 8419261991Sdim } 8420261991Sdim } 8421261991Sdim } 8422261991Sdim 8423261991Sdim // Check if Ty is a usable substitute for the coercion type. 8424261991Sdim bool isUsableType(llvm::StructType *Ty) const { 8425288943Sdim return llvm::makeArrayRef(Elems) == Ty->elements(); 8426261991Sdim } 8427261991Sdim 8428261991Sdim // Get the coercion type as a literal struct type. 8429261991Sdim llvm::Type *getType() const { 8430261991Sdim if (Elems.size() == 1) 8431261991Sdim return Elems.front(); 8432261991Sdim else 8433261991Sdim return llvm::StructType::get(Context, Elems); 8434261991Sdim } 8435261991Sdim }; 8436261991Sdim}; 8437261991Sdim} // end anonymous namespace 8438261991Sdim 8439261991SdimABIArgInfo 8440261991SdimSparcV9ABIInfo::classifyType(QualType Ty, unsigned SizeLimit) const { 8441261991Sdim if (Ty->isVoidType()) 8442261991Sdim return ABIArgInfo::getIgnore(); 8443261991Sdim 8444261991Sdim uint64_t Size = getContext().getTypeSize(Ty); 8445261991Sdim 8446261991Sdim // Anything too big to fit in registers is passed with an explicit indirect 8447261991Sdim // pointer / sret pointer. 8448261991Sdim if (Size > SizeLimit) 8449296417Sdim return getNaturalAlignIndirect(Ty, /*ByVal=*/false); 8450261991Sdim 8451261991Sdim // Treat an enum type as its underlying type. 8452261991Sdim if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 8453261991Sdim Ty = EnumTy->getDecl()->getIntegerType(); 8454261991Sdim 8455261991Sdim // Integer types smaller than a register are extended. 8456261991Sdim if (Size < 64 && Ty->isIntegerType()) 8457341825Sdim return ABIArgInfo::getExtend(Ty); 8458261991Sdim 8459261991Sdim // Other non-aggregates go in registers. 8460261991Sdim if (!isAggregateTypeForABI(Ty)) 8461261991Sdim return ABIArgInfo::getDirect(); 8462261991Sdim 8463262613Sdim // If a C++ object has either a non-trivial copy constructor or a non-trivial 8464262613Sdim // destructor, it is passed with an explicit indirect pointer / sret pointer. 8465262613Sdim if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) 8466296417Sdim return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory); 8467262613Sdim 8468261991Sdim // This is a small aggregate type that should be passed in registers. 8469261991Sdim // Build a coercion type from the LLVM struct type. 8470261991Sdim llvm::StructType *StrTy = dyn_cast<llvm::StructType>(CGT.ConvertType(Ty)); 8471261991Sdim if (!StrTy) 8472261991Sdim return ABIArgInfo::getDirect(); 8473261991Sdim 8474261991Sdim CoerceBuilder CB(getVMContext(), getDataLayout()); 8475261991Sdim CB.addStruct(0, StrTy); 8476309124Sdim CB.pad(llvm::alignTo(CB.DL.getTypeSizeInBits(StrTy), 64)); 8477261991Sdim 8478261991Sdim // Try to use the original type for coercion. 8479261991Sdim llvm::Type *CoerceTy = CB.isUsableType(StrTy) ? StrTy : CB.getType(); 8480261991Sdim 8481261991Sdim if (CB.InReg) 8482261991Sdim return ABIArgInfo::getDirectInReg(CoerceTy); 8483261991Sdim else 8484261991Sdim return ABIArgInfo::getDirect(CoerceTy); 8485261991Sdim} 8486261991Sdim 8487296417SdimAddress SparcV9ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 8488296417Sdim QualType Ty) const { 8489261991Sdim ABIArgInfo AI = classifyType(Ty, 16 * 8); 8490261991Sdim llvm::Type *ArgTy = CGT.ConvertType(Ty); 8491261991Sdim if (AI.canHaveCoerceToType() && !AI.getCoerceToType()) 8492261991Sdim AI.setCoerceToType(ArgTy); 8493261991Sdim 8494296417Sdim CharUnits SlotSize = CharUnits::fromQuantity(8); 8495296417Sdim 8496261991Sdim CGBuilderTy &Builder = CGF.Builder; 8497296417Sdim Address Addr(Builder.CreateLoad(VAListAddr, "ap.cur"), SlotSize); 8498261991Sdim llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy); 8499261991Sdim 8500296417Sdim auto TypeInfo = getContext().getTypeInfoInChars(Ty); 8501296417Sdim 8502296417Sdim Address ArgAddr = Address::invalid(); 8503296417Sdim CharUnits Stride; 8504261991Sdim switch (AI.getKind()) { 8505261991Sdim case ABIArgInfo::Expand: 8506309124Sdim case ABIArgInfo::CoerceAndExpand: 8507276479Sdim case ABIArgInfo::InAlloca: 8508261991Sdim llvm_unreachable("Unsupported ABI kind for va_arg"); 8509261991Sdim 8510296417Sdim case ABIArgInfo::Extend: { 8511296417Sdim Stride = SlotSize; 8512296417Sdim CharUnits Offset = SlotSize - TypeInfo.first; 8513296417Sdim ArgAddr = Builder.CreateConstInBoundsByteGEP(Addr, Offset, "extend"); 8514261991Sdim break; 8515296417Sdim } 8516261991Sdim 8517296417Sdim case ABIArgInfo::Direct: { 8518296417Sdim auto AllocSize = getDataLayout().getTypeAllocSize(AI.getCoerceToType()); 8519309124Sdim Stride = CharUnits::fromQuantity(AllocSize).alignTo(SlotSize); 8520261991Sdim ArgAddr = Addr; 8521261991Sdim break; 8522296417Sdim } 8523261991Sdim 8524261991Sdim case ABIArgInfo::Indirect: 8525296417Sdim Stride = SlotSize; 8526296417Sdim ArgAddr = Builder.CreateElementBitCast(Addr, ArgPtrTy, "indirect"); 8527296417Sdim ArgAddr = Address(Builder.CreateLoad(ArgAddr, "indirect.arg"), 8528296417Sdim TypeInfo.second); 8529261991Sdim break; 8530261991Sdim 8531261991Sdim case ABIArgInfo::Ignore: 8532296417Sdim return Address(llvm::UndefValue::get(ArgPtrTy), TypeInfo.second); 8533261991Sdim } 8534261991Sdim 8535261991Sdim // Update VAList. 8536353358Sdim Address NextPtr = Builder.CreateConstInBoundsByteGEP(Addr, Stride, "ap.next"); 8537353358Sdim Builder.CreateStore(NextPtr.getPointer(), VAListAddr); 8538261991Sdim 8539296417Sdim return Builder.CreateBitCast(ArgAddr, ArgPtrTy, "arg.addr"); 8540261991Sdim} 8541261991Sdim 8542261991Sdimvoid SparcV9ABIInfo::computeInfo(CGFunctionInfo &FI) const { 8543261991Sdim FI.getReturnInfo() = classifyType(FI.getReturnType(), 32 * 8); 8544276479Sdim for (auto &I : FI.arguments()) 8545276479Sdim I.info = classifyType(I.type, 16 * 8); 8546261991Sdim} 8547261991Sdim 8548261991Sdimnamespace { 8549261991Sdimclass SparcV9TargetCodeGenInfo : public TargetCodeGenInfo { 8550261991Sdimpublic: 8551261991Sdim SparcV9TargetCodeGenInfo(CodeGenTypes &CGT) 8552261991Sdim : TargetCodeGenInfo(new SparcV9ABIInfo(CGT)) {} 8553262613Sdim 8554276479Sdim int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override { 8555262613Sdim return 14; 8556262613Sdim } 8557262613Sdim 8558262613Sdim bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 8559276479Sdim llvm::Value *Address) const override; 8560261991Sdim}; 8561261991Sdim} // end anonymous namespace 8562261991Sdim 8563262613Sdimbool 8564262613SdimSparcV9TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 8565262613Sdim llvm::Value *Address) const { 8566262613Sdim // This is calculated from the LLVM and GCC tables and verified 8567262613Sdim // against gcc output. AFAIK all ABIs use the same encoding. 8568261991Sdim 8569262613Sdim CodeGen::CGBuilderTy &Builder = CGF.Builder; 8570262613Sdim 8571262613Sdim llvm::IntegerType *i8 = CGF.Int8Ty; 8572262613Sdim llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4); 8573262613Sdim llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8); 8574262613Sdim 8575262613Sdim // 0-31: the 8-byte general-purpose registers 8576262613Sdim AssignToArrayRange(Builder, Address, Eight8, 0, 31); 8577262613Sdim 8578262613Sdim // 32-63: f0-31, the 4-byte floating-point registers 8579262613Sdim AssignToArrayRange(Builder, Address, Four8, 32, 63); 8580262613Sdim 8581262613Sdim // Y = 64 8582262613Sdim // PSR = 65 8583262613Sdim // WIM = 66 8584262613Sdim // TBR = 67 8585262613Sdim // PC = 68 8586262613Sdim // NPC = 69 8587262613Sdim // FSR = 70 8588262613Sdim // CSR = 71 8589262613Sdim AssignToArrayRange(Builder, Address, Eight8, 64, 71); 8590288943Sdim 8591262613Sdim // 72-87: d0-15, the 8-byte floating-point registers 8592262613Sdim AssignToArrayRange(Builder, Address, Eight8, 72, 87); 8593262613Sdim 8594262613Sdim return false; 8595262613Sdim} 8596262613Sdim 8597344779Sdim// ARC ABI implementation. 8598344779Sdimnamespace { 8599262613Sdim 8600344779Sdimclass ARCABIInfo : public DefaultABIInfo { 8601344779Sdimpublic: 8602344779Sdim using DefaultABIInfo::DefaultABIInfo; 8603344779Sdim 8604344779Sdimprivate: 8605344779Sdim Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 8606344779Sdim QualType Ty) const override; 8607344779Sdim 8608344779Sdim void updateState(const ABIArgInfo &Info, QualType Ty, CCState &State) const { 8609344779Sdim if (!State.FreeRegs) 8610344779Sdim return; 8611344779Sdim if (Info.isIndirect() && Info.getInReg()) 8612344779Sdim State.FreeRegs--; 8613344779Sdim else if (Info.isDirect() && Info.getInReg()) { 8614344779Sdim unsigned sz = (getContext().getTypeSize(Ty) + 31) / 32; 8615344779Sdim if (sz < State.FreeRegs) 8616344779Sdim State.FreeRegs -= sz; 8617344779Sdim else 8618344779Sdim State.FreeRegs = 0; 8619344779Sdim } 8620344779Sdim } 8621344779Sdim 8622344779Sdim void computeInfo(CGFunctionInfo &FI) const override { 8623360784Sdim CCState State(FI); 8624344779Sdim // ARC uses 8 registers to pass arguments. 8625344779Sdim State.FreeRegs = 8; 8626344779Sdim 8627344779Sdim if (!getCXXABI().classifyReturnType(FI)) 8628344779Sdim FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 8629344779Sdim updateState(FI.getReturnInfo(), FI.getReturnType(), State); 8630344779Sdim for (auto &I : FI.arguments()) { 8631344779Sdim I.info = classifyArgumentType(I.type, State.FreeRegs); 8632344779Sdim updateState(I.info, I.type, State); 8633344779Sdim } 8634344779Sdim } 8635344779Sdim 8636344779Sdim ABIArgInfo getIndirectByRef(QualType Ty, bool HasFreeRegs) const; 8637344779Sdim ABIArgInfo getIndirectByValue(QualType Ty) const; 8638344779Sdim ABIArgInfo classifyArgumentType(QualType Ty, uint8_t FreeRegs) const; 8639344779Sdim ABIArgInfo classifyReturnType(QualType RetTy) const; 8640344779Sdim}; 8641344779Sdim 8642344779Sdimclass ARCTargetCodeGenInfo : public TargetCodeGenInfo { 8643344779Sdimpublic: 8644344779Sdim ARCTargetCodeGenInfo(CodeGenTypes &CGT) 8645344779Sdim : TargetCodeGenInfo(new ARCABIInfo(CGT)) {} 8646344779Sdim}; 8647344779Sdim 8648344779Sdim 8649344779SdimABIArgInfo ARCABIInfo::getIndirectByRef(QualType Ty, bool HasFreeRegs) const { 8650344779Sdim return HasFreeRegs ? getNaturalAlignIndirectInReg(Ty) : 8651344779Sdim getNaturalAlignIndirect(Ty, false); 8652344779Sdim} 8653344779Sdim 8654344779SdimABIArgInfo ARCABIInfo::getIndirectByValue(QualType Ty) const { 8655344779Sdim // Compute the byval alignment. 8656344779Sdim const unsigned MinABIStackAlignInBytes = 4; 8657344779Sdim unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8; 8658344779Sdim return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true, 8659344779Sdim TypeAlign > MinABIStackAlignInBytes); 8660344779Sdim} 8661344779Sdim 8662344779SdimAddress ARCABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 8663344779Sdim QualType Ty) const { 8664344779Sdim return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false, 8665344779Sdim getContext().getTypeInfoInChars(Ty), 8666344779Sdim CharUnits::fromQuantity(4), true); 8667344779Sdim} 8668344779Sdim 8669344779SdimABIArgInfo ARCABIInfo::classifyArgumentType(QualType Ty, 8670344779Sdim uint8_t FreeRegs) const { 8671344779Sdim // Handle the generic C++ ABI. 8672344779Sdim const RecordType *RT = Ty->getAs<RecordType>(); 8673344779Sdim if (RT) { 8674344779Sdim CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI()); 8675344779Sdim if (RAA == CGCXXABI::RAA_Indirect) 8676344779Sdim return getIndirectByRef(Ty, FreeRegs > 0); 8677344779Sdim 8678344779Sdim if (RAA == CGCXXABI::RAA_DirectInMemory) 8679344779Sdim return getIndirectByValue(Ty); 8680344779Sdim } 8681344779Sdim 8682344779Sdim // Treat an enum type as its underlying type. 8683344779Sdim if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 8684344779Sdim Ty = EnumTy->getDecl()->getIntegerType(); 8685344779Sdim 8686344779Sdim auto SizeInRegs = llvm::alignTo(getContext().getTypeSize(Ty), 32) / 32; 8687344779Sdim 8688344779Sdim if (isAggregateTypeForABI(Ty)) { 8689344779Sdim // Structures with flexible arrays are always indirect. 8690344779Sdim if (RT && RT->getDecl()->hasFlexibleArrayMember()) 8691344779Sdim return getIndirectByValue(Ty); 8692344779Sdim 8693344779Sdim // Ignore empty structs/unions. 8694344779Sdim if (isEmptyRecord(getContext(), Ty, true)) 8695344779Sdim return ABIArgInfo::getIgnore(); 8696344779Sdim 8697344779Sdim llvm::LLVMContext &LLVMContext = getVMContext(); 8698344779Sdim 8699344779Sdim llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext); 8700344779Sdim SmallVector<llvm::Type *, 3> Elements(SizeInRegs, Int32); 8701344779Sdim llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements); 8702344779Sdim 8703344779Sdim return FreeRegs >= SizeInRegs ? 8704344779Sdim ABIArgInfo::getDirectInReg(Result) : 8705344779Sdim ABIArgInfo::getDirect(Result, 0, nullptr, false); 8706344779Sdim } 8707344779Sdim 8708344779Sdim return Ty->isPromotableIntegerType() ? 8709344779Sdim (FreeRegs >= SizeInRegs ? ABIArgInfo::getExtendInReg(Ty) : 8710344779Sdim ABIArgInfo::getExtend(Ty)) : 8711344779Sdim (FreeRegs >= SizeInRegs ? ABIArgInfo::getDirectInReg() : 8712344779Sdim ABIArgInfo::getDirect()); 8713344779Sdim} 8714344779Sdim 8715344779SdimABIArgInfo ARCABIInfo::classifyReturnType(QualType RetTy) const { 8716344779Sdim if (RetTy->isAnyComplexType()) 8717344779Sdim return ABIArgInfo::getDirectInReg(); 8718344779Sdim 8719344779Sdim // Arguments of size > 4 registers are indirect. 8720344779Sdim auto RetSize = llvm::alignTo(getContext().getTypeSize(RetTy), 32) / 32; 8721344779Sdim if (RetSize > 4) 8722344779Sdim return getIndirectByRef(RetTy, /*HasFreeRegs*/ true); 8723344779Sdim 8724344779Sdim return DefaultABIInfo::classifyReturnType(RetTy); 8725344779Sdim} 8726344779Sdim 8727344779Sdim} // End anonymous namespace. 8728344779Sdim 8729261991Sdim//===----------------------------------------------------------------------===// 8730276479Sdim// XCore ABI Implementation 8731261991Sdim//===----------------------------------------------------------------------===// 8732276479Sdim 8733261991Sdimnamespace { 8734276479Sdim 8735276479Sdim/// A SmallStringEnc instance is used to build up the TypeString by passing 8736276479Sdim/// it by reference between functions that append to it. 8737276479Sdimtypedef llvm::SmallString<128> SmallStringEnc; 8738276479Sdim 8739276479Sdim/// TypeStringCache caches the meta encodings of Types. 8740276479Sdim/// 8741276479Sdim/// The reason for caching TypeStrings is two fold: 8742276479Sdim/// 1. To cache a type's encoding for later uses; 8743276479Sdim/// 2. As a means to break recursive member type inclusion. 8744276479Sdim/// 8745276479Sdim/// A cache Entry can have a Status of: 8746276479Sdim/// NonRecursive: The type encoding is not recursive; 8747276479Sdim/// Recursive: The type encoding is recursive; 8748276479Sdim/// Incomplete: An incomplete TypeString; 8749276479Sdim/// IncompleteUsed: An incomplete TypeString that has been used in a 8750276479Sdim/// Recursive type encoding. 8751276479Sdim/// 8752276479Sdim/// A NonRecursive entry will have all of its sub-members expanded as fully 8753276479Sdim/// as possible. Whilst it may contain types which are recursive, the type 8754276479Sdim/// itself is not recursive and thus its encoding may be safely used whenever 8755276479Sdim/// the type is encountered. 8756276479Sdim/// 8757276479Sdim/// A Recursive entry will have all of its sub-members expanded as fully as 8758276479Sdim/// possible. The type itself is recursive and it may contain other types which 8759276479Sdim/// are recursive. The Recursive encoding must not be used during the expansion 8760276479Sdim/// of a recursive type's recursive branch. For simplicity the code uses 8761276479Sdim/// IncompleteCount to reject all usage of Recursive encodings for member types. 8762276479Sdim/// 8763276479Sdim/// An Incomplete entry is always a RecordType and only encodes its 8764276479Sdim/// identifier e.g. "s(S){}". Incomplete 'StubEnc' entries are ephemeral and 8765276479Sdim/// are placed into the cache during type expansion as a means to identify and 8766276479Sdim/// handle recursive inclusion of types as sub-members. If there is recursion 8767276479Sdim/// the entry becomes IncompleteUsed. 8768276479Sdim/// 8769276479Sdim/// During the expansion of a RecordType's members: 8770276479Sdim/// 8771276479Sdim/// If the cache contains a NonRecursive encoding for the member type, the 8772276479Sdim/// cached encoding is used; 8773276479Sdim/// 8774276479Sdim/// If the cache contains a Recursive encoding for the member type, the 8775276479Sdim/// cached encoding is 'Swapped' out, as it may be incorrect, and... 8776276479Sdim/// 8777276479Sdim/// If the member is a RecordType, an Incomplete encoding is placed into the 8778276479Sdim/// cache to break potential recursive inclusion of itself as a sub-member; 8779276479Sdim/// 8780276479Sdim/// Once a member RecordType has been expanded, its temporary incomplete 8781276479Sdim/// entry is removed from the cache. If a Recursive encoding was swapped out 8782276479Sdim/// it is swapped back in; 8783276479Sdim/// 8784276479Sdim/// If an incomplete entry is used to expand a sub-member, the incomplete 8785276479Sdim/// entry is marked as IncompleteUsed. The cache keeps count of how many 8786276479Sdim/// IncompleteUsed entries it currently contains in IncompleteUsedCount; 8787276479Sdim/// 8788276479Sdim/// If a member's encoding is found to be a NonRecursive or Recursive viz: 8789276479Sdim/// IncompleteUsedCount==0, the member's encoding is added to the cache. 8790276479Sdim/// Else the member is part of a recursive type and thus the recursion has 8791276479Sdim/// been exited too soon for the encoding to be correct for the member. 8792276479Sdim/// 8793276479Sdimclass TypeStringCache { 8794276479Sdim enum Status {NonRecursive, Recursive, Incomplete, IncompleteUsed}; 8795276479Sdim struct Entry { 8796276479Sdim std::string Str; // The encoded TypeString for the type. 8797276479Sdim enum Status State; // Information about the encoding in 'Str'. 8798276479Sdim std::string Swapped; // A temporary place holder for a Recursive encoding 8799276479Sdim // during the expansion of RecordType's members. 8800276479Sdim }; 8801276479Sdim std::map<const IdentifierInfo *, struct Entry> Map; 8802276479Sdim unsigned IncompleteCount; // Number of Incomplete entries in the Map. 8803276479Sdim unsigned IncompleteUsedCount; // Number of IncompleteUsed entries in the Map. 8804276479Sdimpublic: 8805296417Sdim TypeStringCache() : IncompleteCount(0), IncompleteUsedCount(0) {} 8806276479Sdim void addIncomplete(const IdentifierInfo *ID, std::string StubEnc); 8807276479Sdim bool removeIncomplete(const IdentifierInfo *ID); 8808276479Sdim void addIfComplete(const IdentifierInfo *ID, StringRef Str, 8809276479Sdim bool IsRecursive); 8810276479Sdim StringRef lookupStr(const IdentifierInfo *ID); 8811276479Sdim}; 8812276479Sdim 8813276479Sdim/// TypeString encodings for enum & union fields must be order. 8814276479Sdim/// FieldEncoding is a helper for this ordering process. 8815276479Sdimclass FieldEncoding { 8816276479Sdim bool HasName; 8817276479Sdim std::string Enc; 8818276479Sdimpublic: 8819296417Sdim FieldEncoding(bool b, SmallStringEnc &e) : HasName(b), Enc(e.c_str()) {} 8820314564Sdim StringRef str() { return Enc; } 8821276479Sdim bool operator<(const FieldEncoding &rhs) const { 8822276479Sdim if (HasName != rhs.HasName) return HasName; 8823276479Sdim return Enc < rhs.Enc; 8824276479Sdim } 8825276479Sdim}; 8826276479Sdim 8827261991Sdimclass XCoreABIInfo : public DefaultABIInfo { 8828261991Sdimpublic: 8829261991Sdim XCoreABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {} 8830296417Sdim Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 8831296417Sdim QualType Ty) const override; 8832261991Sdim}; 8833261991Sdim 8834276479Sdimclass XCoreTargetCodeGenInfo : public TargetCodeGenInfo { 8835276479Sdim mutable TypeStringCache TSC; 8836261991Sdimpublic: 8837276479Sdim XCoreTargetCodeGenInfo(CodeGenTypes &CGT) 8838261991Sdim :TargetCodeGenInfo(new XCoreABIInfo(CGT)) {} 8839276479Sdim void emitTargetMD(const Decl *D, llvm::GlobalValue *GV, 8840276479Sdim CodeGen::CodeGenModule &M) const override; 8841261991Sdim}; 8842276479Sdim 8843261991Sdim} // End anonymous namespace. 8844261991Sdim 8845309124Sdim// TODO: this implementation is likely now redundant with the default 8846309124Sdim// EmitVAArg. 8847296417SdimAddress XCoreABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 8848296417Sdim QualType Ty) const { 8849261991Sdim CGBuilderTy &Builder = CGF.Builder; 8850261991Sdim 8851261991Sdim // Get the VAList. 8852296417Sdim CharUnits SlotSize = CharUnits::fromQuantity(4); 8853296417Sdim Address AP(Builder.CreateLoad(VAListAddr), SlotSize); 8854261991Sdim 8855261991Sdim // Handle the argument. 8856261991Sdim ABIArgInfo AI = classifyArgumentType(Ty); 8857296417Sdim CharUnits TypeAlign = getContext().getTypeAlignInChars(Ty); 8858261991Sdim llvm::Type *ArgTy = CGT.ConvertType(Ty); 8859261991Sdim if (AI.canHaveCoerceToType() && !AI.getCoerceToType()) 8860261991Sdim AI.setCoerceToType(ArgTy); 8861261991Sdim llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy); 8862296417Sdim 8863296417Sdim Address Val = Address::invalid(); 8864296417Sdim CharUnits ArgSize = CharUnits::Zero(); 8865261991Sdim switch (AI.getKind()) { 8866261991Sdim case ABIArgInfo::Expand: 8867309124Sdim case ABIArgInfo::CoerceAndExpand: 8868276479Sdim case ABIArgInfo::InAlloca: 8869261991Sdim llvm_unreachable("Unsupported ABI kind for va_arg"); 8870261991Sdim case ABIArgInfo::Ignore: 8871296417Sdim Val = Address(llvm::UndefValue::get(ArgPtrTy), TypeAlign); 8872296417Sdim ArgSize = CharUnits::Zero(); 8873261991Sdim break; 8874261991Sdim case ABIArgInfo::Extend: 8875261991Sdim case ABIArgInfo::Direct: 8876296417Sdim Val = Builder.CreateBitCast(AP, ArgPtrTy); 8877296417Sdim ArgSize = CharUnits::fromQuantity( 8878296417Sdim getDataLayout().getTypeAllocSize(AI.getCoerceToType())); 8879309124Sdim ArgSize = ArgSize.alignTo(SlotSize); 8880261991Sdim break; 8881261991Sdim case ABIArgInfo::Indirect: 8882296417Sdim Val = Builder.CreateElementBitCast(AP, ArgPtrTy); 8883296417Sdim Val = Address(Builder.CreateLoad(Val), TypeAlign); 8884296417Sdim ArgSize = SlotSize; 8885261991Sdim break; 8886261991Sdim } 8887261991Sdim 8888261991Sdim // Increment the VAList. 8889296417Sdim if (!ArgSize.isZero()) { 8890353358Sdim Address APN = Builder.CreateConstInBoundsByteGEP(AP, ArgSize); 8891353358Sdim Builder.CreateStore(APN.getPointer(), VAListAddr); 8892261991Sdim } 8893296417Sdim 8894261991Sdim return Val; 8895261991Sdim} 8896261991Sdim 8897276479Sdim/// During the expansion of a RecordType, an incomplete TypeString is placed 8898276479Sdim/// into the cache as a means to identify and break recursion. 8899276479Sdim/// If there is a Recursive encoding in the cache, it is swapped out and will 8900276479Sdim/// be reinserted by removeIncomplete(). 8901276479Sdim/// All other types of encoding should have been used rather than arriving here. 8902276479Sdimvoid TypeStringCache::addIncomplete(const IdentifierInfo *ID, 8903276479Sdim std::string StubEnc) { 8904276479Sdim if (!ID) 8905276479Sdim return; 8906276479Sdim Entry &E = Map[ID]; 8907276479Sdim assert( (E.Str.empty() || E.State == Recursive) && 8908276479Sdim "Incorrectly use of addIncomplete"); 8909276479Sdim assert(!StubEnc.empty() && "Passing an empty string to addIncomplete()"); 8910276479Sdim E.Swapped.swap(E.Str); // swap out the Recursive 8911276479Sdim E.Str.swap(StubEnc); 8912276479Sdim E.State = Incomplete; 8913276479Sdim ++IncompleteCount; 8914276479Sdim} 8915276479Sdim 8916276479Sdim/// Once the RecordType has been expanded, the temporary incomplete TypeString 8917276479Sdim/// must be removed from the cache. 8918276479Sdim/// If a Recursive was swapped out by addIncomplete(), it will be replaced. 8919276479Sdim/// Returns true if the RecordType was defined recursively. 8920276479Sdimbool TypeStringCache::removeIncomplete(const IdentifierInfo *ID) { 8921276479Sdim if (!ID) 8922276479Sdim return false; 8923276479Sdim auto I = Map.find(ID); 8924276479Sdim assert(I != Map.end() && "Entry not present"); 8925276479Sdim Entry &E = I->second; 8926276479Sdim assert( (E.State == Incomplete || 8927276479Sdim E.State == IncompleteUsed) && 8928276479Sdim "Entry must be an incomplete type"); 8929276479Sdim bool IsRecursive = false; 8930276479Sdim if (E.State == IncompleteUsed) { 8931276479Sdim // We made use of our Incomplete encoding, thus we are recursive. 8932276479Sdim IsRecursive = true; 8933276479Sdim --IncompleteUsedCount; 8934276479Sdim } 8935276479Sdim if (E.Swapped.empty()) 8936276479Sdim Map.erase(I); 8937276479Sdim else { 8938276479Sdim // Swap the Recursive back. 8939276479Sdim E.Swapped.swap(E.Str); 8940276479Sdim E.Swapped.clear(); 8941276479Sdim E.State = Recursive; 8942276479Sdim } 8943276479Sdim --IncompleteCount; 8944276479Sdim return IsRecursive; 8945276479Sdim} 8946276479Sdim 8947276479Sdim/// Add the encoded TypeString to the cache only if it is NonRecursive or 8948276479Sdim/// Recursive (viz: all sub-members were expanded as fully as possible). 8949276479Sdimvoid TypeStringCache::addIfComplete(const IdentifierInfo *ID, StringRef Str, 8950276479Sdim bool IsRecursive) { 8951276479Sdim if (!ID || IncompleteUsedCount) 8952276479Sdim return; // No key or it is is an incomplete sub-type so don't add. 8953276479Sdim Entry &E = Map[ID]; 8954276479Sdim if (IsRecursive && !E.Str.empty()) { 8955276479Sdim assert(E.State==Recursive && E.Str.size() == Str.size() && 8956276479Sdim "This is not the same Recursive entry"); 8957276479Sdim // The parent container was not recursive after all, so we could have used 8958276479Sdim // this Recursive sub-member entry after all, but we assumed the worse when 8959276479Sdim // we started viz: IncompleteCount!=0. 8960276479Sdim return; 8961276479Sdim } 8962276479Sdim assert(E.Str.empty() && "Entry already present"); 8963276479Sdim E.Str = Str.str(); 8964276479Sdim E.State = IsRecursive? Recursive : NonRecursive; 8965276479Sdim} 8966276479Sdim 8967276479Sdim/// Return a cached TypeString encoding for the ID. If there isn't one, or we 8968276479Sdim/// are recursively expanding a type (IncompleteCount != 0) and the cached 8969276479Sdim/// encoding is Recursive, return an empty StringRef. 8970276479SdimStringRef TypeStringCache::lookupStr(const IdentifierInfo *ID) { 8971276479Sdim if (!ID) 8972276479Sdim return StringRef(); // We have no key. 8973276479Sdim auto I = Map.find(ID); 8974276479Sdim if (I == Map.end()) 8975276479Sdim return StringRef(); // We have no encoding. 8976276479Sdim Entry &E = I->second; 8977276479Sdim if (E.State == Recursive && IncompleteCount) 8978276479Sdim return StringRef(); // We don't use Recursive encodings for member types. 8979276479Sdim 8980276479Sdim if (E.State == Incomplete) { 8981276479Sdim // The incomplete type is being used to break out of recursion. 8982276479Sdim E.State = IncompleteUsed; 8983276479Sdim ++IncompleteUsedCount; 8984276479Sdim } 8985314564Sdim return E.Str; 8986276479Sdim} 8987276479Sdim 8988276479Sdim/// The XCore ABI includes a type information section that communicates symbol 8989276479Sdim/// type information to the linker. The linker uses this information to verify 8990276479Sdim/// safety/correctness of things such as array bound and pointers et al. 8991276479Sdim/// The ABI only requires C (and XC) language modules to emit TypeStrings. 8992276479Sdim/// This type information (TypeString) is emitted into meta data for all global 8993276479Sdim/// symbols: definitions, declarations, functions & variables. 8994276479Sdim/// 8995276479Sdim/// The TypeString carries type, qualifier, name, size & value details. 8996276479Sdim/// Please see 'Tools Development Guide' section 2.16.2 for format details: 8997288943Sdim/// https://www.xmos.com/download/public/Tools-Development-Guide%28X9114A%29.pdf 8998276479Sdim/// The output is tested by test/CodeGen/xcore-stringtype.c. 8999276479Sdim/// 9000276479Sdimstatic bool getTypeString(SmallStringEnc &Enc, const Decl *D, 9001276479Sdim CodeGen::CodeGenModule &CGM, TypeStringCache &TSC); 9002276479Sdim 9003276479Sdim/// XCore uses emitTargetMD to emit TypeString metadata for global symbols. 9004276479Sdimvoid XCoreTargetCodeGenInfo::emitTargetMD(const Decl *D, llvm::GlobalValue *GV, 9005276479Sdim CodeGen::CodeGenModule &CGM) const { 9006276479Sdim SmallStringEnc Enc; 9007276479Sdim if (getTypeString(Enc, D, CGM, TSC)) { 9008276479Sdim llvm::LLVMContext &Ctx = CGM.getModule().getContext(); 9009309124Sdim llvm::Metadata *MDVals[] = {llvm::ConstantAsMetadata::get(GV), 9010309124Sdim llvm::MDString::get(Ctx, Enc.str())}; 9011276479Sdim llvm::NamedMDNode *MD = 9012276479Sdim CGM.getModule().getOrInsertNamedMetadata("xcore.typestrings"); 9013276479Sdim MD->addOperand(llvm::MDNode::get(Ctx, MDVals)); 9014276479Sdim } 9015276479Sdim} 9016276479Sdim 9017309124Sdim//===----------------------------------------------------------------------===// 9018309124Sdim// SPIR ABI Implementation 9019309124Sdim//===----------------------------------------------------------------------===// 9020309124Sdim 9021309124Sdimnamespace { 9022309124Sdimclass SPIRTargetCodeGenInfo : public TargetCodeGenInfo { 9023309124Sdimpublic: 9024309124Sdim SPIRTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT) 9025309124Sdim : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {} 9026309124Sdim unsigned getOpenCLKernelCallingConv() const override; 9027309124Sdim}; 9028321369Sdim 9029309124Sdim} // End anonymous namespace. 9030309124Sdim 9031321369Sdimnamespace clang { 9032321369Sdimnamespace CodeGen { 9033321369Sdimvoid computeSPIRKernelABIInfo(CodeGenModule &CGM, CGFunctionInfo &FI) { 9034321369Sdim DefaultABIInfo SPIRABI(CGM.getTypes()); 9035321369Sdim SPIRABI.computeInfo(FI); 9036314564Sdim} 9037309124Sdim} 9038321369Sdim} 9039309124Sdim 9040309124Sdimunsigned SPIRTargetCodeGenInfo::getOpenCLKernelCallingConv() const { 9041309124Sdim return llvm::CallingConv::SPIR_KERNEL; 9042309124Sdim} 9043309124Sdim 9044276479Sdimstatic bool appendType(SmallStringEnc &Enc, QualType QType, 9045276479Sdim const CodeGen::CodeGenModule &CGM, 9046276479Sdim TypeStringCache &TSC); 9047276479Sdim 9048276479Sdim/// Helper function for appendRecordType(). 9049288943Sdim/// Builds a SmallVector containing the encoded field types in declaration 9050288943Sdim/// order. 9051276479Sdimstatic bool extractFieldType(SmallVectorImpl<FieldEncoding> &FE, 9052276479Sdim const RecordDecl *RD, 9053276479Sdim const CodeGen::CodeGenModule &CGM, 9054276479Sdim TypeStringCache &TSC) { 9055280031Sdim for (const auto *Field : RD->fields()) { 9056276479Sdim SmallStringEnc Enc; 9057276479Sdim Enc += "m("; 9058280031Sdim Enc += Field->getName(); 9059276479Sdim Enc += "){"; 9060280031Sdim if (Field->isBitField()) { 9061276479Sdim Enc += "b("; 9062276479Sdim llvm::raw_svector_ostream OS(Enc); 9063280031Sdim OS << Field->getBitWidthValue(CGM.getContext()); 9064276479Sdim Enc += ':'; 9065276479Sdim } 9066280031Sdim if (!appendType(Enc, Field->getType(), CGM, TSC)) 9067276479Sdim return false; 9068280031Sdim if (Field->isBitField()) 9069276479Sdim Enc += ')'; 9070276479Sdim Enc += '}'; 9071288943Sdim FE.emplace_back(!Field->getName().empty(), Enc); 9072276479Sdim } 9073276479Sdim return true; 9074276479Sdim} 9075276479Sdim 9076276479Sdim/// Appends structure and union types to Enc and adds encoding to cache. 9077276479Sdim/// Recursively calls appendType (via extractFieldType) for each field. 9078276479Sdim/// Union types have their fields ordered according to the ABI. 9079276479Sdimstatic bool appendRecordType(SmallStringEnc &Enc, const RecordType *RT, 9080276479Sdim const CodeGen::CodeGenModule &CGM, 9081276479Sdim TypeStringCache &TSC, const IdentifierInfo *ID) { 9082276479Sdim // Append the cached TypeString if we have one. 9083276479Sdim StringRef TypeString = TSC.lookupStr(ID); 9084276479Sdim if (!TypeString.empty()) { 9085276479Sdim Enc += TypeString; 9086276479Sdim return true; 9087276479Sdim } 9088276479Sdim 9089276479Sdim // Start to emit an incomplete TypeString. 9090276479Sdim size_t Start = Enc.size(); 9091276479Sdim Enc += (RT->isUnionType()? 'u' : 's'); 9092276479Sdim Enc += '('; 9093276479Sdim if (ID) 9094276479Sdim Enc += ID->getName(); 9095276479Sdim Enc += "){"; 9096276479Sdim 9097276479Sdim // We collect all encoded fields and order as necessary. 9098276479Sdim bool IsRecursive = false; 9099276479Sdim const RecordDecl *RD = RT->getDecl()->getDefinition(); 9100276479Sdim if (RD && !RD->field_empty()) { 9101276479Sdim // An incomplete TypeString stub is placed in the cache for this RecordType 9102276479Sdim // so that recursive calls to this RecordType will use it whilst building a 9103276479Sdim // complete TypeString for this RecordType. 9104276479Sdim SmallVector<FieldEncoding, 16> FE; 9105276479Sdim std::string StubEnc(Enc.substr(Start).str()); 9106276479Sdim StubEnc += '}'; // StubEnc now holds a valid incomplete TypeString. 9107276479Sdim TSC.addIncomplete(ID, std::move(StubEnc)); 9108276479Sdim if (!extractFieldType(FE, RD, CGM, TSC)) { 9109276479Sdim (void) TSC.removeIncomplete(ID); 9110276479Sdim return false; 9111276479Sdim } 9112276479Sdim IsRecursive = TSC.removeIncomplete(ID); 9113276479Sdim // The ABI requires unions to be sorted but not structures. 9114276479Sdim // See FieldEncoding::operator< for sort algorithm. 9115276479Sdim if (RT->isUnionType()) 9116344779Sdim llvm::sort(FE); 9117276479Sdim // We can now complete the TypeString. 9118276479Sdim unsigned E = FE.size(); 9119276479Sdim for (unsigned I = 0; I != E; ++I) { 9120276479Sdim if (I) 9121276479Sdim Enc += ','; 9122276479Sdim Enc += FE[I].str(); 9123276479Sdim } 9124276479Sdim } 9125276479Sdim Enc += '}'; 9126276479Sdim TSC.addIfComplete(ID, Enc.substr(Start), IsRecursive); 9127276479Sdim return true; 9128276479Sdim} 9129276479Sdim 9130276479Sdim/// Appends enum types to Enc and adds the encoding to the cache. 9131276479Sdimstatic bool appendEnumType(SmallStringEnc &Enc, const EnumType *ET, 9132276479Sdim TypeStringCache &TSC, 9133276479Sdim const IdentifierInfo *ID) { 9134276479Sdim // Append the cached TypeString if we have one. 9135276479Sdim StringRef TypeString = TSC.lookupStr(ID); 9136276479Sdim if (!TypeString.empty()) { 9137276479Sdim Enc += TypeString; 9138276479Sdim return true; 9139276479Sdim } 9140276479Sdim 9141276479Sdim size_t Start = Enc.size(); 9142276479Sdim Enc += "e("; 9143276479Sdim if (ID) 9144276479Sdim Enc += ID->getName(); 9145276479Sdim Enc += "){"; 9146276479Sdim 9147276479Sdim // We collect all encoded enumerations and order them alphanumerically. 9148276479Sdim if (const EnumDecl *ED = ET->getDecl()->getDefinition()) { 9149276479Sdim SmallVector<FieldEncoding, 16> FE; 9150276479Sdim for (auto I = ED->enumerator_begin(), E = ED->enumerator_end(); I != E; 9151276479Sdim ++I) { 9152276479Sdim SmallStringEnc EnumEnc; 9153276479Sdim EnumEnc += "m("; 9154276479Sdim EnumEnc += I->getName(); 9155276479Sdim EnumEnc += "){"; 9156276479Sdim I->getInitVal().toString(EnumEnc); 9157276479Sdim EnumEnc += '}'; 9158276479Sdim FE.push_back(FieldEncoding(!I->getName().empty(), EnumEnc)); 9159276479Sdim } 9160344779Sdim llvm::sort(FE); 9161276479Sdim unsigned E = FE.size(); 9162276479Sdim for (unsigned I = 0; I != E; ++I) { 9163276479Sdim if (I) 9164276479Sdim Enc += ','; 9165276479Sdim Enc += FE[I].str(); 9166276479Sdim } 9167276479Sdim } 9168276479Sdim Enc += '}'; 9169276479Sdim TSC.addIfComplete(ID, Enc.substr(Start), false); 9170276479Sdim return true; 9171276479Sdim} 9172276479Sdim 9173276479Sdim/// Appends type's qualifier to Enc. 9174276479Sdim/// This is done prior to appending the type's encoding. 9175276479Sdimstatic void appendQualifier(SmallStringEnc &Enc, QualType QT) { 9176276479Sdim // Qualifiers are emitted in alphabetical order. 9177296417Sdim static const char *const Table[]={"","c:","r:","cr:","v:","cv:","rv:","crv:"}; 9178276479Sdim int Lookup = 0; 9179276479Sdim if (QT.isConstQualified()) 9180276479Sdim Lookup += 1<<0; 9181276479Sdim if (QT.isRestrictQualified()) 9182276479Sdim Lookup += 1<<1; 9183276479Sdim if (QT.isVolatileQualified()) 9184276479Sdim Lookup += 1<<2; 9185276479Sdim Enc += Table[Lookup]; 9186276479Sdim} 9187276479Sdim 9188276479Sdim/// Appends built-in types to Enc. 9189276479Sdimstatic bool appendBuiltinType(SmallStringEnc &Enc, const BuiltinType *BT) { 9190276479Sdim const char *EncType; 9191276479Sdim switch (BT->getKind()) { 9192276479Sdim case BuiltinType::Void: 9193276479Sdim EncType = "0"; 9194276479Sdim break; 9195276479Sdim case BuiltinType::Bool: 9196276479Sdim EncType = "b"; 9197276479Sdim break; 9198276479Sdim case BuiltinType::Char_U: 9199276479Sdim EncType = "uc"; 9200276479Sdim break; 9201276479Sdim case BuiltinType::UChar: 9202276479Sdim EncType = "uc"; 9203276479Sdim break; 9204276479Sdim case BuiltinType::SChar: 9205276479Sdim EncType = "sc"; 9206276479Sdim break; 9207276479Sdim case BuiltinType::UShort: 9208276479Sdim EncType = "us"; 9209276479Sdim break; 9210276479Sdim case BuiltinType::Short: 9211276479Sdim EncType = "ss"; 9212276479Sdim break; 9213276479Sdim case BuiltinType::UInt: 9214276479Sdim EncType = "ui"; 9215276479Sdim break; 9216276479Sdim case BuiltinType::Int: 9217276479Sdim EncType = "si"; 9218276479Sdim break; 9219276479Sdim case BuiltinType::ULong: 9220276479Sdim EncType = "ul"; 9221276479Sdim break; 9222276479Sdim case BuiltinType::Long: 9223276479Sdim EncType = "sl"; 9224276479Sdim break; 9225276479Sdim case BuiltinType::ULongLong: 9226276479Sdim EncType = "ull"; 9227276479Sdim break; 9228276479Sdim case BuiltinType::LongLong: 9229276479Sdim EncType = "sll"; 9230276479Sdim break; 9231276479Sdim case BuiltinType::Float: 9232276479Sdim EncType = "ft"; 9233276479Sdim break; 9234276479Sdim case BuiltinType::Double: 9235276479Sdim EncType = "d"; 9236276479Sdim break; 9237276479Sdim case BuiltinType::LongDouble: 9238276479Sdim EncType = "ld"; 9239276479Sdim break; 9240276479Sdim default: 9241276479Sdim return false; 9242276479Sdim } 9243276479Sdim Enc += EncType; 9244276479Sdim return true; 9245276479Sdim} 9246276479Sdim 9247276479Sdim/// Appends a pointer encoding to Enc before calling appendType for the pointee. 9248276479Sdimstatic bool appendPointerType(SmallStringEnc &Enc, const PointerType *PT, 9249276479Sdim const CodeGen::CodeGenModule &CGM, 9250276479Sdim TypeStringCache &TSC) { 9251276479Sdim Enc += "p("; 9252276479Sdim if (!appendType(Enc, PT->getPointeeType(), CGM, TSC)) 9253276479Sdim return false; 9254276479Sdim Enc += ')'; 9255276479Sdim return true; 9256276479Sdim} 9257276479Sdim 9258276479Sdim/// Appends array encoding to Enc before calling appendType for the element. 9259276479Sdimstatic bool appendArrayType(SmallStringEnc &Enc, QualType QT, 9260276479Sdim const ArrayType *AT, 9261276479Sdim const CodeGen::CodeGenModule &CGM, 9262276479Sdim TypeStringCache &TSC, StringRef NoSizeEnc) { 9263276479Sdim if (AT->getSizeModifier() != ArrayType::Normal) 9264276479Sdim return false; 9265276479Sdim Enc += "a("; 9266276479Sdim if (const ConstantArrayType *CAT = dyn_cast<ConstantArrayType>(AT)) 9267276479Sdim CAT->getSize().toStringUnsigned(Enc); 9268276479Sdim else 9269276479Sdim Enc += NoSizeEnc; // Global arrays use "*", otherwise it is "". 9270276479Sdim Enc += ':'; 9271276479Sdim // The Qualifiers should be attached to the type rather than the array. 9272276479Sdim appendQualifier(Enc, QT); 9273276479Sdim if (!appendType(Enc, AT->getElementType(), CGM, TSC)) 9274276479Sdim return false; 9275276479Sdim Enc += ')'; 9276276479Sdim return true; 9277276479Sdim} 9278276479Sdim 9279276479Sdim/// Appends a function encoding to Enc, calling appendType for the return type 9280276479Sdim/// and the arguments. 9281276479Sdimstatic bool appendFunctionType(SmallStringEnc &Enc, const FunctionType *FT, 9282276479Sdim const CodeGen::CodeGenModule &CGM, 9283276479Sdim TypeStringCache &TSC) { 9284276479Sdim Enc += "f{"; 9285276479Sdim if (!appendType(Enc, FT->getReturnType(), CGM, TSC)) 9286276479Sdim return false; 9287276479Sdim Enc += "}("; 9288276479Sdim if (const FunctionProtoType *FPT = FT->getAs<FunctionProtoType>()) { 9289276479Sdim // N.B. we are only interested in the adjusted param types. 9290276479Sdim auto I = FPT->param_type_begin(); 9291276479Sdim auto E = FPT->param_type_end(); 9292276479Sdim if (I != E) { 9293276479Sdim do { 9294276479Sdim if (!appendType(Enc, *I, CGM, TSC)) 9295276479Sdim return false; 9296276479Sdim ++I; 9297276479Sdim if (I != E) 9298276479Sdim Enc += ','; 9299276479Sdim } while (I != E); 9300276479Sdim if (FPT->isVariadic()) 9301276479Sdim Enc += ",va"; 9302276479Sdim } else { 9303276479Sdim if (FPT->isVariadic()) 9304276479Sdim Enc += "va"; 9305276479Sdim else 9306276479Sdim Enc += '0'; 9307276479Sdim } 9308276479Sdim } 9309276479Sdim Enc += ')'; 9310276479Sdim return true; 9311276479Sdim} 9312276479Sdim 9313276479Sdim/// Handles the type's qualifier before dispatching a call to handle specific 9314276479Sdim/// type encodings. 9315276479Sdimstatic bool appendType(SmallStringEnc &Enc, QualType QType, 9316276479Sdim const CodeGen::CodeGenModule &CGM, 9317276479Sdim TypeStringCache &TSC) { 9318276479Sdim 9319276479Sdim QualType QT = QType.getCanonicalType(); 9320276479Sdim 9321276479Sdim if (const ArrayType *AT = QT->getAsArrayTypeUnsafe()) 9322276479Sdim // The Qualifiers should be attached to the type rather than the array. 9323276479Sdim // Thus we don't call appendQualifier() here. 9324276479Sdim return appendArrayType(Enc, QT, AT, CGM, TSC, ""); 9325276479Sdim 9326276479Sdim appendQualifier(Enc, QT); 9327276479Sdim 9328276479Sdim if (const BuiltinType *BT = QT->getAs<BuiltinType>()) 9329276479Sdim return appendBuiltinType(Enc, BT); 9330276479Sdim 9331276479Sdim if (const PointerType *PT = QT->getAs<PointerType>()) 9332276479Sdim return appendPointerType(Enc, PT, CGM, TSC); 9333276479Sdim 9334276479Sdim if (const EnumType *ET = QT->getAs<EnumType>()) 9335276479Sdim return appendEnumType(Enc, ET, TSC, QT.getBaseTypeIdentifier()); 9336276479Sdim 9337276479Sdim if (const RecordType *RT = QT->getAsStructureType()) 9338276479Sdim return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier()); 9339276479Sdim 9340276479Sdim if (const RecordType *RT = QT->getAsUnionType()) 9341276479Sdim return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier()); 9342276479Sdim 9343276479Sdim if (const FunctionType *FT = QT->getAs<FunctionType>()) 9344276479Sdim return appendFunctionType(Enc, FT, CGM, TSC); 9345276479Sdim 9346276479Sdim return false; 9347276479Sdim} 9348276479Sdim 9349276479Sdimstatic bool getTypeString(SmallStringEnc &Enc, const Decl *D, 9350276479Sdim CodeGen::CodeGenModule &CGM, TypeStringCache &TSC) { 9351276479Sdim if (!D) 9352276479Sdim return false; 9353276479Sdim 9354276479Sdim if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) { 9355276479Sdim if (FD->getLanguageLinkage() != CLanguageLinkage) 9356276479Sdim return false; 9357276479Sdim return appendType(Enc, FD->getType(), CGM, TSC); 9358276479Sdim } 9359276479Sdim 9360276479Sdim if (const VarDecl *VD = dyn_cast<VarDecl>(D)) { 9361276479Sdim if (VD->getLanguageLinkage() != CLanguageLinkage) 9362276479Sdim return false; 9363276479Sdim QualType QT = VD->getType().getCanonicalType(); 9364276479Sdim if (const ArrayType *AT = QT->getAsArrayTypeUnsafe()) { 9365276479Sdim // Global ArrayTypes are given a size of '*' if the size is unknown. 9366276479Sdim // The Qualifiers should be attached to the type rather than the array. 9367276479Sdim // Thus we don't call appendQualifier() here. 9368276479Sdim return appendArrayType(Enc, QT, AT, CGM, TSC, "*"); 9369276479Sdim } 9370276479Sdim return appendType(Enc, QT, CGM, TSC); 9371276479Sdim } 9372276479Sdim return false; 9373276479Sdim} 9374276479Sdim 9375341825Sdim//===----------------------------------------------------------------------===// 9376341825Sdim// RISCV ABI Implementation 9377341825Sdim//===----------------------------------------------------------------------===// 9378276479Sdim 9379341825Sdimnamespace { 9380341825Sdimclass RISCVABIInfo : public DefaultABIInfo { 9381341825Sdimprivate: 9382353358Sdim // Size of the integer ('x') registers in bits. 9383353358Sdim unsigned XLen; 9384353358Sdim // Size of the floating point ('f') registers in bits. Note that the target 9385353358Sdim // ISA might have a wider FLen than the selected ABI (e.g. an RV32IF target 9386353358Sdim // with soft float ABI has FLen==0). 9387353358Sdim unsigned FLen; 9388341825Sdim static const int NumArgGPRs = 8; 9389353358Sdim static const int NumArgFPRs = 8; 9390353358Sdim bool detectFPCCEligibleStructHelper(QualType Ty, CharUnits CurOff, 9391353358Sdim llvm::Type *&Field1Ty, 9392353358Sdim CharUnits &Field1Off, 9393353358Sdim llvm::Type *&Field2Ty, 9394353358Sdim CharUnits &Field2Off) const; 9395341825Sdim 9396341825Sdimpublic: 9397353358Sdim RISCVABIInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen, unsigned FLen) 9398353358Sdim : DefaultABIInfo(CGT), XLen(XLen), FLen(FLen) {} 9399341825Sdim 9400341825Sdim // DefaultABIInfo's classifyReturnType and classifyArgumentType are 9401341825Sdim // non-virtual, but computeInfo is virtual, so we overload it. 9402341825Sdim void computeInfo(CGFunctionInfo &FI) const override; 9403341825Sdim 9404353358Sdim ABIArgInfo classifyArgumentType(QualType Ty, bool IsFixed, int &ArgGPRsLeft, 9405353358Sdim int &ArgFPRsLeft) const; 9406341825Sdim ABIArgInfo classifyReturnType(QualType RetTy) const; 9407341825Sdim 9408341825Sdim Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 9409341825Sdim QualType Ty) const override; 9410341825Sdim 9411341825Sdim ABIArgInfo extendType(QualType Ty) const; 9412353358Sdim 9413353358Sdim bool detectFPCCEligibleStruct(QualType Ty, llvm::Type *&Field1Ty, 9414353358Sdim CharUnits &Field1Off, llvm::Type *&Field2Ty, 9415353358Sdim CharUnits &Field2Off, int &NeededArgGPRs, 9416353358Sdim int &NeededArgFPRs) const; 9417353358Sdim ABIArgInfo coerceAndExpandFPCCEligibleStruct(llvm::Type *Field1Ty, 9418353358Sdim CharUnits Field1Off, 9419353358Sdim llvm::Type *Field2Ty, 9420353358Sdim CharUnits Field2Off) const; 9421341825Sdim}; 9422341825Sdim} // end anonymous namespace 9423341825Sdim 9424341825Sdimvoid RISCVABIInfo::computeInfo(CGFunctionInfo &FI) const { 9425341825Sdim QualType RetTy = FI.getReturnType(); 9426341825Sdim if (!getCXXABI().classifyReturnType(FI)) 9427341825Sdim FI.getReturnInfo() = classifyReturnType(RetTy); 9428341825Sdim 9429341825Sdim // IsRetIndirect is true if classifyArgumentType indicated the value should 9430360784Sdim // be passed indirect, or if the type size is a scalar greater than 2*XLen 9431360784Sdim // and not a complex type with elements <= FLen. e.g. fp128 is passed direct 9432360784Sdim // in LLVM IR, relying on the backend lowering code to rewrite the argument 9433360784Sdim // list and pass indirectly on RV32. 9434360784Sdim bool IsRetIndirect = FI.getReturnInfo().getKind() == ABIArgInfo::Indirect; 9435360784Sdim if (!IsRetIndirect && RetTy->isScalarType() && 9436360784Sdim getContext().getTypeSize(RetTy) > (2 * XLen)) { 9437360784Sdim if (RetTy->isComplexType() && FLen) { 9438360784Sdim QualType EltTy = RetTy->getAs<ComplexType>()->getElementType(); 9439360784Sdim IsRetIndirect = getContext().getTypeSize(EltTy) > FLen; 9440360784Sdim } else { 9441360784Sdim // This is a normal scalar > 2*XLen, such as fp128 on RV32. 9442360784Sdim IsRetIndirect = true; 9443360784Sdim } 9444360784Sdim } 9445341825Sdim 9446341825Sdim // We must track the number of GPRs used in order to conform to the RISC-V 9447341825Sdim // ABI, as integer scalars passed in registers should have signext/zeroext 9448341825Sdim // when promoted, but are anyext if passed on the stack. As GPR usage is 9449341825Sdim // different for variadic arguments, we must also track whether we are 9450341825Sdim // examining a vararg or not. 9451341825Sdim int ArgGPRsLeft = IsRetIndirect ? NumArgGPRs - 1 : NumArgGPRs; 9452353358Sdim int ArgFPRsLeft = FLen ? NumArgFPRs : 0; 9453341825Sdim int NumFixedArgs = FI.getNumRequiredArgs(); 9454341825Sdim 9455341825Sdim int ArgNum = 0; 9456341825Sdim for (auto &ArgInfo : FI.arguments()) { 9457341825Sdim bool IsFixed = ArgNum < NumFixedArgs; 9458353358Sdim ArgInfo.info = 9459353358Sdim classifyArgumentType(ArgInfo.type, IsFixed, ArgGPRsLeft, ArgFPRsLeft); 9460341825Sdim ArgNum++; 9461341825Sdim } 9462341825Sdim} 9463341825Sdim 9464353358Sdim// Returns true if the struct is a potential candidate for the floating point 9465353358Sdim// calling convention. If this function returns true, the caller is 9466353358Sdim// responsible for checking that if there is only a single field then that 9467353358Sdim// field is a float. 9468353358Sdimbool RISCVABIInfo::detectFPCCEligibleStructHelper(QualType Ty, CharUnits CurOff, 9469353358Sdim llvm::Type *&Field1Ty, 9470353358Sdim CharUnits &Field1Off, 9471353358Sdim llvm::Type *&Field2Ty, 9472353358Sdim CharUnits &Field2Off) const { 9473353358Sdim bool IsInt = Ty->isIntegralOrEnumerationType(); 9474353358Sdim bool IsFloat = Ty->isRealFloatingType(); 9475353358Sdim 9476353358Sdim if (IsInt || IsFloat) { 9477353358Sdim uint64_t Size = getContext().getTypeSize(Ty); 9478353358Sdim if (IsInt && Size > XLen) 9479353358Sdim return false; 9480353358Sdim // Can't be eligible if larger than the FP registers. Half precision isn't 9481353358Sdim // currently supported on RISC-V and the ABI hasn't been confirmed, so 9482353358Sdim // default to the integer ABI in that case. 9483353358Sdim if (IsFloat && (Size > FLen || Size < 32)) 9484353358Sdim return false; 9485353358Sdim // Can't be eligible if an integer type was already found (int+int pairs 9486353358Sdim // are not eligible). 9487353358Sdim if (IsInt && Field1Ty && Field1Ty->isIntegerTy()) 9488353358Sdim return false; 9489353358Sdim if (!Field1Ty) { 9490353358Sdim Field1Ty = CGT.ConvertType(Ty); 9491353358Sdim Field1Off = CurOff; 9492353358Sdim return true; 9493353358Sdim } 9494353358Sdim if (!Field2Ty) { 9495353358Sdim Field2Ty = CGT.ConvertType(Ty); 9496353358Sdim Field2Off = CurOff; 9497353358Sdim return true; 9498353358Sdim } 9499353358Sdim return false; 9500353358Sdim } 9501353358Sdim 9502353358Sdim if (auto CTy = Ty->getAs<ComplexType>()) { 9503353358Sdim if (Field1Ty) 9504353358Sdim return false; 9505353358Sdim QualType EltTy = CTy->getElementType(); 9506353358Sdim if (getContext().getTypeSize(EltTy) > FLen) 9507353358Sdim return false; 9508353358Sdim Field1Ty = CGT.ConvertType(EltTy); 9509353358Sdim Field1Off = CurOff; 9510353358Sdim assert(CurOff.isZero() && "Unexpected offset for first field"); 9511353358Sdim Field2Ty = Field1Ty; 9512353358Sdim Field2Off = Field1Off + getContext().getTypeSizeInChars(EltTy); 9513353358Sdim return true; 9514353358Sdim } 9515353358Sdim 9516353358Sdim if (const ConstantArrayType *ATy = getContext().getAsConstantArrayType(Ty)) { 9517353358Sdim uint64_t ArraySize = ATy->getSize().getZExtValue(); 9518353358Sdim QualType EltTy = ATy->getElementType(); 9519353358Sdim CharUnits EltSize = getContext().getTypeSizeInChars(EltTy); 9520353358Sdim for (uint64_t i = 0; i < ArraySize; ++i) { 9521353358Sdim bool Ret = detectFPCCEligibleStructHelper(EltTy, CurOff, Field1Ty, 9522353358Sdim Field1Off, Field2Ty, Field2Off); 9523353358Sdim if (!Ret) 9524353358Sdim return false; 9525353358Sdim CurOff += EltSize; 9526353358Sdim } 9527353358Sdim return true; 9528353358Sdim } 9529353358Sdim 9530353358Sdim if (const auto *RTy = Ty->getAs<RecordType>()) { 9531353358Sdim // Structures with either a non-trivial destructor or a non-trivial 9532353358Sdim // copy constructor are not eligible for the FP calling convention. 9533360784Sdim if (getRecordArgABI(Ty, CGT.getCXXABI())) 9534353358Sdim return false; 9535353358Sdim if (isEmptyRecord(getContext(), Ty, true)) 9536353358Sdim return true; 9537353358Sdim const RecordDecl *RD = RTy->getDecl(); 9538353358Sdim // Unions aren't eligible unless they're empty (which is caught above). 9539353358Sdim if (RD->isUnion()) 9540353358Sdim return false; 9541353358Sdim int ZeroWidthBitFieldCount = 0; 9542353358Sdim for (const FieldDecl *FD : RD->fields()) { 9543353358Sdim const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD); 9544353358Sdim uint64_t FieldOffInBits = Layout.getFieldOffset(FD->getFieldIndex()); 9545353358Sdim QualType QTy = FD->getType(); 9546353358Sdim if (FD->isBitField()) { 9547353358Sdim unsigned BitWidth = FD->getBitWidthValue(getContext()); 9548353358Sdim // Allow a bitfield with a type greater than XLen as long as the 9549353358Sdim // bitwidth is XLen or less. 9550353358Sdim if (getContext().getTypeSize(QTy) > XLen && BitWidth <= XLen) 9551353358Sdim QTy = getContext().getIntTypeForBitwidth(XLen, false); 9552353358Sdim if (BitWidth == 0) { 9553353358Sdim ZeroWidthBitFieldCount++; 9554353358Sdim continue; 9555353358Sdim } 9556353358Sdim } 9557353358Sdim 9558353358Sdim bool Ret = detectFPCCEligibleStructHelper( 9559353358Sdim QTy, CurOff + getContext().toCharUnitsFromBits(FieldOffInBits), 9560353358Sdim Field1Ty, Field1Off, Field2Ty, Field2Off); 9561353358Sdim if (!Ret) 9562353358Sdim return false; 9563353358Sdim 9564353358Sdim // As a quirk of the ABI, zero-width bitfields aren't ignored for fp+fp 9565353358Sdim // or int+fp structs, but are ignored for a struct with an fp field and 9566353358Sdim // any number of zero-width bitfields. 9567353358Sdim if (Field2Ty && ZeroWidthBitFieldCount > 0) 9568353358Sdim return false; 9569353358Sdim } 9570353358Sdim return Field1Ty != nullptr; 9571353358Sdim } 9572353358Sdim 9573353358Sdim return false; 9574353358Sdim} 9575353358Sdim 9576353358Sdim// Determine if a struct is eligible for passing according to the floating 9577353358Sdim// point calling convention (i.e., when flattened it contains a single fp 9578353358Sdim// value, fp+fp, or int+fp of appropriate size). If so, NeededArgFPRs and 9579353358Sdim// NeededArgGPRs are incremented appropriately. 9580353358Sdimbool RISCVABIInfo::detectFPCCEligibleStruct(QualType Ty, llvm::Type *&Field1Ty, 9581353358Sdim CharUnits &Field1Off, 9582353358Sdim llvm::Type *&Field2Ty, 9583353358Sdim CharUnits &Field2Off, 9584353358Sdim int &NeededArgGPRs, 9585353358Sdim int &NeededArgFPRs) const { 9586353358Sdim Field1Ty = nullptr; 9587353358Sdim Field2Ty = nullptr; 9588353358Sdim NeededArgGPRs = 0; 9589353358Sdim NeededArgFPRs = 0; 9590353358Sdim bool IsCandidate = detectFPCCEligibleStructHelper( 9591353358Sdim Ty, CharUnits::Zero(), Field1Ty, Field1Off, Field2Ty, Field2Off); 9592353358Sdim // Not really a candidate if we have a single int but no float. 9593353358Sdim if (Field1Ty && !Field2Ty && !Field1Ty->isFloatingPointTy()) 9594360784Sdim return false; 9595353358Sdim if (!IsCandidate) 9596353358Sdim return false; 9597353358Sdim if (Field1Ty && Field1Ty->isFloatingPointTy()) 9598353358Sdim NeededArgFPRs++; 9599353358Sdim else if (Field1Ty) 9600353358Sdim NeededArgGPRs++; 9601353358Sdim if (Field2Ty && Field2Ty->isFloatingPointTy()) 9602353358Sdim NeededArgFPRs++; 9603353358Sdim else if (Field2Ty) 9604353358Sdim NeededArgGPRs++; 9605353358Sdim return IsCandidate; 9606353358Sdim} 9607353358Sdim 9608353358Sdim// Call getCoerceAndExpand for the two-element flattened struct described by 9609353358Sdim// Field1Ty, Field1Off, Field2Ty, Field2Off. This method will create an 9610353358Sdim// appropriate coerceToType and unpaddedCoerceToType. 9611353358SdimABIArgInfo RISCVABIInfo::coerceAndExpandFPCCEligibleStruct( 9612353358Sdim llvm::Type *Field1Ty, CharUnits Field1Off, llvm::Type *Field2Ty, 9613353358Sdim CharUnits Field2Off) const { 9614353358Sdim SmallVector<llvm::Type *, 3> CoerceElts; 9615353358Sdim SmallVector<llvm::Type *, 2> UnpaddedCoerceElts; 9616353358Sdim if (!Field1Off.isZero()) 9617353358Sdim CoerceElts.push_back(llvm::ArrayType::get( 9618353358Sdim llvm::Type::getInt8Ty(getVMContext()), Field1Off.getQuantity())); 9619353358Sdim 9620353358Sdim CoerceElts.push_back(Field1Ty); 9621353358Sdim UnpaddedCoerceElts.push_back(Field1Ty); 9622353358Sdim 9623353358Sdim if (!Field2Ty) { 9624353358Sdim return ABIArgInfo::getCoerceAndExpand( 9625353358Sdim llvm::StructType::get(getVMContext(), CoerceElts, !Field1Off.isZero()), 9626353358Sdim UnpaddedCoerceElts[0]); 9627353358Sdim } 9628353358Sdim 9629353358Sdim CharUnits Field2Align = 9630353358Sdim CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(Field2Ty)); 9631353358Sdim CharUnits Field1Size = 9632353358Sdim CharUnits::fromQuantity(getDataLayout().getTypeStoreSize(Field1Ty)); 9633353358Sdim CharUnits Field2OffNoPadNoPack = Field1Size.alignTo(Field2Align); 9634353358Sdim 9635353358Sdim CharUnits Padding = CharUnits::Zero(); 9636353358Sdim if (Field2Off > Field2OffNoPadNoPack) 9637353358Sdim Padding = Field2Off - Field2OffNoPadNoPack; 9638353358Sdim else if (Field2Off != Field2Align && Field2Off > Field1Size) 9639353358Sdim Padding = Field2Off - Field1Size; 9640353358Sdim 9641353358Sdim bool IsPacked = !Field2Off.isMultipleOf(Field2Align); 9642353358Sdim 9643353358Sdim if (!Padding.isZero()) 9644353358Sdim CoerceElts.push_back(llvm::ArrayType::get( 9645353358Sdim llvm::Type::getInt8Ty(getVMContext()), Padding.getQuantity())); 9646353358Sdim 9647353358Sdim CoerceElts.push_back(Field2Ty); 9648353358Sdim UnpaddedCoerceElts.push_back(Field2Ty); 9649353358Sdim 9650353358Sdim auto CoerceToType = 9651353358Sdim llvm::StructType::get(getVMContext(), CoerceElts, IsPacked); 9652353358Sdim auto UnpaddedCoerceToType = 9653353358Sdim llvm::StructType::get(getVMContext(), UnpaddedCoerceElts, IsPacked); 9654353358Sdim 9655353358Sdim return ABIArgInfo::getCoerceAndExpand(CoerceToType, UnpaddedCoerceToType); 9656353358Sdim} 9657353358Sdim 9658341825SdimABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed, 9659353358Sdim int &ArgGPRsLeft, 9660353358Sdim int &ArgFPRsLeft) const { 9661341825Sdim assert(ArgGPRsLeft <= NumArgGPRs && "Arg GPR tracking underflow"); 9662341825Sdim Ty = useFirstFieldIfTransparentUnion(Ty); 9663341825Sdim 9664341825Sdim // Structures with either a non-trivial destructor or a non-trivial 9665341825Sdim // copy constructor are always passed indirectly. 9666341825Sdim if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) { 9667341825Sdim if (ArgGPRsLeft) 9668341825Sdim ArgGPRsLeft -= 1; 9669341825Sdim return getNaturalAlignIndirect(Ty, /*ByVal=*/RAA == 9670341825Sdim CGCXXABI::RAA_DirectInMemory); 9671341825Sdim } 9672341825Sdim 9673341825Sdim // Ignore empty structs/unions. 9674341825Sdim if (isEmptyRecord(getContext(), Ty, true)) 9675341825Sdim return ABIArgInfo::getIgnore(); 9676341825Sdim 9677341825Sdim uint64_t Size = getContext().getTypeSize(Ty); 9678353358Sdim 9679353358Sdim // Pass floating point values via FPRs if possible. 9680363496Sdim if (IsFixed && Ty->isFloatingType() && !Ty->isComplexType() && 9681363496Sdim FLen >= Size && ArgFPRsLeft) { 9682353358Sdim ArgFPRsLeft--; 9683353358Sdim return ABIArgInfo::getDirect(); 9684353358Sdim } 9685353358Sdim 9686353358Sdim // Complex types for the hard float ABI must be passed direct rather than 9687353358Sdim // using CoerceAndExpand. 9688353358Sdim if (IsFixed && Ty->isComplexType() && FLen && ArgFPRsLeft >= 2) { 9689360784Sdim QualType EltTy = Ty->castAs<ComplexType>()->getElementType(); 9690353358Sdim if (getContext().getTypeSize(EltTy) <= FLen) { 9691353358Sdim ArgFPRsLeft -= 2; 9692353358Sdim return ABIArgInfo::getDirect(); 9693353358Sdim } 9694353358Sdim } 9695353358Sdim 9696353358Sdim if (IsFixed && FLen && Ty->isStructureOrClassType()) { 9697353358Sdim llvm::Type *Field1Ty = nullptr; 9698353358Sdim llvm::Type *Field2Ty = nullptr; 9699353358Sdim CharUnits Field1Off = CharUnits::Zero(); 9700353358Sdim CharUnits Field2Off = CharUnits::Zero(); 9701353358Sdim int NeededArgGPRs; 9702353358Sdim int NeededArgFPRs; 9703353358Sdim bool IsCandidate = 9704353358Sdim detectFPCCEligibleStruct(Ty, Field1Ty, Field1Off, Field2Ty, Field2Off, 9705353358Sdim NeededArgGPRs, NeededArgFPRs); 9706353358Sdim if (IsCandidate && NeededArgGPRs <= ArgGPRsLeft && 9707353358Sdim NeededArgFPRs <= ArgFPRsLeft) { 9708353358Sdim ArgGPRsLeft -= NeededArgGPRs; 9709353358Sdim ArgFPRsLeft -= NeededArgFPRs; 9710353358Sdim return coerceAndExpandFPCCEligibleStruct(Field1Ty, Field1Off, Field2Ty, 9711353358Sdim Field2Off); 9712353358Sdim } 9713353358Sdim } 9714353358Sdim 9715341825Sdim uint64_t NeededAlign = getContext().getTypeAlign(Ty); 9716341825Sdim bool MustUseStack = false; 9717341825Sdim // Determine the number of GPRs needed to pass the current argument 9718341825Sdim // according to the ABI. 2*XLen-aligned varargs are passed in "aligned" 9719341825Sdim // register pairs, so may consume 3 registers. 9720341825Sdim int NeededArgGPRs = 1; 9721341825Sdim if (!IsFixed && NeededAlign == 2 * XLen) 9722341825Sdim NeededArgGPRs = 2 + (ArgGPRsLeft % 2); 9723341825Sdim else if (Size > XLen && Size <= 2 * XLen) 9724341825Sdim NeededArgGPRs = 2; 9725341825Sdim 9726341825Sdim if (NeededArgGPRs > ArgGPRsLeft) { 9727341825Sdim MustUseStack = true; 9728341825Sdim NeededArgGPRs = ArgGPRsLeft; 9729341825Sdim } 9730341825Sdim 9731341825Sdim ArgGPRsLeft -= NeededArgGPRs; 9732341825Sdim 9733341825Sdim if (!isAggregateTypeForABI(Ty) && !Ty->isVectorType()) { 9734341825Sdim // Treat an enum type as its underlying type. 9735341825Sdim if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 9736341825Sdim Ty = EnumTy->getDecl()->getIntegerType(); 9737341825Sdim 9738341825Sdim // All integral types are promoted to XLen width, unless passed on the 9739341825Sdim // stack. 9740341825Sdim if (Size < XLen && Ty->isIntegralOrEnumerationType() && !MustUseStack) { 9741341825Sdim return extendType(Ty); 9742341825Sdim } 9743341825Sdim 9744341825Sdim return ABIArgInfo::getDirect(); 9745341825Sdim } 9746341825Sdim 9747341825Sdim // Aggregates which are <= 2*XLen will be passed in registers if possible, 9748341825Sdim // so coerce to integers. 9749341825Sdim if (Size <= 2 * XLen) { 9750341825Sdim unsigned Alignment = getContext().getTypeAlign(Ty); 9751341825Sdim 9752341825Sdim // Use a single XLen int if possible, 2*XLen if 2*XLen alignment is 9753341825Sdim // required, and a 2-element XLen array if only XLen alignment is required. 9754341825Sdim if (Size <= XLen) { 9755341825Sdim return ABIArgInfo::getDirect( 9756341825Sdim llvm::IntegerType::get(getVMContext(), XLen)); 9757341825Sdim } else if (Alignment == 2 * XLen) { 9758341825Sdim return ABIArgInfo::getDirect( 9759341825Sdim llvm::IntegerType::get(getVMContext(), 2 * XLen)); 9760341825Sdim } else { 9761341825Sdim return ABIArgInfo::getDirect(llvm::ArrayType::get( 9762341825Sdim llvm::IntegerType::get(getVMContext(), XLen), 2)); 9763341825Sdim } 9764341825Sdim } 9765341825Sdim return getNaturalAlignIndirect(Ty, /*ByVal=*/false); 9766341825Sdim} 9767341825Sdim 9768341825SdimABIArgInfo RISCVABIInfo::classifyReturnType(QualType RetTy) const { 9769341825Sdim if (RetTy->isVoidType()) 9770341825Sdim return ABIArgInfo::getIgnore(); 9771341825Sdim 9772341825Sdim int ArgGPRsLeft = 2; 9773353358Sdim int ArgFPRsLeft = FLen ? 2 : 0; 9774341825Sdim 9775341825Sdim // The rules for return and argument types are the same, so defer to 9776341825Sdim // classifyArgumentType. 9777353358Sdim return classifyArgumentType(RetTy, /*IsFixed=*/true, ArgGPRsLeft, 9778353358Sdim ArgFPRsLeft); 9779341825Sdim} 9780341825Sdim 9781341825SdimAddress RISCVABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, 9782341825Sdim QualType Ty) const { 9783341825Sdim CharUnits SlotSize = CharUnits::fromQuantity(XLen / 8); 9784341825Sdim 9785341825Sdim // Empty records are ignored for parameter passing purposes. 9786341825Sdim if (isEmptyRecord(getContext(), Ty, true)) { 9787341825Sdim Address Addr(CGF.Builder.CreateLoad(VAListAddr), SlotSize); 9788341825Sdim Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty)); 9789341825Sdim return Addr; 9790341825Sdim } 9791341825Sdim 9792341825Sdim std::pair<CharUnits, CharUnits> SizeAndAlign = 9793341825Sdim getContext().getTypeInfoInChars(Ty); 9794341825Sdim 9795341825Sdim // Arguments bigger than 2*Xlen bytes are passed indirectly. 9796341825Sdim bool IsIndirect = SizeAndAlign.first > 2 * SlotSize; 9797341825Sdim 9798341825Sdim return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, SizeAndAlign, 9799341825Sdim SlotSize, /*AllowHigherAlign=*/true); 9800341825Sdim} 9801341825Sdim 9802341825SdimABIArgInfo RISCVABIInfo::extendType(QualType Ty) const { 9803341825Sdim int TySize = getContext().getTypeSize(Ty); 9804341825Sdim // RV64 ABI requires unsigned 32 bit integers to be sign extended. 9805341825Sdim if (XLen == 64 && Ty->isUnsignedIntegerOrEnumerationType() && TySize == 32) 9806341825Sdim return ABIArgInfo::getSignExtend(Ty); 9807341825Sdim return ABIArgInfo::getExtend(Ty); 9808341825Sdim} 9809341825Sdim 9810341825Sdimnamespace { 9811341825Sdimclass RISCVTargetCodeGenInfo : public TargetCodeGenInfo { 9812341825Sdimpublic: 9813353358Sdim RISCVTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen, 9814353358Sdim unsigned FLen) 9815353358Sdim : TargetCodeGenInfo(new RISCVABIInfo(CGT, XLen, FLen)) {} 9816341825Sdim 9817341825Sdim void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 9818341825Sdim CodeGen::CodeGenModule &CGM) const override { 9819341825Sdim const auto *FD = dyn_cast_or_null<FunctionDecl>(D); 9820341825Sdim if (!FD) return; 9821341825Sdim 9822341825Sdim const auto *Attr = FD->getAttr<RISCVInterruptAttr>(); 9823341825Sdim if (!Attr) 9824341825Sdim return; 9825341825Sdim 9826341825Sdim const char *Kind; 9827341825Sdim switch (Attr->getInterrupt()) { 9828341825Sdim case RISCVInterruptAttr::user: Kind = "user"; break; 9829341825Sdim case RISCVInterruptAttr::supervisor: Kind = "supervisor"; break; 9830341825Sdim case RISCVInterruptAttr::machine: Kind = "machine"; break; 9831341825Sdim } 9832341825Sdim 9833341825Sdim auto *Fn = cast<llvm::Function>(GV); 9834341825Sdim 9835341825Sdim Fn->addFnAttr("interrupt", Kind); 9836341825Sdim } 9837341825Sdim}; 9838341825Sdim} // namespace 9839341825Sdim 9840261991Sdim//===----------------------------------------------------------------------===// 9841261991Sdim// Driver code 9842261991Sdim//===----------------------------------------------------------------------===// 9843261991Sdim 9844280031Sdimbool CodeGenModule::supportsCOMDAT() const { 9845309124Sdim return getTriple().supportsCOMDAT(); 9846280031Sdim} 9847280031Sdim 9848212904Sdimconst TargetCodeGenInfo &CodeGenModule::getTargetCodeGenInfo() { 9849202379Srdivacky if (TheTargetCodeGenInfo) 9850202379Srdivacky return *TheTargetCodeGenInfo; 9851202379Srdivacky 9852309124Sdim // Helper to set the unique_ptr while still keeping the return value. 9853309124Sdim auto SetCGInfo = [&](TargetCodeGenInfo *P) -> const TargetCodeGenInfo & { 9854309124Sdim this->TheTargetCodeGenInfo.reset(P); 9855309124Sdim return *P; 9856309124Sdim }; 9857309124Sdim 9858251662Sdim const llvm::Triple &Triple = getTarget().getTriple(); 9859202379Srdivacky switch (Triple.getArch()) { 9860202379Srdivacky default: 9861309124Sdim return SetCGInfo(new DefaultTargetCodeGenInfo(Types)); 9862202379Srdivacky 9863243830Sdim case llvm::Triple::le32: 9864309124Sdim return SetCGInfo(new PNaClTargetCodeGenInfo(Types)); 9865208600Srdivacky case llvm::Triple::mips: 9866208600Srdivacky case llvm::Triple::mipsel: 9867288943Sdim if (Triple.getOS() == llvm::Triple::NaCl) 9868309124Sdim return SetCGInfo(new PNaClTargetCodeGenInfo(Types)); 9869309124Sdim return SetCGInfo(new MIPSTargetCodeGenInfo(Types, true)); 9870208600Srdivacky 9871226633Sdim case llvm::Triple::mips64: 9872226633Sdim case llvm::Triple::mips64el: 9873309124Sdim return SetCGInfo(new MIPSTargetCodeGenInfo(Types, false)); 9874226633Sdim 9875321369Sdim case llvm::Triple::avr: 9876321369Sdim return SetCGInfo(new AVRTargetCodeGenInfo(Types)); 9877321369Sdim 9878249423Sdim case llvm::Triple::aarch64: 9879360784Sdim case llvm::Triple::aarch64_32: 9880280031Sdim case llvm::Triple::aarch64_be: { 9881276479Sdim AArch64ABIInfo::ABIKind Kind = AArch64ABIInfo::AAPCS; 9882276479Sdim if (getTarget().getABI() == "darwinpcs") 9883276479Sdim Kind = AArch64ABIInfo::DarwinPCS; 9884321369Sdim else if (Triple.isOSWindows()) 9885327952Sdim return SetCGInfo( 9886327952Sdim new WindowsAArch64TargetCodeGenInfo(Types, AArch64ABIInfo::Win64)); 9887249423Sdim 9888309124Sdim return SetCGInfo(new AArch64TargetCodeGenInfo(Types, Kind)); 9889276479Sdim } 9890276479Sdim 9891296417Sdim case llvm::Triple::wasm32: 9892296417Sdim case llvm::Triple::wasm64: 9893309124Sdim return SetCGInfo(new WebAssemblyTargetCodeGenInfo(Types)); 9894296417Sdim 9895202379Srdivacky case llvm::Triple::arm: 9896276479Sdim case llvm::Triple::armeb: 9897202379Srdivacky case llvm::Triple::thumb: 9898309124Sdim case llvm::Triple::thumbeb: { 9899309124Sdim if (Triple.getOS() == llvm::Triple::Win32) { 9900309124Sdim return SetCGInfo( 9901309124Sdim new WindowsARMTargetCodeGenInfo(Types, ARMABIInfo::AAPCS_VFP)); 9902309124Sdim } 9903288943Sdim 9904309124Sdim ARMABIInfo::ABIKind Kind = ARMABIInfo::AAPCS; 9905309124Sdim StringRef ABIStr = getTarget().getABI(); 9906309124Sdim if (ABIStr == "apcs-gnu") 9907309124Sdim Kind = ARMABIInfo::APCS; 9908309124Sdim else if (ABIStr == "aapcs16") 9909309124Sdim Kind = ARMABIInfo::AAPCS16_VFP; 9910309124Sdim else if (CodeGenOpts.FloatABI == "hard" || 9911309124Sdim (CodeGenOpts.FloatABI != "soft" && 9912309124Sdim (Triple.getEnvironment() == llvm::Triple::GNUEABIHF || 9913309124Sdim Triple.getEnvironment() == llvm::Triple::MuslEABIHF || 9914309124Sdim Triple.getEnvironment() == llvm::Triple::EABIHF))) 9915309124Sdim Kind = ARMABIInfo::AAPCS_VFP; 9916202379Srdivacky 9917309124Sdim return SetCGInfo(new ARMTargetCodeGenInfo(Types, Kind)); 9918309124Sdim } 9919221345Sdim 9920363496Sdim case llvm::Triple::ppc: { 9921363496Sdim bool IsSoftFloat = 9922363496Sdim CodeGenOpts.FloatABI == "soft" || getTarget().hasFeature("spe"); 9923363496Sdim bool RetSmallStructInRegABI = 9924363496Sdim PPC32TargetCodeGenInfo::isStructReturnInRegABI(Triple, CodeGenOpts); 9925309124Sdim return SetCGInfo( 9926363496Sdim new PPC32TargetCodeGenInfo(Types, IsSoftFloat, RetSmallStructInRegABI)); 9927363496Sdim } 9928239462Sdim case llvm::Triple::ppc64: 9929276479Sdim if (Triple.isOSBinFormatELF()) { 9930276479Sdim PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv1; 9931280031Sdim if (getTarget().getABI() == "elfv2") 9932280031Sdim Kind = PPC64_SVR4_ABIInfo::ELFv2; 9933288943Sdim bool HasQPX = getTarget().getABI() == "elfv1-qpx"; 9934309149Sdim bool IsSoftFloat = CodeGenOpts.FloatABI == "soft"; 9935280031Sdim 9936309149Sdim return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX, 9937309149Sdim IsSoftFloat)); 9938276479Sdim } else 9939309124Sdim return SetCGInfo(new PPC64TargetCodeGenInfo(Types)); 9940276479Sdim case llvm::Triple::ppc64le: { 9941261991Sdim assert(Triple.isOSBinFormatELF() && "PPC64 LE non-ELF not supported!"); 9942276479Sdim PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv2; 9943288943Sdim if (getTarget().getABI() == "elfv1" || getTarget().getABI() == "elfv1-qpx") 9944280031Sdim Kind = PPC64_SVR4_ABIInfo::ELFv1; 9945288943Sdim bool HasQPX = getTarget().getABI() == "elfv1-qpx"; 9946309149Sdim bool IsSoftFloat = CodeGenOpts.FloatABI == "soft"; 9947280031Sdim 9948309149Sdim return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX, 9949309149Sdim IsSoftFloat)); 9950276479Sdim } 9951205219Srdivacky 9952239462Sdim case llvm::Triple::nvptx: 9953239462Sdim case llvm::Triple::nvptx64: 9954309124Sdim return SetCGInfo(new NVPTXTargetCodeGenInfo(Types)); 9955221345Sdim 9956202379Srdivacky case llvm::Triple::msp430: 9957309124Sdim return SetCGInfo(new MSP430TargetCodeGenInfo(Types)); 9958202379Srdivacky 9959341825Sdim case llvm::Triple::riscv32: 9960353358Sdim case llvm::Triple::riscv64: { 9961353358Sdim StringRef ABIStr = getTarget().getABI(); 9962353358Sdim unsigned XLen = getTarget().getPointerWidth(0); 9963353358Sdim unsigned ABIFLen = 0; 9964353358Sdim if (ABIStr.endswith("f")) 9965353358Sdim ABIFLen = 32; 9966353358Sdim else if (ABIStr.endswith("d")) 9967353358Sdim ABIFLen = 64; 9968353358Sdim return SetCGInfo(new RISCVTargetCodeGenInfo(Types, XLen, ABIFLen)); 9969353358Sdim } 9970341825Sdim 9971288943Sdim case llvm::Triple::systemz: { 9972288943Sdim bool HasVector = getTarget().getABI() == "vector"; 9973309124Sdim return SetCGInfo(new SystemZTargetCodeGenInfo(Types, HasVector)); 9974288943Sdim } 9975251662Sdim 9976226633Sdim case llvm::Triple::tce: 9977314564Sdim case llvm::Triple::tcele: 9978309124Sdim return SetCGInfo(new TCETargetCodeGenInfo(Types)); 9979226633Sdim 9980224145Sdim case llvm::Triple::x86: { 9981261991Sdim bool IsDarwinVectorABI = Triple.isOSDarwin(); 9982296417Sdim bool RetSmallStructInRegABI = 9983261991Sdim X86_32TargetCodeGenInfo::isStructReturnInRegABI(Triple, CodeGenOpts); 9984280031Sdim bool IsWin32FloatStructABI = Triple.isOSWindows() && !Triple.isOSCygMing(); 9985221345Sdim 9986261991Sdim if (Triple.getOS() == llvm::Triple::Win32) { 9987309124Sdim return SetCGInfo(new WinX86_32TargetCodeGenInfo( 9988309124Sdim Types, IsDarwinVectorABI, RetSmallStructInRegABI, 9989309124Sdim IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters)); 9990261991Sdim } else { 9991309124Sdim return SetCGInfo(new X86_32TargetCodeGenInfo( 9992309124Sdim Types, IsDarwinVectorABI, RetSmallStructInRegABI, 9993309124Sdim IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters, 9994309124Sdim CodeGenOpts.FloatABI == "soft")); 9995202379Srdivacky } 9996224145Sdim } 9997202379Srdivacky 9998234353Sdim case llvm::Triple::x86_64: { 9999288943Sdim StringRef ABI = getTarget().getABI(); 10000309124Sdim X86AVXABILevel AVXLevel = 10001309124Sdim (ABI == "avx512" 10002309124Sdim ? X86AVXABILevel::AVX512 10003309124Sdim : ABI == "avx" ? X86AVXABILevel::AVX : X86AVXABILevel::None); 10004234353Sdim 10005212904Sdim switch (Triple.getOS()) { 10006212904Sdim case llvm::Triple::Win32: 10007309124Sdim return SetCGInfo(new WinX86_64TargetCodeGenInfo(Types, AVXLevel)); 10008212904Sdim default: 10009309124Sdim return SetCGInfo(new X86_64TargetCodeGenInfo(Types, AVXLevel)); 10010212904Sdim } 10011202379Srdivacky } 10012234353Sdim case llvm::Triple::hexagon: 10013309124Sdim return SetCGInfo(new HexagonTargetCodeGenInfo(Types)); 10014309124Sdim case llvm::Triple::lanai: 10015309124Sdim return SetCGInfo(new LanaiTargetCodeGenInfo(Types)); 10016280031Sdim case llvm::Triple::r600: 10017309124Sdim return SetCGInfo(new AMDGPUTargetCodeGenInfo(Types)); 10018280031Sdim case llvm::Triple::amdgcn: 10019309124Sdim return SetCGInfo(new AMDGPUTargetCodeGenInfo(Types)); 10020309124Sdim case llvm::Triple::sparc: 10021309124Sdim return SetCGInfo(new SparcV8TargetCodeGenInfo(Types)); 10022261991Sdim case llvm::Triple::sparcv9: 10023309124Sdim return SetCGInfo(new SparcV9TargetCodeGenInfo(Types)); 10024261991Sdim case llvm::Triple::xcore: 10025309124Sdim return SetCGInfo(new XCoreTargetCodeGenInfo(Types)); 10026344779Sdim case llvm::Triple::arc: 10027344779Sdim return SetCGInfo(new ARCTargetCodeGenInfo(Types)); 10028309124Sdim case llvm::Triple::spir: 10029309124Sdim case llvm::Triple::spir64: 10030309124Sdim return SetCGInfo(new SPIRTargetCodeGenInfo(Types)); 10031234353Sdim } 10032202379Srdivacky} 10033327952Sdim 10034327952Sdim/// Create an OpenCL kernel for an enqueued block. 10035327952Sdim/// 10036327952Sdim/// The kernel has the same function type as the block invoke function. Its 10037327952Sdim/// name is the name of the block invoke function postfixed with "_kernel". 10038327952Sdim/// It simply calls the block invoke function then returns. 10039327952Sdimllvm::Function * 10040327952SdimTargetCodeGenInfo::createEnqueuedBlockKernel(CodeGenFunction &CGF, 10041327952Sdim llvm::Function *Invoke, 10042327952Sdim llvm::Value *BlockLiteral) const { 10043327952Sdim auto *InvokeFT = Invoke->getFunctionType(); 10044327952Sdim llvm::SmallVector<llvm::Type *, 2> ArgTys; 10045327952Sdim for (auto &P : InvokeFT->params()) 10046327952Sdim ArgTys.push_back(P); 10047327952Sdim auto &C = CGF.getLLVMContext(); 10048327952Sdim std::string Name = Invoke->getName().str() + "_kernel"; 10049327952Sdim auto *FT = llvm::FunctionType::get(llvm::Type::getVoidTy(C), ArgTys, false); 10050327952Sdim auto *F = llvm::Function::Create(FT, llvm::GlobalValue::InternalLinkage, Name, 10051327952Sdim &CGF.CGM.getModule()); 10052327952Sdim auto IP = CGF.Builder.saveIP(); 10053327952Sdim auto *BB = llvm::BasicBlock::Create(C, "entry", F); 10054327952Sdim auto &Builder = CGF.Builder; 10055327952Sdim Builder.SetInsertPoint(BB); 10056327952Sdim llvm::SmallVector<llvm::Value *, 2> Args; 10057327952Sdim for (auto &A : F->args()) 10058327952Sdim Args.push_back(&A); 10059327952Sdim Builder.CreateCall(Invoke, Args); 10060327952Sdim Builder.CreateRetVoid(); 10061327952Sdim Builder.restoreIP(IP); 10062327952Sdim return F; 10063327952Sdim} 10064327952Sdim 10065327952Sdim/// Create an OpenCL kernel for an enqueued block. 10066327952Sdim/// 10067327952Sdim/// The type of the first argument (the block literal) is the struct type 10068327952Sdim/// of the block literal instead of a pointer type. The first argument 10069327952Sdim/// (block literal) is passed directly by value to the kernel. The kernel 10070327952Sdim/// allocates the same type of struct on stack and stores the block literal 10071327952Sdim/// to it and passes its pointer to the block invoke function. The kernel 10072327952Sdim/// has "enqueued-block" function attribute and kernel argument metadata. 10073327952Sdimllvm::Function *AMDGPUTargetCodeGenInfo::createEnqueuedBlockKernel( 10074327952Sdim CodeGenFunction &CGF, llvm::Function *Invoke, 10075327952Sdim llvm::Value *BlockLiteral) const { 10076327952Sdim auto &Builder = CGF.Builder; 10077327952Sdim auto &C = CGF.getLLVMContext(); 10078327952Sdim 10079327952Sdim auto *BlockTy = BlockLiteral->getType()->getPointerElementType(); 10080327952Sdim auto *InvokeFT = Invoke->getFunctionType(); 10081327952Sdim llvm::SmallVector<llvm::Type *, 2> ArgTys; 10082327952Sdim llvm::SmallVector<llvm::Metadata *, 8> AddressQuals; 10083327952Sdim llvm::SmallVector<llvm::Metadata *, 8> AccessQuals; 10084327952Sdim llvm::SmallVector<llvm::Metadata *, 8> ArgTypeNames; 10085327952Sdim llvm::SmallVector<llvm::Metadata *, 8> ArgBaseTypeNames; 10086327952Sdim llvm::SmallVector<llvm::Metadata *, 8> ArgTypeQuals; 10087327952Sdim llvm::SmallVector<llvm::Metadata *, 8> ArgNames; 10088327952Sdim 10089327952Sdim ArgTys.push_back(BlockTy); 10090327952Sdim ArgTypeNames.push_back(llvm::MDString::get(C, "__block_literal")); 10091327952Sdim AddressQuals.push_back(llvm::ConstantAsMetadata::get(Builder.getInt32(0))); 10092327952Sdim ArgBaseTypeNames.push_back(llvm::MDString::get(C, "__block_literal")); 10093327952Sdim ArgTypeQuals.push_back(llvm::MDString::get(C, "")); 10094327952Sdim AccessQuals.push_back(llvm::MDString::get(C, "none")); 10095327952Sdim ArgNames.push_back(llvm::MDString::get(C, "block_literal")); 10096327952Sdim for (unsigned I = 1, E = InvokeFT->getNumParams(); I < E; ++I) { 10097327952Sdim ArgTys.push_back(InvokeFT->getParamType(I)); 10098327952Sdim ArgTypeNames.push_back(llvm::MDString::get(C, "void*")); 10099327952Sdim AddressQuals.push_back(llvm::ConstantAsMetadata::get(Builder.getInt32(3))); 10100327952Sdim AccessQuals.push_back(llvm::MDString::get(C, "none")); 10101327952Sdim ArgBaseTypeNames.push_back(llvm::MDString::get(C, "void*")); 10102327952Sdim ArgTypeQuals.push_back(llvm::MDString::get(C, "")); 10103327952Sdim ArgNames.push_back( 10104327952Sdim llvm::MDString::get(C, (Twine("local_arg") + Twine(I)).str())); 10105327952Sdim } 10106327952Sdim std::string Name = Invoke->getName().str() + "_kernel"; 10107327952Sdim auto *FT = llvm::FunctionType::get(llvm::Type::getVoidTy(C), ArgTys, false); 10108327952Sdim auto *F = llvm::Function::Create(FT, llvm::GlobalValue::InternalLinkage, Name, 10109327952Sdim &CGF.CGM.getModule()); 10110327952Sdim F->addFnAttr("enqueued-block"); 10111327952Sdim auto IP = CGF.Builder.saveIP(); 10112327952Sdim auto *BB = llvm::BasicBlock::Create(C, "entry", F); 10113327952Sdim Builder.SetInsertPoint(BB); 10114327952Sdim unsigned BlockAlign = CGF.CGM.getDataLayout().getPrefTypeAlignment(BlockTy); 10115327952Sdim auto *BlockPtr = Builder.CreateAlloca(BlockTy, nullptr); 10116360784Sdim BlockPtr->setAlignment(llvm::MaybeAlign(BlockAlign)); 10117327952Sdim Builder.CreateAlignedStore(F->arg_begin(), BlockPtr, BlockAlign); 10118327952Sdim auto *Cast = Builder.CreatePointerCast(BlockPtr, InvokeFT->getParamType(0)); 10119327952Sdim llvm::SmallVector<llvm::Value *, 2> Args; 10120327952Sdim Args.push_back(Cast); 10121327952Sdim for (auto I = F->arg_begin() + 1, E = F->arg_end(); I != E; ++I) 10122327952Sdim Args.push_back(I); 10123327952Sdim Builder.CreateCall(Invoke, Args); 10124327952Sdim Builder.CreateRetVoid(); 10125327952Sdim Builder.restoreIP(IP); 10126327952Sdim 10127327952Sdim F->setMetadata("kernel_arg_addr_space", llvm::MDNode::get(C, AddressQuals)); 10128327952Sdim F->setMetadata("kernel_arg_access_qual", llvm::MDNode::get(C, AccessQuals)); 10129327952Sdim F->setMetadata("kernel_arg_type", llvm::MDNode::get(C, ArgTypeNames)); 10130327952Sdim F->setMetadata("kernel_arg_base_type", 10131327952Sdim llvm::MDNode::get(C, ArgBaseTypeNames)); 10132327952Sdim F->setMetadata("kernel_arg_type_qual", llvm::MDNode::get(C, ArgTypeQuals)); 10133327952Sdim if (CGF.CGM.getCodeGenOpts().EmitOpenCLArgMetadata) 10134327952Sdim F->setMetadata("kernel_arg_name", llvm::MDNode::get(C, ArgNames)); 10135327952Sdim 10136327952Sdim return F; 10137327952Sdim} 10138