/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 409 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an 412 EXTRACT_SUBVECTOR, enumerator in enum:llvm::ISD::NodeType
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorTypes.cpp | 53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; 833 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; 1117 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); 1119 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, 1927 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; 2160 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); 2162 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, 2691 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break; 3012 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, 3015 ISD::EXTRACT_SUBVECTOR, d [all...] |
H A D | DAGCombiner.cpp | 1609 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); 11002 if (!LegalTypes && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) { 11009 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N0->getOperand(0)), VT, 15427 // EXTRACT_SUBVECTOR. 15430 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) { 15436 unsigned OpC = MemVT.isVector() ? ISD::EXTRACT_SUBVECTOR 15540 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR); 15610 OtherBC.getOpcode() != ISD::EXTRACT_SUBVECTOR) 15772 StoredVal.getOpcode() == ISD::EXTRACT_SUBVECTOR); 17472 VecIn2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, D [all...] |
H A D | SelectionDAGDumper.cpp | 284 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector";
|
H A D | LegalizeIntegerTypes.cpp | 95 case ISD::EXTRACT_SUBVECTOR: 386 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, InOp, 1065 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, WideExt, ZeroIdx); 1300 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break; 4429 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1));
|
H A D | SelectionDAG.cpp | 2328 case ISD::EXTRACT_SUBVECTOR: { 2658 case ISD::EXTRACT_SUBVECTOR: { 3916 case ISD::EXTRACT_SUBVECTOR: { 4309 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR || 5378 // EXTRACT_VECTOR_ELT of v1iX EXTRACT_SUBVECTOR could be formed 5381 if (N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && 5408 case ISD::EXTRACT_SUBVECTOR: 5428 // EXTRACT_SUBVECTOR of an UNDEF is an UNDEF. 5432 // EXTRACT_SUBVECTOR of CONCAT_VECTOR can be simplified if the pieces of 5441 // EXTRACT_SUBVECTOR o [all...] |
H A D | SelectionDAGBuilder.cpp | 442 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 476 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 746 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val, 3687 ISD::EXTRACT_SUBVECTOR, DL, VT, Result, 3733 ISD::EXTRACT_SUBVECTOR, DL, VT, Src,
|
H A D | TargetLowering.cpp | 960 case ISD::EXTRACT_SUBVECTOR: { 2359 case ISD::EXTRACT_SUBVECTOR: {
|
H A D | LegalizeDAG.cpp | 3016 case ISD::EXTRACT_SUBVECTOR:
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 286 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom); 287 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom); 288 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3f32, Custom); 289 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3i32, Custom); 290 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom); 291 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom); 292 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5f32, Custom); 293 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5i32, Custom); 294 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom); 295 setOperationAction(ISD::EXTRACT_SUBVECTOR, MV [all...] |
H A D | SIISelLowering.cpp | 273 case ISD::EXTRACT_SUBVECTOR: 535 case ISD::EXTRACT_SUBVECTOR: 1448 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, NarrowedVT, Val, 4952 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, 5688 ISD::EXTRACT_SUBVECTOR, DL, VT, WidenedOp, 6754 ISD::EXTRACT_SUBVECTOR, DL, VT, NewOp, 8849 case ISD::EXTRACT_SUBVECTOR: {
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 780 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand); 1338 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); 1439 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); 1611 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); 1756 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); 1989 setTargetDAGCombine(ISD::EXTRACT_SUBVECTOR); 5046 if (UI->getOpcode() != ISD::EXTRACT_SUBVECTOR || !UI->hasOneUse() || 5118 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) 5627 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR 5641 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, d [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 896 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); 3227 case ISD::EXTRACT_SUBVECTOR: 6654 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, 6660 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, 6665 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, 6668 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, 7020 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0, 7024 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1, 7247 BitCast.getOperand(0).getOpcode() != ISD::EXTRACT_SUBVECTOR) 7277 } else if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) { [all...] |
H A D | AArch64ISelDAGToDAG.cpp | 549 if (EV.getOpcode() != ISD::EXTRACT_SUBVECTOR) 1847 if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR)
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 99 setOperationAction(ISD::EXTRACT_SUBVECTOR, T, Custom); 190 setOperationAction(ISD::EXTRACT_SUBVECTOR, BoolV, Custom); 1567 case ISD::EXTRACT_SUBVECTOR: return LowerHvxExtractSubvector(Op, DAG);
|
H A D | HexagonISelLowering.cpp | 1492 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, 1540 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom); 2906 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 185 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); 411 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); 5704 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast, 7499 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, 7505 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, 7510 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, 7513 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, 8332 "Unexpected custom EXTRACT_SUBVECTOR lowering"); 8334 "EXTRACT_SUBVECTOR lowering only supported for MVE"); 8730 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, d [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 2185 case ISD::EXTRACT_SUBVECTOR:
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 1009 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand); 1057 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand); 1098 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand); 10394 case ISD::EXTRACT_SUBVECTOR: {
|