Searched refs:Disp (Results 1 - 25 of 43) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCCodeEmitter.cpp187 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); local
188 assert(isUInt<4>(Base) && isUInt<12>(Disp));
189 return (Base << 12) | Disp;
197 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); local
198 assert(isUInt<4>(Base) && isInt<20>(Disp));
199 return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12);
207 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); local
209 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index));
210 return (Index << 16) | (Base << 12) | Disp;
218 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); local
230 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); local
241 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); local
252 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); local
263 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); local
[all...]
H A DSystemZInstPrinter.cpp26 void SystemZInstPrinter::printAddress(unsigned Base, int64_t Disp, argument
28 O << Disp; local
202 uint64_t Disp = MI->getOperand(OpNum + 1).getImm(); local
204 O << Disp << '(' << Length;
213 uint64_t Disp = MI->getOperand(OpNum + 1).getImm(); local
215 O << Disp << "(%" << getRegisterName(Length);
H A DSystemZInstPrinter.h34 static void printAddress(unsigned Base, int64_t Disp, unsigned Index,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430InstPrinter.cpp71 const MCOperand &Disp = MI->getOperand(OpNo+1); local
84 if (Disp.isExpr())
85 Disp.getExpr()->print(O, &MAI);
87 assert(Disp.isImm() && "Expected immediate in displacement field");
88 O << Disp.getImm();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp47 int16_t Disp = 0; member in struct:__anon2295::MSP430ISelAddressMode
70 errs() << " Disp " << Disp << '\n';
119 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
145 AM.Disp += G->getOffset();
150 AM.Disp += CP->getOffset();
187 AM.Disp += Val;
230 AM.Disp += Offset;
245 SDValue &Base, SDValue &Disp) {
262 Disp
244 SelectAddr(SDValue N, SDValue &Base, SDValue &Disp) argument
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H A DMSP430AsmPrinter.cpp110 const MachineOperand &Disp = MI->getOperand(OpNum+1); local
115 if (Disp.isImm() && Base.getReg() == MSP430::SR)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp85 const MachineOperand *Disp)
86 : Disp(Disp) {
103 return isSimilarDispOp(*Disp, *Other.Disp);
110 const MachineOperand *Disp; member in class:__anon2514::MemOpKey
136 assert(Val.Disp != PtrInfo::getEmptyKey() && "Cannot hash the empty key");
137 assert(Val.Disp != PtrInfo::getTombstoneKey() &&
147 switch (Val.Disp->getType()) {
152 Hash = hash_combine(Hash, Val.Disp
83 MemOpKey(const MachineOperand *Base, const MachineOperand *Scale, const MachineOperand *Index, const MachineOperand *Segment, const MachineOperand *Disp) argument
[all...]
H A DX86InstrBuilder.h40 /// with BP or SP and Disp being offsetted accordingly. The displacement may
55 int Disp; member in struct:llvm::X86AddressMode
60 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr),
81 MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags));
83 MO.push_back(MachineOperand::CreateImm(Disp));
114 AM.Disp = Op3.getImm();
185 MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
187 MIB.addImm(AM.Disp);
H A DX86FixupLEAs.cpp360 const MachineOperand &Disp = MI.getOperand(1 + X86::AddrDisp); local
363 if (Segment.getReg() != 0 || !Disp.isImm() || Scale.getImm() > 1 ||
387 if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 &&
410 if (OptIncDec && (Disp.getImm() == 1 || Disp.getImm() == -1)) {
411 bool IsINC = Disp.getImm() == 1;
423 unsigned NewOpcode = getADDriFromLEA(MI.getOpcode(), Disp);
427 .addReg(BaseReg).addImm(Disp.getImm())
431 .addReg(BaseReg).addImm(Disp.getImm());
H A DX86ISelDAGToDAG.cpp67 int32_t Disp; member in struct:__anon104::X86ISelAddressMode
80 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
126 dbgs() << " Disp " << Disp << '\n'
222 SDValue &Scale, SDValue &Index, SDValue &Disp,
225 SDValue &Scale, SDValue &Index, SDValue &Disp,
229 SDValue &Scale, SDValue &Index, SDValue &Disp,
232 SDValue &Scale, SDValue &Index, SDValue &Disp,
235 SDValue &Scale, SDValue &Index, SDValue &Disp,
239 SDValue &Index, SDValue &Disp,
250 tryFoldLoad(SDNode *P, SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment) argument
269 getAddressOperands(X86ISelAddressMode &AM, const SDLoc &DL, MVT VT, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment) argument
1996 uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val; local
2062 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue(); local
2283 selectVectorAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment) argument
2317 selectAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment) argument
2374 selectScalarSSELoad(SDNode *Root, SDNode *Parent, SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment, SDValue &PatternNodeWithChain) argument
2458 selectLEA64_32Addr(SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment) argument
2495 selectLEAAddr(SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment) argument
2585 selectTLSADDRAddr(SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment) argument
2649 tryFoldLoad(SDNode *Root, SDNode *P, SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment) argument
2663 tryFoldBroadcast(SDNode *Root, SDNode *P, SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment) argument
3050 SDValue Base, Scale, Index, Disp, Segment; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp58 // Base + Disp + Index + (IncludesDynAlloc ? ADJDYNALLOC : 0)
60 int64_t Disp; member in struct:__anon2408::SystemZAddressingMode
65 : Form(form), DR(dr), Base(), Disp(0), Index(),
91 errs() << " Disp " << Disp;
159 SDValue &Base, SDValue &Disp) const;
161 SDValue &Base, SDValue &Disp, SDValue &Index) const;
165 // Base and Disp respectively.
167 SDValue &Base, SDValue &Disp) const;
171 // base and displacement in Base and Disp respectivel
214 selectBDXAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument
220 selectBDXAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument
226 selectDynAlloc12Only(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument
232 selectBDXAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument
238 selectBDXAddr20Only128(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument
244 selectBDXAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument
250 selectLAAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument
256 selectLAAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument
517 shouldUseLA(SDNode *Base, int64_t Disp, SDNode *Index) argument
651 getAddressOperands(const SystemZAddressingMode &AM, EVT VT, SDValue &Base, SDValue &Disp, SDValue &Index) const argument
685 selectBDXAddr(SystemZAddressingMode::AddrForm Form, SystemZAddressingMode::DispRange DR, SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) const argument
697 selectBDVAddr12Only(SDValue Addr, SDValue Elem, SDValue &Base, SDValue &Disp, SDValue &Index) const argument
1388 SDValue Base, Disp; local
1635 SDValue Base, Disp, Index; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp200 uint64_t Disp = Imm & 0xFFFF;
224 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp)));
235 uint64_t Disp = Imm & 0x3FFF;
245 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2)));
256 uint64_t Disp = Imm & 0xFFF;
260 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4)));
271 uint64_t Disp = Imm & 0x1F;
275 Inst.addOperand(MCOperand::createImm(Disp << 3));
286 uint64_t Disp = Imm & 0x1F;
290 Inst.addOperand(MCOperand::createImm(Disp <<
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp294 uint64_t Disp = Field & 0xfff;
297 Inst.addOperand(MCOperand::createImm(Disp));
304 uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff);
307 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
315 uint64_t Disp = Field & 0xfff;
318 Inst.addOperand(MCOperand::createImm(Disp));
327 uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12);
330 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
339 uint64_t Disp = Field & 0xfff;
342 Inst.addOperand(MCOperand::createImm(Disp));
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp38 bool SelectAddr(SDNode *Op, SDValue N, SDValue &Base, SDValue &Disp);
65 SDValue &Disp) {
73 Disp = CurDAG->getTargetConstant(0, dl, MVT::i8);
100 Disp = CurDAG->getTargetConstant(RHSC, dl, MVT::i16);
112 Disp = CurDAG->getTargetConstant(RHSC, dl, MVT::i8);
225 SDValue Base, Disp; local
227 if (SelectAddr(Op.getNode(), Op, Base, Disp)) {
229 OutOps.push_back(Disp);
263 SDValue Base, Disp;
282 Disp
64 SelectAddr(SDNode *Op, SDValue N, SDValue &Base, SDValue &Disp) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp89 void emitImmediate(const MCOperand &Disp, SMLoc Loc, unsigned ImmSize,
188 const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp);
190 if (STI.hasFeature(X86::Mode16Bit) && BaseReg.getReg() == 0 && Disp.isImm() &&
191 Disp.getImm() < 0x10000)
374 const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp); local
424 int ImmSize = !Disp.isImm() && X86II::hasImm(TSFlags)
428 emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), CurByte, OS,
472 if (Disp.isImm() && isDisp8(Disp.getImm())) {
473 if (Disp
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h275 const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off, argument
282 TargetFlags = Disp.getTargetFlags();
284 switch (Disp.getType()) {
288 return addImm(Disp.getImm() + off);
290 return addConstantPoolIndex(Disp.getIndex(), Disp.getOffset() + off,
293 return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off,
296 return addBlockAddress(Disp.getBlockAddress(), Disp
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86Operand.h61 const MCExpr *Disp; member in struct:llvm::final::MemOp
142 if (Mem.Disp)
143 PrintImmValue(Mem.Disp, ",Disp=");
177 return Mem.Disp;
629 CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc, argument
634 Res->Mem.Disp = Disp;
649 CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp, argument
662 Res->Mem.Disp
[all...]
H A DX86AsmParser.cpp891 const MCExpr *&Disp,
899 CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
1265 const MCExpr *Disp = MCConstantExpr::create(0, getContext()); local
1266 return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
1274 const MCExpr *Disp = MCConstantExpr::create(0, getContext()); local
1275 return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
1409 unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,
1423 return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size,
1441 return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End);
1447 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseRe
1408 CreateMemForInlineAsm( unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier, const InlineAsmIdentifierInfo &Info) argument
1946 const MCExpr *Disp = SM.getSym(); local
2209 ParseMemOperand(unsigned SegReg, const MCExpr *&Disp, const SMLoc &StartLoc, SMLoc &EndLoc) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp110 // Base + Disp + Index, where Base and Index are LLVM registers or 0.
119 const MCExpr *Disp; member in struct:__anon2401::SystemZOperand::MemOp
185 const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
192 Op->Mem.Disp = Disp;
267 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
270 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
307 addExpr(Inst, Mem.Disp);
313 addExpr(Inst, Mem.Disp);
320 addExpr(Inst, Mem.Disp);
184 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base, const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm, unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) argument
835 parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2, Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length) argument
902 const MCExpr *Disp; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Support/
H A DFileSystem.h944 /// @param Disp Value specifying the existing-file behavior.
952 CreationDisposition Disp, FileAccess Access,
962 /// @param Disp Value specifying the existing-file behavior.
969 Expected<file_t> openNativeFile(const Twine &Name, CreationDisposition Disp,
1033 CreationDisposition Disp = CD_CreateAlways,
1035 return openFile(Name, ResultFD, Disp, FA_Write, Flags, Mode);
1052 CreationDisposition Disp,
1055 return openNativeFile(Name, Disp, FA_Write, Flags, Mode);
1074 CreationDisposition Disp,
1077 return openFile(Name, ResultFD, Disp, FA_Writ
1051 openNativeFileForWrite(const Twine &Name, CreationDisposition Disp, OpenFlags Flags, unsigned Mode = 0666) argument
1073 openFileForReadWrite(const Twine &Name, int &ResultFD, CreationDisposition Disp, OpenFlags Flags, unsigned Mode = 0666) argument
1093 openNativeFileForReadWrite(const Twine &Name, CreationDisposition Disp, OpenFlags Flags, unsigned Mode = 0666) argument
[all...]
/freebsd-11-stable/usr.sbin/ppp/
H A Dccp.h128 const char *(*Disp)(struct fsm_opt *); /* Use result immediately ! */ member in struct:ccp_algorithm
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Support/
H A Draw_ostream.cpp520 sys::fs::CreationDisposition Disp, sys::fs::FileAccess Access,
538 EC = sys::fs::openFileForReadWrite(Filename, FD, Disp, Flags);
540 EC = sys::fs::openFileForWrite(Filename, FD, Disp, Flags);
552 sys::fs::CreationDisposition Disp)
553 : raw_fd_ostream(Filename, EC, Disp, sys::fs::FA_Write, sys::fs::OF_None) {}
566 sys::fs::CreationDisposition Disp,
569 : raw_fd_ostream(getFD(Filename, EC, Disp, Access, Flags), true) {}
519 getFD(StringRef Filename, std::error_code &EC, sys::fs::CreationDisposition Disp, sys::fs::FileAccess Access, sys::fs::OpenFlags Flags) argument
551 raw_fd_ostream(StringRef Filename, std::error_code &EC, sys::fs::CreationDisposition Disp) argument
565 raw_fd_ostream(StringRef Filename, std::error_code &EC, sys::fs::CreationDisposition Disp, sys::fs::FileAccess Access, sys::fs::OpenFlags Flags) argument
/freebsd-11-stable/contrib/binutils/opcodes/
H A Di386-opc.h199 #define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */ macro
/freebsd-11-stable/contrib/llvm-project/llvm/tools/llvm-objdump/
H A DCOFFDump.cpp221 uint64_t Offset, uint32_t Disp) {
225 if (Disp > 0)
226 Out << format(" + 0x%04x", Disp);
228 Out << format("0x%04x", Disp);
219 printCOFFSymbolAddress(raw_ostream &Out, const std::vector<RelocationRef> &Rels, uint64_t Offset, uint32_t Disp) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp168 // which can be adjusted by \p Disp
171 int64_t Disp) {
178 int64_t Offset = MO.getImm() + Disp;
169 isLoadStoreThatCanHandleDisplacement(const TargetInstrInfo *TII, const MachineInstr &MI, int64_t Disp) argument

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