1234353Sdim//===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===// 2226584Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6226584Sdim// 7226584Sdim//===----------------------------------------------------------------------===// 8226584Sdim// 9226584Sdim// This file implements the X86MCCodeEmitter class. 10226584Sdim// 11226584Sdim//===----------------------------------------------------------------------===// 12226584Sdim 13226584Sdim#include "MCTargetDesc/X86BaseInfo.h" 14226584Sdim#include "MCTargetDesc/X86FixupKinds.h" 15321369Sdim#include "MCTargetDesc/X86MCTargetDesc.h" 16321369Sdim#include "llvm/ADT/SmallVector.h" 17226584Sdim#include "llvm/MC/MCCodeEmitter.h" 18243830Sdim#include "llvm/MC/MCContext.h" 19226584Sdim#include "llvm/MC/MCExpr.h" 20321369Sdim#include "llvm/MC/MCFixup.h" 21226584Sdim#include "llvm/MC/MCInst.h" 22321369Sdim#include "llvm/MC/MCInstrDesc.h" 23226584Sdim#include "llvm/MC/MCInstrInfo.h" 24226584Sdim#include "llvm/MC/MCRegisterInfo.h" 25226584Sdim#include "llvm/MC/MCSubtargetInfo.h" 26226584Sdim#include "llvm/MC/MCSymbol.h" 27321369Sdim#include "llvm/Support/ErrorHandling.h" 28226584Sdim#include "llvm/Support/raw_ostream.h" 29321369Sdim#include <cassert> 30321369Sdim#include <cstdint> 31321369Sdim#include <cstdlib> 32226584Sdim 33226584Sdimusing namespace llvm; 34226584Sdim 35276479Sdim#define DEBUG_TYPE "mccodeemitter" 36276479Sdim 37226584Sdimnamespace { 38321369Sdim 39226584Sdimclass X86MCCodeEmitter : public MCCodeEmitter { 40226584Sdim const MCInstrInfo &MCII; 41226584Sdim MCContext &Ctx; 42321369Sdim 43226584Sdimpublic: 44276479Sdim X86MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) 45360784Sdim : MCII(mcii), Ctx(ctx) {} 46321369Sdim X86MCCodeEmitter(const X86MCCodeEmitter &) = delete; 47321369Sdim X86MCCodeEmitter &operator=(const X86MCCodeEmitter &) = delete; 48321369Sdim ~X86MCCodeEmitter() override = default; 49226584Sdim 50360784Sdim void emitPrefix(const MCInst &MI, raw_ostream &OS, 51360784Sdim const MCSubtargetInfo &STI) const override; 52226584Sdim 53360784Sdim void encodeInstruction(const MCInst &MI, raw_ostream &OS, 54360784Sdim SmallVectorImpl<MCFixup> &Fixups, 55360784Sdim const MCSubtargetInfo &STI) const override; 56234353Sdim 57360784Sdimprivate: 58360784Sdim unsigned getX86RegNum(const MCOperand &MO) const { 59261991Sdim return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7; 60226584Sdim } 61226584Sdim 62309124Sdim unsigned getX86RegEncoding(const MCInst &MI, unsigned OpNum) const { 63309124Sdim return Ctx.getRegisterInfo()->getEncodingValue( 64360784Sdim MI.getOperand(OpNum).getReg()); 65226584Sdim } 66226584Sdim 67360784Sdim /// \param MI a single low-level machine instruction. 68360784Sdim /// \param OpNum the operand #. 69360784Sdim /// \returns true if the OpNumth operand of MI require a bit to be set in 70360784Sdim /// REX prefix. 71314564Sdim bool isREXExtendedReg(const MCInst &MI, unsigned OpNum) const { 72309124Sdim return (getX86RegEncoding(MI, OpNum) >> 3) & 1; 73261991Sdim } 74261991Sdim 75360784Sdim void emitByte(uint8_t C, unsigned &CurByte, raw_ostream &OS) const { 76226584Sdim OS << (char)C; 77226584Sdim ++CurByte; 78226584Sdim } 79226584Sdim 80360784Sdim void emitConstant(uint64_t Val, unsigned Size, unsigned &CurByte, 81226584Sdim raw_ostream &OS) const { 82226584Sdim // Output the constant in little endian byte order. 83226584Sdim for (unsigned i = 0; i != Size; ++i) { 84360784Sdim emitByte(Val & 255, CurByte, OS); 85226584Sdim Val >>= 8; 86226584Sdim } 87226584Sdim } 88226584Sdim 89360784Sdim void emitImmediate(const MCOperand &Disp, SMLoc Loc, unsigned ImmSize, 90360784Sdim MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS, 91360784Sdim SmallVectorImpl<MCFixup> &Fixups, int ImmOffset = 0) const; 92226584Sdim 93360784Sdim static uint8_t modRMByte(unsigned Mod, unsigned RegOpcode, unsigned RM) { 94226584Sdim assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!"); 95226584Sdim return RM | (RegOpcode << 3) | (Mod << 6); 96226584Sdim } 97226584Sdim 98360784Sdim void emitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld, 99226584Sdim unsigned &CurByte, raw_ostream &OS) const { 100360784Sdim emitByte(modRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)), CurByte, OS); 101226584Sdim } 102226584Sdim 103360784Sdim void emitSIBByte(unsigned SS, unsigned Index, unsigned Base, 104226584Sdim unsigned &CurByte, raw_ostream &OS) const { 105360784Sdim // SIB byte is in the same format as the modRMByte. 106360784Sdim emitByte(modRMByte(SS, Index, Base), CurByte, OS); 107226584Sdim } 108226584Sdim 109309124Sdim void emitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField, 110309124Sdim uint64_t TSFlags, bool Rex, unsigned &CurByte, 111309124Sdim raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, 112276479Sdim const MCSubtargetInfo &STI) const; 113226584Sdim 114360784Sdim void emitPrefixImpl(uint64_t TSFlags, unsigned &CurOp, unsigned &CurByte, 115360784Sdim bool &Rex, const MCInst &MI, const MCInstrDesc &Desc, 116360784Sdim const MCSubtargetInfo &STI, raw_ostream &OS) const; 117226584Sdim 118360784Sdim void emitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 119226584Sdim const MCInst &MI, const MCInstrDesc &Desc, 120226584Sdim raw_ostream &OS) const; 121226584Sdim 122360784Sdim void emitSegmentOverridePrefix(unsigned &CurByte, unsigned SegOperand, 123276479Sdim const MCInst &MI, raw_ostream &OS) const; 124226584Sdim 125309124Sdim bool emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 126226584Sdim const MCInst &MI, const MCInstrDesc &Desc, 127309124Sdim const MCSubtargetInfo &STI, raw_ostream &OS) const; 128309124Sdim 129360784Sdim uint8_t determineREXPrefix(const MCInst &MI, uint64_t TSFlags, int MemOperand, 130360784Sdim const MCInstrDesc &Desc) const; 131226584Sdim}; 132226584Sdim 133226584Sdim} // end anonymous namespace 134226584Sdim 135360784Sdim/// \returns true if this signed displacement fits in a 8-bit sign-extended 136360784Sdim/// field. 137360784Sdimstatic bool isDisp8(int Value) { return Value == (int8_t)Value; } 138226584Sdim 139360784Sdim/// \returns true if this signed displacement fits in a 8-bit compressed 140360784Sdim/// dispacement field. 141360784Sdimstatic bool isCDisp8(uint64_t TSFlags, int Value, int &CValue) { 142280031Sdim assert(((TSFlags & X86II::EncodingMask) == X86II::EVEX) && 143261991Sdim "Compressed 8-bit displacement is only valid for EVEX inst."); 144261991Sdim 145276479Sdim unsigned CD8_Scale = 146360784Sdim (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift; 147276479Sdim if (CD8_Scale == 0) { 148261991Sdim CValue = Value; 149261991Sdim return isDisp8(Value); 150261991Sdim } 151261991Sdim 152276479Sdim unsigned Mask = CD8_Scale - 1; 153276479Sdim assert((CD8_Scale & Mask) == 0 && "Invalid memory object size."); 154276479Sdim if (Value & Mask) // Unaligned offset 155261991Sdim return false; 156276479Sdim Value /= (int)CD8_Scale; 157309124Sdim bool Ret = (Value == (int8_t)Value); 158261991Sdim 159261991Sdim if (Ret) 160261991Sdim CValue = Value; 161261991Sdim return Ret; 162261991Sdim} 163261991Sdim 164360784Sdim/// \returns the appropriate fixup kind to use for an immediate in an 165360784Sdim/// instruction with the specified TSFlags. 166226584Sdimstatic MCFixupKind getImmFixupKind(uint64_t TSFlags) { 167226584Sdim unsigned Size = X86II::getSizeOfImm(TSFlags); 168226584Sdim bool isPCRel = X86II::isImmPCRel(TSFlags); 169226584Sdim 170276479Sdim if (X86II::isImmSigned(TSFlags)) { 171276479Sdim switch (Size) { 172360784Sdim default: 173360784Sdim llvm_unreachable("Unsupported signed fixup size!"); 174360784Sdim case 4: 175360784Sdim return MCFixupKind(X86::reloc_signed_4byte); 176276479Sdim } 177276479Sdim } 178226584Sdim return MCFixup::getKindForSize(Size, isPCRel); 179226584Sdim} 180226584Sdim 181360784Sdim/// \param Op operand # of the memory operand. 182360784Sdim/// 183360784Sdim/// \returns true if the specified instruction has a 16-bit memory operand. 184360784Sdimstatic bool is16BitMemOperand(const MCInst &MI, unsigned Op, 185360784Sdim const MCSubtargetInfo &STI) { 186360784Sdim const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); 187360784Sdim const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); 188360784Sdim const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp); 189226584Sdim 190360784Sdim if (STI.hasFeature(X86::Mode16Bit) && BaseReg.getReg() == 0 && Disp.isImm() && 191360784Sdim Disp.getImm() < 0x10000) 192360784Sdim return true; 193226584Sdim if ((BaseReg.getReg() != 0 && 194360784Sdim X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || 195360784Sdim (IndexReg.getReg() != 0 && 196360784Sdim X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) 197360784Sdim return true; 198360784Sdim return false; 199360784Sdim} 200360784Sdim 201360784Sdim/// \param Op operand # of the memory operand. 202360784Sdim/// 203360784Sdim/// \returns true if the specified instruction has a 32-bit memory operand. 204360784Sdimstatic bool is32BitMemOperand(const MCInst &MI, unsigned Op) { 205360784Sdim const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); 206360784Sdim const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); 207360784Sdim 208360784Sdim if ((BaseReg.getReg() != 0 && 209226584Sdim X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || 210226584Sdim (IndexReg.getReg() != 0 && 211226584Sdim X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) 212226584Sdim return true; 213309124Sdim if (BaseReg.getReg() == X86::EIP) { 214309124Sdim assert(IndexReg.getReg() == 0 && "Invalid eip-based address."); 215309124Sdim return true; 216309124Sdim } 217341825Sdim if (IndexReg.getReg() == X86::EIZ) 218341825Sdim return true; 219226584Sdim return false; 220226584Sdim} 221226584Sdim 222360784Sdim/// \param Op operand # of the memory operand. 223360784Sdim/// 224360784Sdim/// \returns true if the specified instruction has a 64-bit memory operand. 225234353Sdim#ifndef NDEBUG 226360784Sdimstatic bool is64BitMemOperand(const MCInst &MI, unsigned Op) { 227360784Sdim const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); 228360784Sdim const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); 229234353Sdim 230234353Sdim if ((BaseReg.getReg() != 0 && 231234353Sdim X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || 232234353Sdim (IndexReg.getReg() != 0 && 233234353Sdim X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg()))) 234234353Sdim return true; 235234353Sdim return false; 236234353Sdim} 237234353Sdim#endif 238234353Sdim 239360784Sdimenum GlobalOffsetTableExprKind { GOT_None, GOT_Normal, GOT_SymDiff }; 240360784Sdim 241360784Sdim/// Check if this expression starts with _GLOBAL_OFFSET_TABLE_ and if it is 242360784Sdim/// of the form _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on 243360784Sdim/// ELF i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that 244360784Sdim/// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start of a 245360784Sdim/// binary expression. 246234353Sdimstatic GlobalOffsetTableExprKind 247360784SdimstartsWithGlobalOffsetTable(const MCExpr *Expr) { 248276479Sdim const MCExpr *RHS = nullptr; 249226584Sdim if (Expr->getKind() == MCExpr::Binary) { 250226584Sdim const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr); 251226584Sdim Expr = BE->getLHS(); 252234353Sdim RHS = BE->getRHS(); 253226584Sdim } 254226584Sdim 255226584Sdim if (Expr->getKind() != MCExpr::SymbolRef) 256234353Sdim return GOT_None; 257226584Sdim 258360784Sdim const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr); 259226584Sdim const MCSymbol &S = Ref->getSymbol(); 260234353Sdim if (S.getName() != "_GLOBAL_OFFSET_TABLE_") 261234353Sdim return GOT_None; 262234353Sdim if (RHS && RHS->getKind() == MCExpr::SymbolRef) 263234353Sdim return GOT_SymDiff; 264234353Sdim return GOT_Normal; 265226584Sdim} 266226584Sdim 267360784Sdimstatic bool hasSecRelSymbolRef(const MCExpr *Expr) { 268251662Sdim if (Expr->getKind() == MCExpr::SymbolRef) { 269360784Sdim const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr); 270251662Sdim return Ref->getKind() == MCSymbolRefExpr::VK_SECREL; 271251662Sdim } 272251662Sdim return false; 273251662Sdim} 274251662Sdim 275360784Sdimstatic bool isPCRel32Branch(const MCInst &MI, const MCInstrInfo &MCII) { 276341825Sdim unsigned Opcode = MI.getOpcode(); 277341825Sdim const MCInstrDesc &Desc = MCII.get(Opcode); 278341825Sdim if ((Opcode != X86::CALL64pcrel32 && Opcode != X86::JMP_4) || 279341825Sdim getImmFixupKind(Desc.TSFlags) != FK_PCRel_4) 280341825Sdim return false; 281341825Sdim 282341825Sdim unsigned CurOp = X86II::getOperandBias(Desc); 283341825Sdim const MCOperand &Op = MI.getOperand(CurOp); 284341825Sdim if (!Op.isExpr()) 285341825Sdim return false; 286341825Sdim 287341825Sdim const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(Op.getExpr()); 288341825Sdim return Ref && Ref->getKind() == MCSymbolRefExpr::VK_None; 289341825Sdim} 290341825Sdim 291360784Sdimvoid X86MCCodeEmitter::emitImmediate(const MCOperand &DispOp, SMLoc Loc, 292360784Sdim unsigned Size, MCFixupKind FixupKind, 293360784Sdim unsigned &CurByte, raw_ostream &OS, 294360784Sdim SmallVectorImpl<MCFixup> &Fixups, 295360784Sdim int ImmOffset) const { 296276479Sdim const MCExpr *Expr = nullptr; 297226584Sdim if (DispOp.isImm()) { 298226584Sdim // If this is a simple integer displacement that doesn't require a 299226584Sdim // relocation, emit it now. 300360784Sdim if (FixupKind != FK_PCRel_1 && FixupKind != FK_PCRel_2 && 301226584Sdim FixupKind != FK_PCRel_4) { 302360784Sdim emitConstant(DispOp.getImm() + ImmOffset, Size, CurByte, OS); 303226584Sdim return; 304226584Sdim } 305288943Sdim Expr = MCConstantExpr::create(DispOp.getImm(), Ctx); 306226584Sdim } else { 307226584Sdim Expr = DispOp.getExpr(); 308226584Sdim } 309226584Sdim 310226584Sdim // If we have an immoffset, add it to the expression. 311360784Sdim if ((FixupKind == FK_Data_4 || FixupKind == FK_Data_8 || 312234353Sdim FixupKind == MCFixupKind(X86::reloc_signed_4byte))) { 313360784Sdim GlobalOffsetTableExprKind Kind = startsWithGlobalOffsetTable(Expr); 314234353Sdim if (Kind != GOT_None) { 315234353Sdim assert(ImmOffset == 0); 316226584Sdim 317276479Sdim if (Size == 8) { 318276479Sdim FixupKind = MCFixupKind(X86::reloc_global_offset_table8); 319276479Sdim } else { 320276479Sdim assert(Size == 4); 321276479Sdim FixupKind = MCFixupKind(X86::reloc_global_offset_table); 322276479Sdim } 323276479Sdim 324234353Sdim if (Kind == GOT_Normal) 325234353Sdim ImmOffset = CurByte; 326234353Sdim } else if (Expr->getKind() == MCExpr::SymbolRef) { 327360784Sdim if (hasSecRelSymbolRef(Expr)) { 328234353Sdim FixupKind = MCFixupKind(FK_SecRel_4); 329234353Sdim } 330251662Sdim } else if (Expr->getKind() == MCExpr::Binary) { 331360784Sdim const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr *>(Expr); 332360784Sdim if (hasSecRelSymbolRef(Bin->getLHS()) || 333360784Sdim hasSecRelSymbolRef(Bin->getRHS())) { 334251662Sdim FixupKind = MCFixupKind(FK_SecRel_4); 335251662Sdim } 336234353Sdim } 337226584Sdim } 338226584Sdim 339226584Sdim // If the fixup is pc-relative, we need to bias the value to be relative to 340226584Sdim // the start of the field, not the end of the field. 341226584Sdim if (FixupKind == FK_PCRel_4 || 342226584Sdim FixupKind == MCFixupKind(X86::reloc_riprel_4byte) || 343309124Sdim FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load) || 344309124Sdim FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax) || 345341825Sdim FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax_rex) || 346341825Sdim FixupKind == MCFixupKind(X86::reloc_branch_4byte_pcrel)) { 347226584Sdim ImmOffset -= 4; 348341825Sdim // If this is a pc-relative load off _GLOBAL_OFFSET_TABLE_: 349341825Sdim // leaq _GLOBAL_OFFSET_TABLE_(%rip), %r15 350341825Sdim // this needs to be a GOTPC32 relocation. 351360784Sdim if (startsWithGlobalOffsetTable(Expr) != GOT_None) 352341825Sdim FixupKind = MCFixupKind(X86::reloc_global_offset_table); 353341825Sdim } 354226584Sdim if (FixupKind == FK_PCRel_2) 355226584Sdim ImmOffset -= 2; 356226584Sdim if (FixupKind == FK_PCRel_1) 357226584Sdim ImmOffset -= 1; 358226584Sdim 359226584Sdim if (ImmOffset) 360288943Sdim Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(ImmOffset, Ctx), 361226584Sdim Ctx); 362226584Sdim 363226584Sdim // Emit a symbolic constant as a fixup and 4 zeros. 364288943Sdim Fixups.push_back(MCFixup::create(CurByte, Expr, FixupKind, Loc)); 365360784Sdim emitConstant(0, Size, CurByte, OS); 366226584Sdim} 367226584Sdim 368309124Sdimvoid X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op, 369226584Sdim unsigned RegOpcodeField, 370309124Sdim uint64_t TSFlags, bool Rex, 371309124Sdim unsigned &CurByte, raw_ostream &OS, 372276479Sdim SmallVectorImpl<MCFixup> &Fixups, 373309124Sdim const MCSubtargetInfo &STI) const { 374360784Sdim const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp); 375360784Sdim const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); 376360784Sdim const MCOperand &Scale = MI.getOperand(Op + X86::AddrScaleAmt); 377360784Sdim const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); 378226584Sdim unsigned BaseReg = Base.getReg(); 379280031Sdim bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX; 380226584Sdim 381226584Sdim // Handle %rip relative addressing. 382309124Sdim if (BaseReg == X86::RIP || 383360784Sdim BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode 384360784Sdim assert(STI.hasFeature(X86::Mode64Bit) && 385360784Sdim "Rip-relative addressing requires 64-bit mode"); 386226584Sdim assert(IndexReg.getReg() == 0 && "Invalid rip-relative address"); 387360784Sdim emitByte(modRMByte(0, RegOpcodeField, 5), CurByte, OS); 388226584Sdim 389309124Sdim unsigned Opcode = MI.getOpcode(); 390226584Sdim // movq loads are handled with a special relocation form which allows the 391226584Sdim // linker to eliminate some loads for GOT references which end up in the 392226584Sdim // same linkage unit. 393309124Sdim unsigned FixupKind = [=]() { 394309124Sdim switch (Opcode) { 395309124Sdim default: 396309124Sdim return X86::reloc_riprel_4byte; 397309124Sdim case X86::MOV64rm: 398309124Sdim assert(Rex); 399309124Sdim return X86::reloc_riprel_4byte_movq_load; 400309124Sdim case X86::CALL64m: 401309124Sdim case X86::JMP64m: 402341825Sdim case X86::TAILJMPm64: 403327952Sdim case X86::TEST64mr: 404309124Sdim case X86::ADC64rm: 405309124Sdim case X86::ADD64rm: 406309124Sdim case X86::AND64rm: 407309124Sdim case X86::CMP64rm: 408309124Sdim case X86::OR64rm: 409309124Sdim case X86::SBB64rm: 410309124Sdim case X86::SUB64rm: 411309124Sdim case X86::XOR64rm: 412309124Sdim return Rex ? X86::reloc_riprel_4byte_relax_rex 413309124Sdim : X86::reloc_riprel_4byte_relax; 414309124Sdim } 415309124Sdim }(); 416226584Sdim 417226584Sdim // rip-relative addressing is actually relative to the *next* instruction. 418226584Sdim // Since an immediate can follow the mod/rm byte for an instruction, this 419329410Sdim // means that we need to bias the displacement field of the instruction with 420329410Sdim // the size of the immediate field. If we have this case, add it into the 421226584Sdim // expression to emit. 422329410Sdim // Note: rip-relative addressing using immediate displacement values should 423329410Sdim // not be adjusted, assuming it was the user's intent. 424329410Sdim int ImmSize = !Disp.isImm() && X86II::hasImm(TSFlags) 425329410Sdim ? X86II::getSizeOfImm(TSFlags) 426329410Sdim : 0; 427226584Sdim 428360784Sdim emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), CurByte, OS, 429360784Sdim Fixups, -ImmSize); 430226584Sdim return; 431226584Sdim } 432226584Sdim 433360784Sdim unsigned BaseRegNo = BaseReg ? getX86RegNum(Base) : -1U; 434226584Sdim 435276479Sdim // 16-bit addressing forms of the ModR/M byte have a different encoding for 436276479Sdim // the R/M field and are far more limited in which registers can be used. 437360784Sdim if (is16BitMemOperand(MI, Op, STI)) { 438276479Sdim if (BaseReg) { 439276479Sdim // For 32-bit addressing, the row and column values in Table 2-2 are 440276479Sdim // basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with 441360784Sdim // some special cases. And getX86RegNum reflects that numbering. 442276479Sdim // For 16-bit addressing it's more fun, as shown in the SDM Vol 2A, 443276479Sdim // Table 2-1 "16-Bit Addressing Forms with the ModR/M byte". We can only 444276479Sdim // use SI/DI/BP/BX, which have "row" values 4-7 in no particular order, 445276479Sdim // while values 0-3 indicate the allowed combinations (base+index) of 446276479Sdim // those: 0 for BX+SI, 1 for BX+DI, 2 for BP+SI, 3 for BP+DI. 447276479Sdim // 448276479Sdim // R16Table[] is a lookup from the normal RegNo, to the row values from 449276479Sdim // Table 2-1 for 16-bit addressing modes. Where zero means disallowed. 450360784Sdim static const unsigned R16Table[] = {0, 0, 0, 7, 0, 6, 4, 5}; 451276479Sdim unsigned RMfield = R16Table[BaseRegNo]; 452276479Sdim 453276479Sdim assert(RMfield && "invalid 16-bit base register"); 454276479Sdim 455276479Sdim if (IndexReg.getReg()) { 456360784Sdim unsigned IndexReg16 = R16Table[getX86RegNum(IndexReg)]; 457276479Sdim 458276479Sdim assert(IndexReg16 && "invalid 16-bit index register"); 459276479Sdim // We must have one of SI/DI (4,5), and one of BP/BX (6,7). 460276479Sdim assert(((IndexReg16 ^ RMfield) & 2) && 461276479Sdim "invalid 16-bit base/index register combination"); 462276479Sdim assert(Scale.getImm() == 1 && 463276479Sdim "invalid scale for 16-bit memory reference"); 464276479Sdim 465276479Sdim // Allow base/index to appear in either order (although GAS doesn't). 466276479Sdim if (IndexReg16 & 2) 467276479Sdim RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1); 468276479Sdim else 469276479Sdim RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1); 470276479Sdim } 471276479Sdim 472276479Sdim if (Disp.isImm() && isDisp8(Disp.getImm())) { 473341825Sdim if (Disp.getImm() == 0 && RMfield != 6) { 474276479Sdim // There is no displacement; just the register. 475360784Sdim emitByte(modRMByte(0, RegOpcodeField, RMfield), CurByte, OS); 476276479Sdim return; 477276479Sdim } 478276479Sdim // Use the [REG]+disp8 form, including for [BP] which cannot be encoded. 479360784Sdim emitByte(modRMByte(1, RegOpcodeField, RMfield), CurByte, OS); 480360784Sdim emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups); 481276479Sdim return; 482276479Sdim } 483276479Sdim // This is the [REG]+disp16 case. 484360784Sdim emitByte(modRMByte(2, RegOpcodeField, RMfield), CurByte, OS); 485276479Sdim } else { 486276479Sdim // There is no BaseReg; this is the plain [disp16] case. 487360784Sdim emitByte(modRMByte(0, RegOpcodeField, 6), CurByte, OS); 488276479Sdim } 489276479Sdim 490276479Sdim // Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases. 491360784Sdim emitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, CurByte, OS, Fixups); 492276479Sdim return; 493276479Sdim } 494276479Sdim 495226584Sdim // Determine whether a SIB byte is needed. 496226584Sdim // If no BaseReg, issue a RIP relative instruction only if the MCE can 497226584Sdim // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table 498226584Sdim // 2-7) and absolute references. 499226584Sdim 500360784Sdim if ( // The SIB byte must be used if there is an index register. 501226584Sdim IndexReg.getReg() == 0 && 502226584Sdim // The SIB byte must be used if the base is ESP/RSP/R12, all of which 503226584Sdim // encode to an R/M value of 4, which indicates that a SIB byte is 504226584Sdim // present. 505226584Sdim BaseRegNo != N86::ESP && 506226584Sdim // If there is no base register and we're in 64-bit mode, we need a SIB 507226584Sdim // byte to emit an addr that is just 'disp32' (the non-RIP relative form). 508360784Sdim (!STI.hasFeature(X86::Mode64Bit) || BaseReg != 0)) { 509226584Sdim 510360784Sdim if (BaseReg == 0) { // [disp32] in X86-32 mode 511360784Sdim emitByte(modRMByte(0, RegOpcodeField, 5), CurByte, OS); 512360784Sdim emitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups); 513226584Sdim return; 514226584Sdim } 515226584Sdim 516226584Sdim // If the base is not EBP/ESP and there is no displacement, use simple 517226584Sdim // indirect register encoding, this handles addresses like [EAX]. The 518226584Sdim // encoding for [EBP] with no displacement means [disp32] so we handle it 519226584Sdim // by emitting a displacement of 0 below. 520353358Sdim if (BaseRegNo != N86::EBP) { 521353358Sdim if (Disp.isImm() && Disp.getImm() == 0) { 522360784Sdim emitByte(modRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS); 523353358Sdim return; 524353358Sdim } 525353358Sdim 526353358Sdim // If the displacement is @tlscall, treat it as a zero. 527353358Sdim if (Disp.isExpr()) { 528353358Sdim auto *Sym = dyn_cast<MCSymbolRefExpr>(Disp.getExpr()); 529353358Sdim if (Sym && Sym->getKind() == MCSymbolRefExpr::VK_TLSCALL) { 530353358Sdim // This is exclusively used by call *a@tlscall(base). The relocation 531353358Sdim // (R_386_TLSCALL or R_X86_64_TLSCALL) applies to the beginning. 532353358Sdim Fixups.push_back(MCFixup::create(0, Sym, FK_NONE, MI.getLoc())); 533360784Sdim emitByte(modRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS); 534353358Sdim return; 535353358Sdim } 536353358Sdim } 537226584Sdim } 538226584Sdim 539226584Sdim // Otherwise, if the displacement fits in a byte, encode as [REG+disp8]. 540261991Sdim if (Disp.isImm()) { 541261991Sdim if (!HasEVEX && isDisp8(Disp.getImm())) { 542360784Sdim emitByte(modRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS); 543360784Sdim emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups); 544261991Sdim return; 545261991Sdim } 546261991Sdim // Try EVEX compressed 8-bit displacement first; if failed, fall back to 547261991Sdim // 32-bit displacement. 548261991Sdim int CDisp8 = 0; 549261991Sdim if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) { 550360784Sdim emitByte(modRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS); 551360784Sdim emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, 552261991Sdim CDisp8 - Disp.getImm()); 553261991Sdim return; 554261991Sdim } 555226584Sdim } 556226584Sdim 557226584Sdim // Otherwise, emit the most general non-SIB encoding: [REG+disp32] 558360784Sdim emitByte(modRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS); 559309124Sdim unsigned Opcode = MI.getOpcode(); 560309124Sdim unsigned FixupKind = Opcode == X86::MOV32rm ? X86::reloc_signed_4byte_relax 561309124Sdim : X86::reloc_signed_4byte; 562360784Sdim emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), CurByte, OS, 563309124Sdim Fixups); 564226584Sdim return; 565226584Sdim } 566226584Sdim 567226584Sdim // We need a SIB byte, so start by outputting the ModR/M byte first 568360784Sdim assert(IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP && 569360784Sdim "Cannot use ESP as index reg!"); 570226584Sdim 571226584Sdim bool ForceDisp32 = false; 572360784Sdim bool ForceDisp8 = false; 573261991Sdim int CDisp8 = 0; 574261991Sdim int ImmOffset = 0; 575226584Sdim if (BaseReg == 0) { 576226584Sdim // If there is no base register, we emit the special case SIB byte with 577226584Sdim // MOD=0, BASE=5, to JUST get the index, scale, and displacement. 578360784Sdim emitByte(modRMByte(0, RegOpcodeField, 4), CurByte, OS); 579226584Sdim ForceDisp32 = true; 580226584Sdim } else if (!Disp.isImm()) { 581226584Sdim // Emit the normal disp32 encoding. 582360784Sdim emitByte(modRMByte(2, RegOpcodeField, 4), CurByte, OS); 583226584Sdim ForceDisp32 = true; 584226584Sdim } else if (Disp.getImm() == 0 && 585226584Sdim // Base reg can't be anything that ends up with '5' as the base 586226584Sdim // reg, it is the magic [*] nomenclature that indicates no base. 587226584Sdim BaseRegNo != N86::EBP) { 588226584Sdim // Emit no displacement ModR/M byte 589360784Sdim emitByte(modRMByte(0, RegOpcodeField, 4), CurByte, OS); 590261991Sdim } else if (!HasEVEX && isDisp8(Disp.getImm())) { 591226584Sdim // Emit the disp8 encoding. 592360784Sdim emitByte(modRMByte(1, RegOpcodeField, 4), CurByte, OS); 593360784Sdim ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 594261991Sdim } else if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) { 595261991Sdim // Emit the disp8 encoding. 596360784Sdim emitByte(modRMByte(1, RegOpcodeField, 4), CurByte, OS); 597360784Sdim ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 598261991Sdim ImmOffset = CDisp8 - Disp.getImm(); 599226584Sdim } else { 600226584Sdim // Emit the normal disp32 encoding. 601360784Sdim emitByte(modRMByte(2, RegOpcodeField, 4), CurByte, OS); 602226584Sdim } 603226584Sdim 604226584Sdim // Calculate what the SS field value should be... 605360784Sdim static const unsigned SSTable[] = {~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3}; 606226584Sdim unsigned SS = SSTable[Scale.getImm()]; 607226584Sdim 608226584Sdim if (BaseReg == 0) { 609226584Sdim // Handle the SIB byte for the case where there is no base, see Intel 610226584Sdim // Manual 2A, table 2-7. The displacement has already been output. 611226584Sdim unsigned IndexRegNo; 612226584Sdim if (IndexReg.getReg()) 613360784Sdim IndexRegNo = getX86RegNum(IndexReg); 614226584Sdim else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5) 615226584Sdim IndexRegNo = 4; 616360784Sdim emitSIBByte(SS, IndexRegNo, 5, CurByte, OS); 617226584Sdim } else { 618226584Sdim unsigned IndexRegNo; 619226584Sdim if (IndexReg.getReg()) 620360784Sdim IndexRegNo = getX86RegNum(IndexReg); 621226584Sdim else 622360784Sdim IndexRegNo = 4; // For example [ESP+1*<noreg>+4] 623360784Sdim emitSIBByte(SS, IndexRegNo, getX86RegNum(Base), CurByte, OS); 624226584Sdim } 625226584Sdim 626226584Sdim // Do we need to output a displacement? 627226584Sdim if (ForceDisp8) 628360784Sdim emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, 629360784Sdim ImmOffset); 630226584Sdim else if (ForceDisp32 || Disp.getImm() != 0) 631360784Sdim emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), 632234353Sdim CurByte, OS, Fixups); 633226584Sdim} 634226584Sdim 635360784Sdimvoid X86MCCodeEmitter::emitPrefixImpl(uint64_t TSFlags, unsigned &CurOp, 636360784Sdim unsigned &CurByte, bool &Rex, 637360784Sdim const MCInst &MI, const MCInstrDesc &Desc, 638360784Sdim const MCSubtargetInfo &STI, 639360784Sdim raw_ostream &OS) const { 640360784Sdim // Determine where the memory operand starts, if present. 641360784Sdim int MemoryOperand = X86II::getMemoryOperandNo(TSFlags); 642360784Sdim if (MemoryOperand != -1) 643360784Sdim MemoryOperand += CurOp; 644360784Sdim 645360784Sdim // Emit segment override opcode prefix as needed. 646360784Sdim if (MemoryOperand >= 0) 647360784Sdim emitSegmentOverridePrefix(CurByte, MemoryOperand + X86::AddrSegmentReg, MI, 648360784Sdim OS); 649360784Sdim 650360784Sdim // Emit the repeat opcode prefix as needed. 651360784Sdim unsigned Flags = MI.getFlags(); 652360784Sdim if (TSFlags & X86II::REP || Flags & X86::IP_HAS_REPEAT) 653360784Sdim emitByte(0xF3, CurByte, OS); 654360784Sdim if (Flags & X86::IP_HAS_REPEAT_NE) 655360784Sdim emitByte(0xF2, CurByte, OS); 656360784Sdim 657360784Sdim // Emit the address size opcode prefix as needed. 658360784Sdim bool need_address_override; 659360784Sdim uint64_t AdSize = TSFlags & X86II::AdSizeMask; 660360784Sdim if ((STI.hasFeature(X86::Mode16Bit) && AdSize == X86II::AdSize32) || 661360784Sdim (STI.hasFeature(X86::Mode32Bit) && AdSize == X86II::AdSize16) || 662360784Sdim (STI.hasFeature(X86::Mode64Bit) && AdSize == X86II::AdSize32)) { 663360784Sdim need_address_override = true; 664360784Sdim } else if (MemoryOperand < 0) { 665360784Sdim need_address_override = false; 666360784Sdim } else if (STI.hasFeature(X86::Mode64Bit)) { 667360784Sdim assert(!is16BitMemOperand(MI, MemoryOperand, STI)); 668360784Sdim need_address_override = is32BitMemOperand(MI, MemoryOperand); 669360784Sdim } else if (STI.hasFeature(X86::Mode32Bit)) { 670360784Sdim assert(!is64BitMemOperand(MI, MemoryOperand)); 671360784Sdim need_address_override = is16BitMemOperand(MI, MemoryOperand, STI); 672360784Sdim } else { 673360784Sdim assert(STI.hasFeature(X86::Mode16Bit)); 674360784Sdim assert(!is64BitMemOperand(MI, MemoryOperand)); 675360784Sdim need_address_override = !is16BitMemOperand(MI, MemoryOperand, STI); 676360784Sdim } 677360784Sdim 678360784Sdim if (need_address_override) 679360784Sdim emitByte(0x67, CurByte, OS); 680360784Sdim 681360784Sdim // Encoding type for this instruction. 682360784Sdim uint64_t Encoding = TSFlags & X86II::EncodingMask; 683360784Sdim if (Encoding == 0) 684360784Sdim Rex = emitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, STI, OS); 685360784Sdim else 686360784Sdim emitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS); 687360784Sdim 688360784Sdim uint64_t Form = TSFlags & X86II::FormMask; 689360784Sdim switch (Form) { 690360784Sdim default: 691360784Sdim break; 692360784Sdim case X86II::RawFrmDstSrc: { 693360784Sdim unsigned siReg = MI.getOperand(1).getReg(); 694360784Sdim assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) || 695360784Sdim (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) || 696360784Sdim (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) && 697360784Sdim "SI and DI register sizes do not match"); 698360784Sdim // Emit segment override opcode prefix as needed (not for %ds). 699360784Sdim if (MI.getOperand(2).getReg() != X86::DS) 700360784Sdim emitSegmentOverridePrefix(CurByte, 2, MI, OS); 701360784Sdim // Emit AdSize prefix as needed. 702360784Sdim if ((!STI.hasFeature(X86::Mode32Bit) && siReg == X86::ESI) || 703360784Sdim (STI.hasFeature(X86::Mode32Bit) && siReg == X86::SI)) 704360784Sdim emitByte(0x67, CurByte, OS); 705360784Sdim CurOp += 3; // Consume operands. 706360784Sdim break; 707360784Sdim } 708360784Sdim case X86II::RawFrmSrc: { 709360784Sdim unsigned siReg = MI.getOperand(0).getReg(); 710360784Sdim // Emit segment override opcode prefix as needed (not for %ds). 711360784Sdim if (MI.getOperand(1).getReg() != X86::DS) 712360784Sdim emitSegmentOverridePrefix(CurByte, 1, MI, OS); 713360784Sdim // Emit AdSize prefix as needed. 714360784Sdim if ((!STI.hasFeature(X86::Mode32Bit) && siReg == X86::ESI) || 715360784Sdim (STI.hasFeature(X86::Mode32Bit) && siReg == X86::SI)) 716360784Sdim emitByte(0x67, CurByte, OS); 717360784Sdim CurOp += 2; // Consume operands. 718360784Sdim break; 719360784Sdim } 720360784Sdim case X86II::RawFrmDst: { 721360784Sdim unsigned siReg = MI.getOperand(0).getReg(); 722360784Sdim // Emit AdSize prefix as needed. 723360784Sdim if ((!STI.hasFeature(X86::Mode32Bit) && siReg == X86::EDI) || 724360784Sdim (STI.hasFeature(X86::Mode32Bit) && siReg == X86::DI)) 725360784Sdim emitByte(0x67, CurByte, OS); 726360784Sdim ++CurOp; // Consume operand. 727360784Sdim break; 728360784Sdim } 729360784Sdim case X86II::RawFrmMemOffs: { 730360784Sdim // Emit segment override opcode prefix as needed. 731360784Sdim emitSegmentOverridePrefix(CurByte, 1, MI, OS); 732360784Sdim break; 733360784Sdim } 734360784Sdim } 735360784Sdim} 736360784Sdim 737360784Sdim/// emitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix 738226584Sdim/// called VEX. 739360784Sdimvoid X86MCCodeEmitter::emitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 740226584Sdim int MemOperand, const MCInst &MI, 741226584Sdim const MCInstrDesc &Desc, 742226584Sdim raw_ostream &OS) const { 743280031Sdim assert(!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX."); 744226584Sdim 745280031Sdim uint64_t Encoding = TSFlags & X86II::EncodingMask; 746280031Sdim bool HasEVEX_K = TSFlags & X86II::EVEX_K; 747280031Sdim bool HasVEX_4V = TSFlags & X86II::VEX_4V; 748280031Sdim bool HasEVEX_RC = TSFlags & X86II::EVEX_RC; 749280031Sdim 750226584Sdim // VEX_R: opcode externsion equivalent to REX.R in 751226584Sdim // 1's complement (inverted) form 752226584Sdim // 753226584Sdim // 1: Same as REX_R=0 (must be 1 in 32-bit mode) 754226584Sdim // 0: Same as REX_R=1 (64 bit mode only) 755226584Sdim // 756309124Sdim uint8_t VEX_R = 0x1; 757309124Sdim uint8_t EVEX_R2 = 0x1; 758226584Sdim 759226584Sdim // VEX_X: equivalent to REX.X, only used when a 760226584Sdim // register is used for index in SIB Byte. 761226584Sdim // 762226584Sdim // 1: Same as REX.X=0 (must be 1 in 32-bit mode) 763226584Sdim // 0: Same as REX.X=1 (64-bit mode only) 764309124Sdim uint8_t VEX_X = 0x1; 765226584Sdim 766226584Sdim // VEX_B: 767226584Sdim // 768226584Sdim // 1: Same as REX_B=0 (ignored in 32-bit mode) 769226584Sdim // 0: Same as REX_B=1 (64 bit mode only) 770226584Sdim // 771309124Sdim uint8_t VEX_B = 0x1; 772226584Sdim 773226584Sdim // VEX_W: opcode specific (use like REX.W, or used for 774226584Sdim // opcode extension, or ignored, depending on the opcode byte) 775309124Sdim uint8_t VEX_W = (TSFlags & X86II::VEX_W) ? 1 : 0; 776226584Sdim 777226584Sdim // VEX_5M (VEX m-mmmmm field): 778226584Sdim // 779226584Sdim // 0b00000: Reserved for future use 780226584Sdim // 0b00001: implied 0F leading opcode 781226584Sdim // 0b00010: implied 0F 38 leading opcode bytes 782226584Sdim // 0b00011: implied 0F 3A leading opcode bytes 783226584Sdim // 0b00100-0b11111: Reserved for future use 784234353Sdim // 0b01000: XOP map select - 08h instructions with imm byte 785261991Sdim // 0b01001: XOP map select - 09h instructions with no imm byte 786261991Sdim // 0b01010: XOP map select - 0Ah instructions with imm dword 787309124Sdim uint8_t VEX_5M; 788309124Sdim switch (TSFlags & X86II::OpMapMask) { 789360784Sdim default: 790360784Sdim llvm_unreachable("Invalid prefix!"); 791360784Sdim case X86II::TB: 792360784Sdim VEX_5M = 0x1; 793360784Sdim break; // 0F 794360784Sdim case X86II::T8: 795360784Sdim VEX_5M = 0x2; 796360784Sdim break; // 0F 38 797360784Sdim case X86II::TA: 798360784Sdim VEX_5M = 0x3; 799360784Sdim break; // 0F 3A 800360784Sdim case X86II::XOP8: 801360784Sdim VEX_5M = 0x8; 802360784Sdim break; 803360784Sdim case X86II::XOP9: 804360784Sdim VEX_5M = 0x9; 805360784Sdim break; 806360784Sdim case X86II::XOPA: 807360784Sdim VEX_5M = 0xA; 808360784Sdim break; 809309124Sdim } 810226584Sdim 811226584Sdim // VEX_4V (VEX vvvv field): a register specifier 812226584Sdim // (in 1's complement form) or 1111 if unused. 813309124Sdim uint8_t VEX_4V = 0xf; 814309124Sdim uint8_t EVEX_V2 = 0x1; 815226584Sdim 816309124Sdim // EVEX_L2/VEX_L (Vector Length): 817226584Sdim // 818309124Sdim // L2 L 819309124Sdim // 0 0: scalar or 128-bit vector 820309124Sdim // 0 1: 256-bit vector 821309124Sdim // 1 0: 512-bit vector 822226584Sdim // 823309124Sdim uint8_t VEX_L = (TSFlags & X86II::VEX_L) ? 1 : 0; 824309124Sdim uint8_t EVEX_L2 = (TSFlags & X86II::EVEX_L2) ? 1 : 0; 825226584Sdim 826226584Sdim // VEX_PP: opcode extension providing equivalent 827226584Sdim // functionality of a SIMD prefix 828226584Sdim // 829226584Sdim // 0b00: None 830226584Sdim // 0b01: 66 831226584Sdim // 0b10: F3 832226584Sdim // 0b11: F2 833226584Sdim // 834341825Sdim uint8_t VEX_PP = 0; 835309124Sdim switch (TSFlags & X86II::OpPrefixMask) { 836360784Sdim case X86II::PD: 837360784Sdim VEX_PP = 0x1; 838360784Sdim break; // 66 839360784Sdim case X86II::XS: 840360784Sdim VEX_PP = 0x2; 841360784Sdim break; // F3 842360784Sdim case X86II::XD: 843360784Sdim VEX_PP = 0x3; 844360784Sdim break; // F2 845309124Sdim } 846226584Sdim 847261991Sdim // EVEX_U 848309124Sdim uint8_t EVEX_U = 1; // Always '1' so far 849261991Sdim 850261991Sdim // EVEX_z 851309124Sdim uint8_t EVEX_z = (HasEVEX_K && (TSFlags & X86II::EVEX_Z)) ? 1 : 0; 852261991Sdim 853261991Sdim // EVEX_b 854309124Sdim uint8_t EVEX_b = (TSFlags & X86II::EVEX_B) ? 1 : 0; 855261991Sdim 856276479Sdim // EVEX_rc 857309124Sdim uint8_t EVEX_rc = 0; 858276479Sdim 859261991Sdim // EVEX_aaa 860309124Sdim uint8_t EVEX_aaa = 0; 861261991Sdim 862276479Sdim bool EncodeRC = false; 863226584Sdim 864226584Sdim // Classify VEX_B, VEX_4V, VEX_R, VEX_X 865239462Sdim unsigned NumOps = Desc.getNumOperands(); 866276479Sdim unsigned CurOp = X86II::getOperandBias(Desc); 867239462Sdim 868226584Sdim switch (TSFlags & X86II::FormMask) { 869360784Sdim default: 870360784Sdim llvm_unreachable("Unexpected form in emitVEXOpcodePrefix!"); 871276479Sdim case X86II::RawFrm: 872276479Sdim break; 873226584Sdim case X86II::MRMDestMem: { 874226584Sdim // MRMDestMem instructions forms: 875226584Sdim // MemAddr, src1(ModR/M) 876226584Sdim // MemAddr, src1(VEX_4V), src2(ModR/M) 877226584Sdim // MemAddr, src1(ModR/M), imm8 878226584Sdim // 879309124Sdim unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); 880309124Sdim VEX_B = ~(BaseRegEnc >> 3) & 1; 881360784Sdim unsigned IndexRegEnc = 882360784Sdim getX86RegEncoding(MI, MemOperand + X86::AddrIndexReg); 883309124Sdim VEX_X = ~(IndexRegEnc >> 3) & 1; 884309124Sdim if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV. 885309124Sdim EVEX_V2 = ~(IndexRegEnc >> 4) & 1; 886226584Sdim 887261991Sdim CurOp += X86::AddrNumOperands; 888226584Sdim 889261991Sdim if (HasEVEX_K) 890309124Sdim EVEX_aaa = getX86RegEncoding(MI, CurOp++); 891261991Sdim 892261991Sdim if (HasVEX_4V) { 893309124Sdim unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 894309124Sdim VEX_4V = ~VRegEnc & 0xf; 895309124Sdim EVEX_V2 = ~(VRegEnc >> 4) & 1; 896261991Sdim } 897261991Sdim 898309124Sdim unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 899309124Sdim VEX_R = ~(RegEnc >> 3) & 1; 900309124Sdim EVEX_R2 = ~(RegEnc >> 4) & 1; 901226584Sdim break; 902226584Sdim } 903309124Sdim case X86II::MRMSrcMem: { 904226584Sdim // MRMSrcMem instructions forms: 905226584Sdim // src1(ModR/M), MemAddr 906226584Sdim // src1(ModR/M), src2(VEX_4V), MemAddr 907226584Sdim // src1(ModR/M), MemAddr, imm8 908314564Sdim // src1(ModR/M), MemAddr, src2(Imm[7:4]) 909226584Sdim // 910234353Sdim // FMA4: 911314564Sdim // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4]) 912309124Sdim unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 913309124Sdim VEX_R = ~(RegEnc >> 3) & 1; 914309124Sdim EVEX_R2 = ~(RegEnc >> 4) & 1; 915226584Sdim 916261991Sdim if (HasEVEX_K) 917309124Sdim EVEX_aaa = getX86RegEncoding(MI, CurOp++); 918261991Sdim 919261991Sdim if (HasVEX_4V) { 920309124Sdim unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 921309124Sdim VEX_4V = ~VRegEnc & 0xf; 922309124Sdim EVEX_V2 = ~(VRegEnc >> 4) & 1; 923261991Sdim } 924226584Sdim 925309124Sdim unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); 926309124Sdim VEX_B = ~(BaseRegEnc >> 3) & 1; 927360784Sdim unsigned IndexRegEnc = 928360784Sdim getX86RegEncoding(MI, MemOperand + X86::AddrIndexReg); 929309124Sdim VEX_X = ~(IndexRegEnc >> 3) & 1; 930309124Sdim if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV. 931309124Sdim EVEX_V2 = ~(IndexRegEnc >> 4) & 1; 932234353Sdim 933226584Sdim break; 934309124Sdim } 935314564Sdim case X86II::MRMSrcMem4VOp3: { 936314564Sdim // Instruction format for 4VOp3: 937314564Sdim // src1(ModR/M), MemAddr, src3(VEX_4V) 938314564Sdim unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 939314564Sdim VEX_R = ~(RegEnc >> 3) & 1; 940314564Sdim 941314564Sdim unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); 942314564Sdim VEX_B = ~(BaseRegEnc >> 3) & 1; 943360784Sdim unsigned IndexRegEnc = 944360784Sdim getX86RegEncoding(MI, MemOperand + X86::AddrIndexReg); 945314564Sdim VEX_X = ~(IndexRegEnc >> 3) & 1; 946314564Sdim 947314564Sdim VEX_4V = ~getX86RegEncoding(MI, CurOp + X86::AddrNumOperands) & 0xf; 948314564Sdim break; 949314564Sdim } 950314564Sdim case X86II::MRMSrcMemOp4: { 951314564Sdim // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M), 952314564Sdim unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 953314564Sdim VEX_R = ~(RegEnc >> 3) & 1; 954314564Sdim 955314564Sdim unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 956314564Sdim VEX_4V = ~VRegEnc & 0xf; 957314564Sdim 958314564Sdim unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); 959314564Sdim VEX_B = ~(BaseRegEnc >> 3) & 1; 960360784Sdim unsigned IndexRegEnc = 961360784Sdim getX86RegEncoding(MI, MemOperand + X86::AddrIndexReg); 962314564Sdim VEX_X = ~(IndexRegEnc >> 3) & 1; 963314564Sdim break; 964314564Sdim } 965360784Sdim case X86II::MRM0m: 966360784Sdim case X86II::MRM1m: 967360784Sdim case X86II::MRM2m: 968360784Sdim case X86II::MRM3m: 969360784Sdim case X86II::MRM4m: 970360784Sdim case X86II::MRM5m: 971360784Sdim case X86II::MRM6m: 972360784Sdim case X86II::MRM7m: { 973226584Sdim // MRM[0-9]m instructions forms: 974226584Sdim // MemAddr 975234353Sdim // src1(VEX_4V), MemAddr 976261991Sdim if (HasVEX_4V) { 977309124Sdim unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 978309124Sdim VEX_4V = ~VRegEnc & 0xf; 979309124Sdim EVEX_V2 = ~(VRegEnc >> 4) & 1; 980261991Sdim } 981234353Sdim 982261991Sdim if (HasEVEX_K) 983309124Sdim EVEX_aaa = getX86RegEncoding(MI, CurOp++); 984261991Sdim 985309124Sdim unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); 986309124Sdim VEX_B = ~(BaseRegEnc >> 3) & 1; 987360784Sdim unsigned IndexRegEnc = 988360784Sdim getX86RegEncoding(MI, MemOperand + X86::AddrIndexReg); 989309124Sdim VEX_X = ~(IndexRegEnc >> 3) & 1; 990360784Sdim if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV. 991360784Sdim EVEX_V2 = ~(IndexRegEnc >> 4) & 1; 992360784Sdim 993226584Sdim break; 994234353Sdim } 995309124Sdim case X86II::MRMSrcReg: { 996226584Sdim // MRMSrcReg instructions forms: 997314564Sdim // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4]) 998226584Sdim // dst(ModR/M), src1(ModR/M) 999226584Sdim // dst(ModR/M), src1(ModR/M), imm8 1000226584Sdim // 1001249423Sdim // FMA4: 1002314564Sdim // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M), 1003309124Sdim unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 1004309124Sdim VEX_R = ~(RegEnc >> 3) & 1; 1005309124Sdim EVEX_R2 = ~(RegEnc >> 4) & 1; 1006226584Sdim 1007261991Sdim if (HasEVEX_K) 1008309124Sdim EVEX_aaa = getX86RegEncoding(MI, CurOp++); 1009249423Sdim 1010261991Sdim if (HasVEX_4V) { 1011309124Sdim unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 1012309124Sdim VEX_4V = ~VRegEnc & 0xf; 1013309124Sdim EVEX_V2 = ~(VRegEnc >> 4) & 1; 1014261991Sdim } 1015261991Sdim 1016309124Sdim RegEnc = getX86RegEncoding(MI, CurOp++); 1017309124Sdim VEX_B = ~(RegEnc >> 3) & 1; 1018309124Sdim VEX_X = ~(RegEnc >> 4) & 1; 1019314564Sdim 1020276479Sdim if (EVEX_b) { 1021276479Sdim if (HasEVEX_RC) { 1022360784Sdim unsigned RcOperand = NumOps - 1; 1023276479Sdim assert(RcOperand >= CurOp); 1024353358Sdim EVEX_rc = MI.getOperand(RcOperand).getImm(); 1025353358Sdim assert(EVEX_rc <= 3 && "Invalid rounding control!"); 1026276479Sdim } 1027276479Sdim EncodeRC = true; 1028280031Sdim } 1029226584Sdim break; 1030309124Sdim } 1031314564Sdim case X86II::MRMSrcReg4VOp3: { 1032314564Sdim // Instruction format for 4VOp3: 1033314564Sdim // src1(ModR/M), src2(ModR/M), src3(VEX_4V) 1034314564Sdim unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 1035314564Sdim VEX_R = ~(RegEnc >> 3) & 1; 1036314564Sdim 1037314564Sdim RegEnc = getX86RegEncoding(MI, CurOp++); 1038314564Sdim VEX_B = ~(RegEnc >> 3) & 1; 1039314564Sdim 1040314564Sdim VEX_4V = ~getX86RegEncoding(MI, CurOp++) & 0xf; 1041314564Sdim break; 1042314564Sdim } 1043314564Sdim case X86II::MRMSrcRegOp4: { 1044314564Sdim // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M), 1045314564Sdim unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 1046314564Sdim VEX_R = ~(RegEnc >> 3) & 1; 1047314564Sdim 1048314564Sdim unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 1049314564Sdim VEX_4V = ~VRegEnc & 0xf; 1050314564Sdim 1051314564Sdim // Skip second register source (encoded in Imm[7:4]) 1052314564Sdim ++CurOp; 1053314564Sdim 1054314564Sdim RegEnc = getX86RegEncoding(MI, CurOp++); 1055314564Sdim VEX_B = ~(RegEnc >> 3) & 1; 1056314564Sdim VEX_X = ~(RegEnc >> 4) & 1; 1057314564Sdim break; 1058314564Sdim } 1059309124Sdim case X86II::MRMDestReg: { 1060226584Sdim // MRMDestReg instructions forms: 1061226584Sdim // dst(ModR/M), src(ModR/M) 1062226584Sdim // dst(ModR/M), src(ModR/M), imm8 1063249423Sdim // dst(ModR/M), src1(VEX_4V), src2(ModR/M) 1064309124Sdim unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 1065309124Sdim VEX_B = ~(RegEnc >> 3) & 1; 1066309124Sdim VEX_X = ~(RegEnc >> 4) & 1; 1067249423Sdim 1068261991Sdim if (HasEVEX_K) 1069309124Sdim EVEX_aaa = getX86RegEncoding(MI, CurOp++); 1070249423Sdim 1071261991Sdim if (HasVEX_4V) { 1072309124Sdim unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 1073309124Sdim VEX_4V = ~VRegEnc & 0xf; 1074309124Sdim EVEX_V2 = ~(VRegEnc >> 4) & 1; 1075261991Sdim } 1076261991Sdim 1077309124Sdim RegEnc = getX86RegEncoding(MI, CurOp++); 1078309124Sdim VEX_R = ~(RegEnc >> 3) & 1; 1079309124Sdim EVEX_R2 = ~(RegEnc >> 4) & 1; 1080276479Sdim if (EVEX_b) 1081276479Sdim EncodeRC = true; 1082226584Sdim break; 1083309124Sdim } 1084360784Sdim case X86II::MRM0r: 1085360784Sdim case X86II::MRM1r: 1086360784Sdim case X86II::MRM2r: 1087360784Sdim case X86II::MRM3r: 1088360784Sdim case X86II::MRM4r: 1089360784Sdim case X86II::MRM5r: 1090360784Sdim case X86II::MRM6r: 1091360784Sdim case X86II::MRM7r: { 1092226584Sdim // MRM0r-MRM7r instructions forms: 1093226584Sdim // dst(VEX_4V), src(ModR/M), imm8 1094261991Sdim if (HasVEX_4V) { 1095309124Sdim unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 1096309124Sdim VEX_4V = ~VRegEnc & 0xf; 1097309124Sdim EVEX_V2 = ~(VRegEnc >> 4) & 1; 1098276479Sdim } 1099261991Sdim if (HasEVEX_K) 1100309124Sdim EVEX_aaa = getX86RegEncoding(MI, CurOp++); 1101261991Sdim 1102309124Sdim unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 1103309124Sdim VEX_B = ~(RegEnc >> 3) & 1; 1104309124Sdim VEX_X = ~(RegEnc >> 4) & 1; 1105226584Sdim break; 1106226584Sdim } 1107309124Sdim } 1108226584Sdim 1109276479Sdim if (Encoding == X86II::VEX || Encoding == X86II::XOP) { 1110261991Sdim // VEX opcode prefix can have 2 or 3 bytes 1111261991Sdim // 1112261991Sdim // 3 bytes: 1113261991Sdim // +-----+ +--------------+ +-------------------+ 1114261991Sdim // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp | 1115261991Sdim // +-----+ +--------------+ +-------------------+ 1116261991Sdim // 2 bytes: 1117261991Sdim // +-----+ +-------------------+ 1118261991Sdim // | C5h | | R | vvvv | L | pp | 1119261991Sdim // +-----+ +-------------------+ 1120261991Sdim // 1121276479Sdim // XOP uses a similar prefix: 1122276479Sdim // +-----+ +--------------+ +-------------------+ 1123276479Sdim // | 8Fh | | RXB | m-mmmm | | W | vvvv | L | pp | 1124276479Sdim // +-----+ +--------------+ +-------------------+ 1125309124Sdim uint8_t LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3); 1126226584Sdim 1127276479Sdim // Can we use the 2 byte VEX prefix? 1128360784Sdim if (!(MI.getFlags() & X86::IP_USE_VEX3) && Encoding == X86II::VEX && 1129360784Sdim VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { 1130360784Sdim emitByte(0xC5, CurByte, OS); 1131360784Sdim emitByte(LastByte | (VEX_R << 7), CurByte, OS); 1132261991Sdim return; 1133261991Sdim } 1134261991Sdim 1135261991Sdim // 3 byte VEX prefix 1136360784Sdim emitByte(Encoding == X86II::XOP ? 0x8F : 0xC4, CurByte, OS); 1137360784Sdim emitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS); 1138360784Sdim emitByte(LastByte | (VEX_W << 7), CurByte, OS); 1139261991Sdim } else { 1140276479Sdim assert(Encoding == X86II::EVEX && "unknown encoding!"); 1141261991Sdim // EVEX opcode prefix can have 4 bytes 1142261991Sdim // 1143261991Sdim // +-----+ +--------------+ +-------------------+ +------------------------+ 1144261991Sdim // | 62h | | RXBR' | 00mm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa | 1145261991Sdim // +-----+ +--------------+ +-------------------+ +------------------------+ 1146360784Sdim assert((VEX_5M & 0x3) == VEX_5M && 1147360784Sdim "More than 2 significant bits in VEX.m-mmmm fields for EVEX!"); 1148261991Sdim 1149360784Sdim emitByte(0x62, CurByte, OS); 1150360784Sdim emitByte((VEX_R << 7) | (VEX_X << 6) | (VEX_B << 5) | (EVEX_R2 << 4) | 1151360784Sdim VEX_5M, 1152360784Sdim CurByte, OS); 1153360784Sdim emitByte((VEX_W << 7) | (VEX_4V << 3) | (EVEX_U << 2) | VEX_PP, CurByte, 1154360784Sdim OS); 1155276479Sdim if (EncodeRC) 1156360784Sdim emitByte((EVEX_z << 7) | (EVEX_rc << 5) | (EVEX_b << 4) | (EVEX_V2 << 3) | 1157360784Sdim EVEX_aaa, 1158360784Sdim CurByte, OS); 1159276479Sdim else 1160360784Sdim emitByte((EVEX_z << 7) | (EVEX_L2 << 6) | (VEX_L << 5) | (EVEX_b << 4) | 1161360784Sdim (EVEX_V2 << 3) | EVEX_aaa, 1162360784Sdim CurByte, OS); 1163226584Sdim } 1164226584Sdim} 1165226584Sdim 1166360784Sdim/// Determine if the MCInst has to be encoded with a X86-64 REX prefix which 1167360784Sdim/// specifies 1) 64-bit instructions, 2) non-default operand size, and 3) use 1168360784Sdim/// of X86-64 extended registers. 1169360784Sdimuint8_t X86MCCodeEmitter::determineREXPrefix(const MCInst &MI, uint64_t TSFlags, 1170309124Sdim int MemOperand, 1171309124Sdim const MCInstrDesc &Desc) const { 1172309124Sdim uint8_t REX = 0; 1173296417Sdim bool UsesHighByteReg = false; 1174296417Sdim 1175226584Sdim if (TSFlags & X86II::REX_W) 1176226584Sdim REX |= 1 << 3; // set REX.W 1177226584Sdim 1178360784Sdim if (MI.getNumOperands() == 0) 1179360784Sdim return REX; 1180226584Sdim 1181226584Sdim unsigned NumOps = MI.getNumOperands(); 1182309124Sdim unsigned CurOp = X86II::getOperandBias(Desc); 1183226584Sdim 1184226584Sdim // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 1185309124Sdim for (unsigned i = CurOp; i != NumOps; ++i) { 1186226584Sdim const MCOperand &MO = MI.getOperand(i); 1187360784Sdim if (!MO.isReg()) 1188360784Sdim continue; 1189226584Sdim unsigned Reg = MO.getReg(); 1190296417Sdim if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH) 1191296417Sdim UsesHighByteReg = true; 1192314564Sdim if (X86II::isX86_64NonExtLowByteReg(Reg)) 1193360784Sdim // FIXME: The caller of determineREXPrefix slaps this prefix onto anything 1194314564Sdim // that returns non-zero. 1195314564Sdim REX |= 0x40; // REX fixed encoding prefix 1196226584Sdim } 1197226584Sdim 1198226584Sdim switch (TSFlags & X86II::FormMask) { 1199309124Sdim case X86II::AddRegFrm: 1200314564Sdim REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B 1201309124Sdim break; 1202226584Sdim case X86II::MRMSrcReg: 1203353358Sdim case X86II::MRMSrcRegCC: 1204314564Sdim REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R 1205314564Sdim REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B 1206226584Sdim break; 1207353358Sdim case X86II::MRMSrcMem: 1208353358Sdim case X86II::MRMSrcMemCC: 1209360784Sdim REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R 1210360784Sdim REX |= isREXExtendedReg(MI, MemOperand + X86::AddrBaseReg) << 0; // REX.B 1211360784Sdim REX |= isREXExtendedReg(MI, MemOperand + X86::AddrIndexReg) << 1; // REX.X 1212309124Sdim CurOp += X86::AddrNumOperands; 1213226584Sdim break; 1214309124Sdim case X86II::MRMDestReg: 1215314564Sdim REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B 1216314564Sdim REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R 1217309124Sdim break; 1218309124Sdim case X86II::MRMDestMem: 1219360784Sdim REX |= isREXExtendedReg(MI, MemOperand + X86::AddrBaseReg) << 0; // REX.B 1220360784Sdim REX |= isREXExtendedReg(MI, MemOperand + X86::AddrIndexReg) << 1; // REX.X 1221309124Sdim CurOp += X86::AddrNumOperands; 1222314564Sdim REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R 1223309124Sdim break; 1224360784Sdim case X86II::MRMXmCC: 1225360784Sdim case X86II::MRMXm: 1226360784Sdim case X86II::MRM0m: 1227360784Sdim case X86II::MRM1m: 1228360784Sdim case X86II::MRM2m: 1229360784Sdim case X86II::MRM3m: 1230360784Sdim case X86II::MRM4m: 1231360784Sdim case X86II::MRM5m: 1232360784Sdim case X86II::MRM6m: 1233360784Sdim case X86II::MRM7m: 1234360784Sdim REX |= isREXExtendedReg(MI, MemOperand + X86::AddrBaseReg) << 0; // REX.B 1235360784Sdim REX |= isREXExtendedReg(MI, MemOperand + X86::AddrIndexReg) << 1; // REX.X 1236226584Sdim break; 1237360784Sdim case X86II::MRMXrCC: 1238360784Sdim case X86II::MRMXr: 1239360784Sdim case X86II::MRM0r: 1240360784Sdim case X86II::MRM1r: 1241360784Sdim case X86II::MRM2r: 1242360784Sdim case X86II::MRM3r: 1243360784Sdim case X86II::MRM4r: 1244360784Sdim case X86II::MRM5r: 1245360784Sdim case X86II::MRM6r: 1246360784Sdim case X86II::MRM7r: 1247314564Sdim REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B 1248226584Sdim break; 1249226584Sdim } 1250296417Sdim if (REX && UsesHighByteReg) 1251360784Sdim report_fatal_error( 1252360784Sdim "Cannot encode high byte register in REX-prefixed instruction"); 1253296417Sdim 1254226584Sdim return REX; 1255226584Sdim} 1256226584Sdim 1257360784Sdim/// Emit segment override opcode prefix as needed. 1258360784Sdimvoid X86MCCodeEmitter::emitSegmentOverridePrefix(unsigned &CurByte, 1259276479Sdim unsigned SegOperand, 1260276479Sdim const MCInst &MI, 1261276479Sdim raw_ostream &OS) const { 1262276479Sdim // Check for explicit segment override on memory operand. 1263276479Sdim switch (MI.getOperand(SegOperand).getReg()) { 1264360784Sdim default: 1265360784Sdim llvm_unreachable("Unknown segment register!"); 1266360784Sdim case 0: 1267360784Sdim break; 1268360784Sdim case X86::CS: 1269360784Sdim emitByte(0x2E, CurByte, OS); 1270360784Sdim break; 1271360784Sdim case X86::SS: 1272360784Sdim emitByte(0x36, CurByte, OS); 1273360784Sdim break; 1274360784Sdim case X86::DS: 1275360784Sdim emitByte(0x3E, CurByte, OS); 1276360784Sdim break; 1277360784Sdim case X86::ES: 1278360784Sdim emitByte(0x26, CurByte, OS); 1279360784Sdim break; 1280360784Sdim case X86::FS: 1281360784Sdim emitByte(0x64, CurByte, OS); 1282360784Sdim break; 1283360784Sdim case X86::GS: 1284360784Sdim emitByte(0x65, CurByte, OS); 1285360784Sdim break; 1286226584Sdim } 1287226584Sdim} 1288226584Sdim 1289309124Sdim/// Emit all instruction prefixes prior to the opcode. 1290226584Sdim/// 1291360784Sdim/// \param MemOperand the operand # of the start of a memory operand if present. 1292360784Sdim/// If not present, it is -1. 1293309124Sdim/// 1294360784Sdim/// \returns true if a REX prefix was used. 1295309124Sdimbool X86MCCodeEmitter::emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 1296226584Sdim int MemOperand, const MCInst &MI, 1297226584Sdim const MCInstrDesc &Desc, 1298276479Sdim const MCSubtargetInfo &STI, 1299226584Sdim raw_ostream &OS) const { 1300309124Sdim bool Ret = false; 1301226584Sdim // Emit the operand size opcode prefix as needed. 1302360784Sdim if ((TSFlags & X86II::OpSizeMask) == 1303360784Sdim (STI.hasFeature(X86::Mode16Bit) ? X86II::OpSize32 : X86II::OpSize16)) 1304360784Sdim emitByte(0x66, CurByte, OS); 1305226584Sdim 1306280031Sdim // Emit the LOCK opcode prefix. 1307327952Sdim if (TSFlags & X86II::LOCK || MI.getFlags() & X86::IP_HAS_LOCK) 1308360784Sdim emitByte(0xF0, CurByte, OS); 1309280031Sdim 1310341825Sdim // Emit the NOTRACK opcode prefix. 1311341825Sdim if (TSFlags & X86II::NOTRACK || MI.getFlags() & X86::IP_HAS_NOTRACK) 1312360784Sdim emitByte(0x3E, CurByte, OS); 1313341825Sdim 1314276479Sdim switch (TSFlags & X86II::OpPrefixMask) { 1315360784Sdim case X86II::PD: // 66 1316360784Sdim emitByte(0x66, CurByte, OS); 1317226584Sdim break; 1318360784Sdim case X86II::XS: // F3 1319360784Sdim emitByte(0xF3, CurByte, OS); 1320234353Sdim break; 1321360784Sdim case X86II::XD: // F2 1322360784Sdim emitByte(0xF2, CurByte, OS); 1323226584Sdim break; 1324226584Sdim } 1325226584Sdim 1326226584Sdim // Handle REX prefix. 1327226584Sdim // FIXME: Can this come before F2 etc to simplify emission? 1328360784Sdim if (STI.hasFeature(X86::Mode64Bit)) { 1329360784Sdim if (uint8_t REX = determineREXPrefix(MI, TSFlags, MemOperand, Desc)) { 1330360784Sdim emitByte(0x40 | REX, CurByte, OS); 1331309124Sdim Ret = true; 1332309124Sdim } 1333327952Sdim } else { 1334327952Sdim assert(!(TSFlags & X86II::REX_W) && "REX.W requires 64bit mode."); 1335226584Sdim } 1336226584Sdim 1337226584Sdim // 0x0F escape code must be emitted just before the opcode. 1338276479Sdim switch (TSFlags & X86II::OpMapMask) { 1339360784Sdim case X86II::TB: // Two-byte opcode map 1340360784Sdim case X86II::T8: // 0F 38 1341360784Sdim case X86II::TA: // 0F 3A 1342360784Sdim case X86II::ThreeDNow: // 0F 0F, second 0F emitted by caller. 1343360784Sdim emitByte(0x0F, CurByte, OS); 1344276479Sdim break; 1345276479Sdim } 1346226584Sdim 1347276479Sdim switch (TSFlags & X86II::OpMapMask) { 1348360784Sdim case X86II::T8: // 0F 38 1349360784Sdim emitByte(0x38, CurByte, OS); 1350226584Sdim break; 1351360784Sdim case X86II::TA: // 0F 3A 1352360784Sdim emitByte(0x3A, CurByte, OS); 1353226584Sdim break; 1354226584Sdim } 1355309124Sdim return Ret; 1356226584Sdim} 1357226584Sdim 1358360784Sdimvoid X86MCCodeEmitter::emitPrefix(const MCInst &MI, raw_ostream &OS, 1359360784Sdim const MCSubtargetInfo &STI) const { 1360226584Sdim unsigned Opcode = MI.getOpcode(); 1361226584Sdim const MCInstrDesc &Desc = MCII.get(Opcode); 1362226584Sdim uint64_t TSFlags = Desc.TSFlags; 1363226584Sdim 1364226584Sdim // Pseudo instructions don't get encoded. 1365226584Sdim if ((TSFlags & X86II::FormMask) == X86II::Pseudo) 1366226584Sdim return; 1367226584Sdim 1368360784Sdim unsigned CurOp = X86II::getOperandBias(Desc); 1369360784Sdim 1370360784Sdim // Keep track of the current byte being emitted. 1371360784Sdim unsigned CurByte = 0; 1372360784Sdim 1373360784Sdim bool Rex = false; 1374360784Sdim emitPrefixImpl(TSFlags, CurOp, CurByte, Rex, MI, Desc, STI, OS); 1375360784Sdim} 1376360784Sdim 1377360784Sdimvoid X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, 1378360784Sdim SmallVectorImpl<MCFixup> &Fixups, 1379360784Sdim const MCSubtargetInfo &STI) const { 1380360784Sdim unsigned Opcode = MI.getOpcode(); 1381360784Sdim const MCInstrDesc &Desc = MCII.get(Opcode); 1382360784Sdim uint64_t TSFlags = Desc.TSFlags; 1383360784Sdim 1384360784Sdim // Pseudo instructions don't get encoded. 1385360784Sdim if ((TSFlags & X86II::FormMask) == X86II::Pseudo) 1386360784Sdim return; 1387360784Sdim 1388226584Sdim unsigned NumOps = Desc.getNumOperands(); 1389251662Sdim unsigned CurOp = X86II::getOperandBias(Desc); 1390226584Sdim 1391226584Sdim // Keep track of the current byte being emitted. 1392226584Sdim unsigned CurByte = 0; 1393226584Sdim 1394360784Sdim bool Rex = false; 1395360784Sdim emitPrefixImpl(TSFlags, CurOp, CurByte, Rex, MI, Desc, STI, OS); 1396226584Sdim 1397226584Sdim // It uses the VEX.VVVV field? 1398280031Sdim bool HasVEX_4V = TSFlags & X86II::VEX_4V; 1399314564Sdim bool HasVEX_I8Reg = (TSFlags & X86II::ImmMask) == X86II::Imm8Reg; 1400226584Sdim 1401261991Sdim // It uses the EVEX.aaa field? 1402280031Sdim bool HasEVEX_K = TSFlags & X86II::EVEX_K; 1403280031Sdim bool HasEVEX_RC = TSFlags & X86II::EVEX_RC; 1404280031Sdim 1405309124Sdim // Used if a register is encoded in 7:4 of immediate. 1406309124Sdim unsigned I8RegNum = 0; 1407309124Sdim 1408309124Sdim uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); 1409226584Sdim 1410341825Sdim if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow) 1411360784Sdim BaseOpcode = 0x0F; // Weird 3DNow! encoding. 1412226584Sdim 1413353358Sdim unsigned OpcodeOffset = 0; 1414353358Sdim 1415309124Sdim uint64_t Form = TSFlags & X86II::FormMask; 1416309124Sdim switch (Form) { 1417360784Sdim default: 1418360784Sdim errs() << "FORM: " << Form << "\n"; 1419234353Sdim llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!"); 1420226584Sdim case X86II::Pseudo: 1421234353Sdim llvm_unreachable("Pseudo instruction shouldn't be emitted"); 1422360784Sdim case X86II::RawFrmDstSrc: 1423360784Sdim case X86II::RawFrmSrc: 1424360784Sdim case X86II::RawFrmDst: 1425360784Sdim emitByte(BaseOpcode, CurByte, OS); 1426276479Sdim break; 1427353358Sdim case X86II::AddCCFrm: { 1428353358Sdim // This will be added to the opcode in the fallthrough. 1429353358Sdim OpcodeOffset = MI.getOperand(NumOps - 1).getImm(); 1430353358Sdim assert(OpcodeOffset < 16 && "Unexpected opcode offset!"); 1431353358Sdim --NumOps; // Drop the operand from the end. 1432353358Sdim LLVM_FALLTHROUGH; 1433353358Sdim case X86II::RawFrm: 1434360784Sdim emitByte(BaseOpcode + OpcodeOffset, CurByte, OS); 1435341825Sdim 1436360784Sdim if (!STI.hasFeature(X86::Mode64Bit) || !isPCRel32Branch(MI, MCII)) 1437341825Sdim break; 1438341825Sdim 1439341825Sdim const MCOperand &Op = MI.getOperand(CurOp++); 1440360784Sdim emitImmediate(Op, MI.getLoc(), X86II::getSizeOfImm(TSFlags), 1441341825Sdim MCFixupKind(X86::reloc_branch_4byte_pcrel), CurByte, OS, 1442341825Sdim Fixups); 1443226584Sdim break; 1444341825Sdim } 1445276479Sdim case X86II::RawFrmMemOffs: 1446360784Sdim emitByte(BaseOpcode, CurByte, OS); 1447360784Sdim emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1448276479Sdim X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1449276479Sdim CurByte, OS, Fixups); 1450276479Sdim ++CurOp; // skip segment operand 1451276479Sdim break; 1452226584Sdim case X86II::RawFrmImm8: 1453360784Sdim emitByte(BaseOpcode, CurByte, OS); 1454360784Sdim emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1455226584Sdim X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1456226584Sdim CurByte, OS, Fixups); 1457360784Sdim emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte, 1458234353Sdim OS, Fixups); 1459226584Sdim break; 1460226584Sdim case X86II::RawFrmImm16: 1461360784Sdim emitByte(BaseOpcode, CurByte, OS); 1462360784Sdim emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1463226584Sdim X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1464226584Sdim CurByte, OS, Fixups); 1465360784Sdim emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte, 1466234353Sdim OS, Fixups); 1467226584Sdim break; 1468226584Sdim 1469226584Sdim case X86II::AddRegFrm: 1470360784Sdim emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++)), CurByte, OS); 1471226584Sdim break; 1472226584Sdim 1473309124Sdim case X86II::MRMDestReg: { 1474360784Sdim emitByte(BaseOpcode, CurByte, OS); 1475309124Sdim unsigned SrcRegNum = CurOp + 1; 1476249423Sdim 1477261991Sdim if (HasEVEX_K) // Skip writemask 1478309124Sdim ++SrcRegNum; 1479261991Sdim 1480249423Sdim if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1481249423Sdim ++SrcRegNum; 1482249423Sdim 1483360784Sdim emitRegModRMByte(MI.getOperand(CurOp), 1484360784Sdim getX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS); 1485249423Sdim CurOp = SrcRegNum + 1; 1486226584Sdim break; 1487309124Sdim } 1488309124Sdim case X86II::MRMDestMem: { 1489360784Sdim emitByte(BaseOpcode, CurByte, OS); 1490309124Sdim unsigned SrcRegNum = CurOp + X86::AddrNumOperands; 1491226584Sdim 1492261991Sdim if (HasEVEX_K) // Skip writemask 1493309124Sdim ++SrcRegNum; 1494261991Sdim 1495226584Sdim if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1496239462Sdim ++SrcRegNum; 1497226584Sdim 1498360784Sdim emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(SrcRegNum)), TSFlags, 1499309124Sdim Rex, CurByte, OS, Fixups, STI); 1500226584Sdim CurOp = SrcRegNum + 1; 1501226584Sdim break; 1502309124Sdim } 1503309124Sdim case X86II::MRMSrcReg: { 1504360784Sdim emitByte(BaseOpcode, CurByte, OS); 1505309124Sdim unsigned SrcRegNum = CurOp + 1; 1506226584Sdim 1507261991Sdim if (HasEVEX_K) // Skip writemask 1508309124Sdim ++SrcRegNum; 1509261991Sdim 1510226584Sdim if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1511239462Sdim ++SrcRegNum; 1512226584Sdim 1513360784Sdim emitRegModRMByte(MI.getOperand(SrcRegNum), 1514360784Sdim getX86RegNum(MI.getOperand(CurOp)), CurByte, OS); 1515309124Sdim CurOp = SrcRegNum + 1; 1516314564Sdim if (HasVEX_I8Reg) 1517309124Sdim I8RegNum = getX86RegEncoding(MI, CurOp++); 1518276479Sdim // do not count the rounding control operand 1519276479Sdim if (HasEVEX_RC) 1520309124Sdim --NumOps; 1521226584Sdim break; 1522309124Sdim } 1523314564Sdim case X86II::MRMSrcReg4VOp3: { 1524360784Sdim emitByte(BaseOpcode, CurByte, OS); 1525314564Sdim unsigned SrcRegNum = CurOp + 1; 1526314564Sdim 1527360784Sdim emitRegModRMByte(MI.getOperand(SrcRegNum), 1528360784Sdim getX86RegNum(MI.getOperand(CurOp)), CurByte, OS); 1529314564Sdim CurOp = SrcRegNum + 1; 1530314564Sdim ++CurOp; // Encoded in VEX.VVVV 1531314564Sdim break; 1532314564Sdim } 1533314564Sdim case X86II::MRMSrcRegOp4: { 1534360784Sdim emitByte(BaseOpcode, CurByte, OS); 1535314564Sdim unsigned SrcRegNum = CurOp + 1; 1536314564Sdim 1537314564Sdim // Skip 1st src (which is encoded in VEX_VVVV) 1538314564Sdim ++SrcRegNum; 1539314564Sdim 1540314564Sdim // Capture 2nd src (which is encoded in Imm[7:4]) 1541314564Sdim assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg"); 1542314564Sdim I8RegNum = getX86RegEncoding(MI, SrcRegNum++); 1543314564Sdim 1544360784Sdim emitRegModRMByte(MI.getOperand(SrcRegNum), 1545360784Sdim getX86RegNum(MI.getOperand(CurOp)), CurByte, OS); 1546314564Sdim CurOp = SrcRegNum + 1; 1547314564Sdim break; 1548314564Sdim } 1549353358Sdim case X86II::MRMSrcRegCC: { 1550353358Sdim unsigned FirstOp = CurOp++; 1551353358Sdim unsigned SecondOp = CurOp++; 1552353358Sdim 1553353358Sdim unsigned CC = MI.getOperand(CurOp++).getImm(); 1554360784Sdim emitByte(BaseOpcode + CC, CurByte, OS); 1555353358Sdim 1556360784Sdim emitRegModRMByte(MI.getOperand(SecondOp), 1557360784Sdim getX86RegNum(MI.getOperand(FirstOp)), CurByte, OS); 1558353358Sdim break; 1559353358Sdim } 1560226584Sdim case X86II::MRMSrcMem: { 1561360784Sdim unsigned FirstMemOp = CurOp + 1; 1562261991Sdim 1563309124Sdim if (HasEVEX_K) // Skip writemask 1564261991Sdim ++FirstMemOp; 1565261991Sdim 1566309124Sdim if (HasVEX_4V) 1567360784Sdim ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV). 1568226584Sdim 1569360784Sdim emitByte(BaseOpcode, CurByte, OS); 1570226584Sdim 1571360784Sdim emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)), 1572309124Sdim TSFlags, Rex, CurByte, OS, Fixups, STI); 1573309124Sdim CurOp = FirstMemOp + X86::AddrNumOperands; 1574314564Sdim if (HasVEX_I8Reg) 1575309124Sdim I8RegNum = getX86RegEncoding(MI, CurOp++); 1576226584Sdim break; 1577226584Sdim } 1578314564Sdim case X86II::MRMSrcMem4VOp3: { 1579360784Sdim unsigned FirstMemOp = CurOp + 1; 1580226584Sdim 1581360784Sdim emitByte(BaseOpcode, CurByte, OS); 1582314564Sdim 1583360784Sdim emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)), 1584314564Sdim TSFlags, Rex, CurByte, OS, Fixups, STI); 1585314564Sdim CurOp = FirstMemOp + X86::AddrNumOperands; 1586314564Sdim ++CurOp; // Encoded in VEX.VVVV. 1587314564Sdim break; 1588314564Sdim } 1589314564Sdim case X86II::MRMSrcMemOp4: { 1590360784Sdim unsigned FirstMemOp = CurOp + 1; 1591314564Sdim 1592360784Sdim ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV). 1593314564Sdim 1594314564Sdim // Capture second register source (encoded in Imm[7:4]) 1595314564Sdim assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg"); 1596314564Sdim I8RegNum = getX86RegEncoding(MI, FirstMemOp++); 1597314564Sdim 1598360784Sdim emitByte(BaseOpcode, CurByte, OS); 1599314564Sdim 1600360784Sdim emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)), 1601314564Sdim TSFlags, Rex, CurByte, OS, Fixups, STI); 1602314564Sdim CurOp = FirstMemOp + X86::AddrNumOperands; 1603314564Sdim break; 1604314564Sdim } 1605353358Sdim case X86II::MRMSrcMemCC: { 1606353358Sdim unsigned RegOp = CurOp++; 1607353358Sdim unsigned FirstMemOp = CurOp; 1608353358Sdim CurOp = FirstMemOp + X86::AddrNumOperands; 1609314564Sdim 1610353358Sdim unsigned CC = MI.getOperand(CurOp++).getImm(); 1611360784Sdim emitByte(BaseOpcode + CC, CurByte, OS); 1612353358Sdim 1613360784Sdim emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(RegOp)), 1614353358Sdim TSFlags, Rex, CurByte, OS, Fixups, STI); 1615353358Sdim break; 1616353358Sdim } 1617353358Sdim 1618353358Sdim case X86II::MRMXrCC: { 1619353358Sdim unsigned RegOp = CurOp++; 1620353358Sdim 1621353358Sdim unsigned CC = MI.getOperand(CurOp++).getImm(); 1622360784Sdim emitByte(BaseOpcode + CC, CurByte, OS); 1623360784Sdim emitRegModRMByte(MI.getOperand(RegOp), 0, CurByte, OS); 1624353358Sdim break; 1625353358Sdim } 1626353358Sdim 1627276479Sdim case X86II::MRMXr: 1628360784Sdim case X86II::MRM0r: 1629360784Sdim case X86II::MRM1r: 1630360784Sdim case X86II::MRM2r: 1631360784Sdim case X86II::MRM3r: 1632360784Sdim case X86II::MRM4r: 1633360784Sdim case X86II::MRM5r: 1634360784Sdim case X86II::MRM6r: 1635360784Sdim case X86II::MRM7r: 1636226584Sdim if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1637239462Sdim ++CurOp; 1638276479Sdim if (HasEVEX_K) // Skip writemask 1639276479Sdim ++CurOp; 1640360784Sdim emitByte(BaseOpcode, CurByte, OS); 1641360784Sdim emitRegModRMByte(MI.getOperand(CurOp++), 1642360784Sdim (Form == X86II::MRMXr) ? 0 : Form - X86II::MRM0r, CurByte, 1643360784Sdim OS); 1644226584Sdim break; 1645276479Sdim 1646353358Sdim case X86II::MRMXmCC: { 1647353358Sdim unsigned FirstMemOp = CurOp; 1648353358Sdim CurOp = FirstMemOp + X86::AddrNumOperands; 1649353358Sdim 1650353358Sdim unsigned CC = MI.getOperand(CurOp++).getImm(); 1651360784Sdim emitByte(BaseOpcode + CC, CurByte, OS); 1652353358Sdim 1653353358Sdim emitMemModRMByte(MI, FirstMemOp, 0, TSFlags, Rex, CurByte, OS, Fixups, STI); 1654353358Sdim break; 1655353358Sdim } 1656353358Sdim 1657276479Sdim case X86II::MRMXm: 1658360784Sdim case X86II::MRM0m: 1659360784Sdim case X86II::MRM1m: 1660360784Sdim case X86II::MRM2m: 1661360784Sdim case X86II::MRM3m: 1662360784Sdim case X86II::MRM4m: 1663360784Sdim case X86II::MRM5m: 1664360784Sdim case X86II::MRM6m: 1665360784Sdim case X86II::MRM7m: 1666234353Sdim if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1667239462Sdim ++CurOp; 1668276479Sdim if (HasEVEX_K) // Skip writemask 1669276479Sdim ++CurOp; 1670360784Sdim emitByte(BaseOpcode, CurByte, OS); 1671309124Sdim emitMemModRMByte(MI, CurOp, 1672309124Sdim (Form == X86II::MRMXm) ? 0 : Form - X86II::MRM0m, TSFlags, 1673309124Sdim Rex, CurByte, OS, Fixups, STI); 1674226584Sdim CurOp += X86::AddrNumOperands; 1675226584Sdim break; 1676321369Sdim 1677360784Sdim case X86II::MRM_C0: 1678360784Sdim case X86II::MRM_C1: 1679360784Sdim case X86II::MRM_C2: 1680360784Sdim case X86II::MRM_C3: 1681360784Sdim case X86II::MRM_C4: 1682360784Sdim case X86II::MRM_C5: 1683360784Sdim case X86II::MRM_C6: 1684360784Sdim case X86II::MRM_C7: 1685360784Sdim case X86II::MRM_C8: 1686360784Sdim case X86II::MRM_C9: 1687360784Sdim case X86II::MRM_CA: 1688360784Sdim case X86II::MRM_CB: 1689360784Sdim case X86II::MRM_CC: 1690360784Sdim case X86II::MRM_CD: 1691360784Sdim case X86II::MRM_CE: 1692360784Sdim case X86II::MRM_CF: 1693360784Sdim case X86II::MRM_D0: 1694360784Sdim case X86II::MRM_D1: 1695360784Sdim case X86II::MRM_D2: 1696360784Sdim case X86II::MRM_D3: 1697360784Sdim case X86II::MRM_D4: 1698360784Sdim case X86II::MRM_D5: 1699360784Sdim case X86II::MRM_D6: 1700360784Sdim case X86II::MRM_D7: 1701360784Sdim case X86II::MRM_D8: 1702360784Sdim case X86II::MRM_D9: 1703360784Sdim case X86II::MRM_DA: 1704360784Sdim case X86II::MRM_DB: 1705360784Sdim case X86II::MRM_DC: 1706360784Sdim case X86II::MRM_DD: 1707360784Sdim case X86II::MRM_DE: 1708360784Sdim case X86II::MRM_DF: 1709360784Sdim case X86II::MRM_E0: 1710360784Sdim case X86II::MRM_E1: 1711360784Sdim case X86II::MRM_E2: 1712360784Sdim case X86II::MRM_E3: 1713360784Sdim case X86II::MRM_E4: 1714360784Sdim case X86II::MRM_E5: 1715360784Sdim case X86II::MRM_E6: 1716360784Sdim case X86II::MRM_E7: 1717360784Sdim case X86II::MRM_E8: 1718360784Sdim case X86II::MRM_E9: 1719360784Sdim case X86II::MRM_EA: 1720360784Sdim case X86II::MRM_EB: 1721360784Sdim case X86II::MRM_EC: 1722360784Sdim case X86II::MRM_ED: 1723360784Sdim case X86II::MRM_EE: 1724360784Sdim case X86II::MRM_EF: 1725360784Sdim case X86II::MRM_F0: 1726360784Sdim case X86II::MRM_F1: 1727360784Sdim case X86II::MRM_F2: 1728360784Sdim case X86II::MRM_F3: 1729360784Sdim case X86II::MRM_F4: 1730360784Sdim case X86II::MRM_F5: 1731360784Sdim case X86II::MRM_F6: 1732360784Sdim case X86II::MRM_F7: 1733360784Sdim case X86II::MRM_F8: 1734360784Sdim case X86II::MRM_F9: 1735360784Sdim case X86II::MRM_FA: 1736360784Sdim case X86II::MRM_FB: 1737360784Sdim case X86II::MRM_FC: 1738360784Sdim case X86II::MRM_FD: 1739360784Sdim case X86II::MRM_FE: 1740288943Sdim case X86II::MRM_FF: 1741360784Sdim emitByte(BaseOpcode, CurByte, OS); 1742360784Sdim emitByte(0xC0 + Form - X86II::MRM_C0, CurByte, OS); 1743226584Sdim break; 1744226584Sdim } 1745226584Sdim 1746314564Sdim if (HasVEX_I8Reg) { 1747226584Sdim // The last source register of a 4 operand instruction in AVX is encoded 1748234353Sdim // in bits[7:4] of a immediate byte. 1749309124Sdim assert(I8RegNum < 16 && "Register encoding out of range"); 1750309124Sdim I8RegNum <<= 4; 1751309124Sdim if (CurOp != NumOps) { 1752309124Sdim unsigned Val = MI.getOperand(CurOp++).getImm(); 1753309124Sdim assert(Val < 16 && "Immediate operand value out of range"); 1754309124Sdim I8RegNum |= Val; 1755309124Sdim } 1756360784Sdim emitImmediate(MCOperand::createImm(I8RegNum), MI.getLoc(), 1, FK_Data_1, 1757309124Sdim CurByte, OS, Fixups); 1758309124Sdim } else { 1759309124Sdim // If there is a remaining operand, it must be a trailing immediate. Emit it 1760309124Sdim // according to the right size for the instruction. Some instructions 1761309124Sdim // (SSE4a extrq and insertq) have two trailing immediates. 1762309124Sdim while (CurOp != NumOps && NumOps - CurOp <= 2) { 1763360784Sdim emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1764276479Sdim X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1765226584Sdim CurByte, OS, Fixups); 1766226584Sdim } 1767226584Sdim } 1768226584Sdim 1769341825Sdim if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow) 1770360784Sdim emitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS); 1771226584Sdim 1772226584Sdim#ifndef NDEBUG 1773226584Sdim // FIXME: Verify. 1774226584Sdim if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) { 1775226584Sdim errs() << "Cannot encode all operands of: "; 1776226584Sdim MI.dump(); 1777226584Sdim errs() << '\n'; 1778226584Sdim abort(); 1779226584Sdim } 1780226584Sdim#endif 1781226584Sdim} 1782321369Sdim 1783321369SdimMCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII, 1784321369Sdim const MCRegisterInfo &MRI, 1785321369Sdim MCContext &Ctx) { 1786321369Sdim return new X86MCCodeEmitter(MCII, Ctx); 1787321369Sdim} 1788