| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIAddIMGInit.cpp | 81 MachineOperand *D16 = TII->getNamedOperand(MI, AMDGPU::OpName::d16); local
89 unsigned D16Val = D16 ? D16->getImm() : 0;
115 // When D16 then we want next whole VGPR after write data.
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| H A D | SIInstrInfo.cpp | 3410 const MachineOperand *D16 = getNamedOperand(MI, AMDGPU::OpName::d16);
3413 if (D16 && D16->getImm() && !ST.hasUnpackedD16VMem())
6370 // Adjust the encoding family to GFX80 for D16 buffer instructions when the
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Support/ |
| H A D | ARMTargetParser.cpp | 177 {"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::D16},
180 {"+vfp3d16", "-vfp3d16", FPUVersion::VFPV3, FPURestriction::D16},
185 {"+vfp4d16", "-vfp4d16", FPUVersion::VFPV4, FPURestriction::D16},
189 {"+fp-armv8d16", "-fp-armv8d16", FPUVersion::VFPV5, FPURestriction::D16},
193 {"+fp64", "-fp64", FPUVersion::VFPV2, FPURestriction::D16},
467 // restriction), D16 (only 16 d-regs) and SP_D16 (16 d-regs
469 // SP restriction without D16. So this test just means 'is it
475 // that SP_D16 has been replaced with just D16, representing adding
480 CandidateFPU.Restriction == ARM::FPURestriction::D16) {
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 82 case D19: case D18: case D17: case D16:
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| H A D | ARMBaseRegisterInfo.cpp | 204 // Reserve D16-D31 if the subtarget doesn't support them.
206 static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");
208 markSuperRegs(Reserved, ARM::D16 + R);
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| /freebsd-11-stable/lib/msun/ld128/ |
| H A D | s_expl.c | 188 * With my coeffs (D11-D16 double):
195 D16 = 4.7628892832607741e-14, /* 0x1.ad00Dfe41feccp-45 */ variable
254 dx * (D14 + dx * (D15 + dx * (D16 +
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Support/ |
| H A D | ARMTargetParser.h | 137 D16, ///< Only 16 D registers member in class:llvm::ARM::FPURestriction
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcRegisterInfo.cpp | 92 for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI)
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 127 case AArch64::D16: return AArch64::B16;
167 case AArch64::B16: return AArch64::D16;
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 120 case AArch64::D16:
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 179 {codeview::RegisterId::ARM64_D16, AArch64::D16},
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 521 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); local
522 if (D16 && AMDGPU::hasPackedD16(STI)) {
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 81 SP::D0, SP::D16, SP::D1, SP::D17,
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 153 Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 337 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1320 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 3934 // Some FPUs only have 16 D registers, so D16-D31 are invalid
3935 if (!hasD32() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
|