/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCRegisterInfo.cpp | 46 unsigned BaseReg = FrameReg; local 51 .addReg(BaseReg) 60 BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass); 61 if (!BaseReg) { 66 BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj); 67 assert(BaseReg && "Register scavenging failed."); 68 LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI) 72 RS->setRegUsed(BaseReg); 76 .addReg(BaseReg, RegState::Define) 94 .addReg(BaseReg, KillStat [all...] |
H A D | ARCOptAddrMode.cpp | 88 // to accomodate increment of register \p BaseReg by \p Incr 90 MachineOperand &Incr, unsigned BaseReg); 93 // of \p BaseReg by \p Offset 94 void fixPastUses(ArrayRef<MachineInstr *> Uses, unsigned BaseReg, 287 Register BaseReg = Ldst->getOperand(BasePos).getReg(); local 297 if (Add->getOperand(0).getReg() == StReg || BaseReg == StReg) { 305 for (MachineInstr &MI : MRI->use_nodbg_instructions(BaseReg)) { 343 MachineOperand &Incr, unsigned BaseReg) { 449 Register BaseReg = Ldst.getOperand(BasePos).getReg(); local 463 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, fals 342 canFixPastUses(const ArrayRef<MachineInstr *> &Uses, MachineOperand &Incr, unsigned BaseReg) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIFixupVectorISel.cpp | 86 unsigned &BaseReg, 115 BaseReg = DefInst->getOperand(2).getReg(); 131 // Chase the BaseReg. 132 MI = MRI.getUniqueVRegDef(BaseReg); 136 BaseReg = MI->getOperand(1).getReg(); 137 BaseRC = MRI.getRegClass(BaseReg); 141 if (!TRI->isSGPRReg(MRI, BaseReg)) 147 MRI.clearKillFlags(BaseReg); 175 unsigned BaseReg = 0; local 178 if (!findSRegBaseAndIndex(Op, BaseReg, IndexRe 85 findSRegBaseAndIndex(MachineOperand *Op, unsigned &BaseReg, unsigned &IndexReg, MachineRegisterInfo &MRI, const SIRegisterInfo *TRI) argument [all...] |
H A D | SIRegisterInfo.h | 90 unsigned BaseReg, int FrameIdx, 93 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 96 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | LocalStackSlotAllocation.cpp | 269 lookupCandidateBaseReg(unsigned BaseReg, argument 278 return TRI->isFrameOffsetLegal(&MI, BaseReg, Offset); 343 unsigned BaseReg = 0; local 387 lookupCandidateBaseReg(BaseReg, BaseOffset, FrameSizeAdjust, 389 LLVM_DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n"); 406 BaseReg, BaseOffset, FrameSizeAdjust, 415 BaseReg = Fn.getRegInfo().createVirtualRegister(RC); 417 LLVM_DEBUG(dbgs() << " Materializing base register " << BaseReg 424 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx, 435 assert(BaseReg ! [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ThumbRegisterInfo.cpp | 126 const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, 132 (BaseReg != 0 && !isARMLowRegister(BaseReg)); 144 assert(BaseReg == ARM::SP && "Unexpected!"); 176 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); 178 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); 189 unsigned BaseReg, int NumBytes, 209 // DestReg and BaseReg are low, high or the stack pointer. 210 // * CopyOpc - DestReg = BaseReg + imm 211 // This will be emitted once if DestReg != BaseReg, an 124 emitThumbRegPlusImmInReg( MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags = MachineInstr::NoFlags) argument 186 emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags) argument [all...] |
H A D | ThumbRegisterInfo.h | 52 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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H A D | ARMBaseRegisterInfo.h | 169 unsigned BaseReg, int FrameIdx, 171 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 173 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
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H A D | Thumb2InstrInfo.cpp | 233 unsigned BaseReg, int NumBytes, 237 if (NumBytes == 0 && DestReg != BaseReg) { 239 .addReg(BaseReg, RegState::Kill) 249 if (DestReg != ARM::SP && DestReg != BaseReg && 271 .addReg(BaseReg) 278 // know anything about BaseReg. t2ADDrr is an invalid 281 // do not generate invalid encoding, put BaseReg first. 283 .addReg(BaseReg) 296 if (DestReg == ARM::SP && BaseReg != ARM::SP) { 299 .addReg(BaseReg) 230 emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument [all...] |
H A D | ARMLoadStoreOptimizer.cpp | 1630 bool RegDeadKill, bool RegUndef, unsigned BaseReg, 1638 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); 1647 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); 1665 Register BaseReg = BaseOp.getReg(); 1673 bool Errata602117 = EvenReg == BaseReg && 1706 .addReg(BaseReg, getKillRegState(BaseKill)) 1714 .addReg(BaseReg, getKillRegState(BaseKill)) 1735 if (isLd && TRI->regsOverlap(EvenReg, BaseReg)) { 1736 assert(!TRI->regsOverlap(OddReg, BaseReg)); 1738 false, BaseReg, fals [all...] |
H A D | ARMBaseRegisterInfo.cpp | 627 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to 631 unsigned BaseReg, int FrameIdx, 646 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 648 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) 655 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, argument 674 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 677 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII, this); 683 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, argument 724 NumBits = (BaseReg == ARM::SP ? 8 : 5); 630 materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FixupLEAs.cpp | 368 Register BaseReg = Base.getReg(); local 377 if (BaseReg != 0) 378 BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit); 387 if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 && 388 (DestReg == BaseReg || DestReg == IndexReg)) { 390 if (DestReg != BaseReg) 391 std::swap(BaseReg, IndexReg); 396 .addReg(BaseReg).addReg(IndexReg) 401 .addReg(BaseReg) 548 Register BaseReg = Base.getReg(); local [all...] |
H A D | X86InsertPrefetch.cpp | 82 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); local 84 return (BaseReg == 0 || 85 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) || 86 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg)) &&
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H A D | X86AsmPrinter.cpp | 285 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); local 290 bool HasBaseReg = BaseReg.getReg() != 0; 292 BaseReg.getReg() == X86::RIP) 350 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); local 357 bool HasBaseReg = BaseReg.getReg() != 0; 359 BaseReg.getReg() == X86::RIP)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64RegisterInfo.h | 99 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, 101 void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, 104 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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H A D | AArch64StorePairSuppress.cpp | 154 Register BaseReg = BaseOp->getReg(); local 155 if (PrevBaseReg == BaseReg) { 164 PrevBaseReg = BaseReg;
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H A D | AArch64LoadStoreOptimizer.cpp | 174 unsigned BaseReg, int Offset); 1176 Register BaseReg = getLdStBaseOp(LoadMI).getReg(); 1201 // it's unnecessary to check if BaseReg is modified by the store itself. 1203 BaseReg == getLdStBaseOp(MI).getReg() && 1218 if (!ModifiedRegUnits.available(BaseReg)) 1447 Register BaseReg = getLdStBaseOp(FirstMI).getReg(); 1513 if (BaseReg == MIBaseReg && ((Offset == MIOffset + OffsetStride) || 1622 if (!ModifiedRegUnits.available(BaseReg)) 1703 unsigned BaseReg, int Offset) { 1719 if (MI.getOperand(0).getReg() != BaseReg || [all...] |
H A D | AArch64FalkorHWPFFix.cpp | 217 Register BaseReg; member in struct:__anon2029::LoadInfo 646 Register BaseReg = MI.getOperand(BaseRegIdx).getReg(); local 647 if (BaseReg == AArch64::SP || BaseReg == AArch64::WSP) 652 LI.BaseReg = BaseReg; 662 unsigned Base = TRI->getEncodingValue(LI.BaseReg); 756 NewLdI.BaseReg = ScratchReg; 773 .addReg(LdI.BaseReg) 786 TII->get(AArch64::ORRXrs), LdI.BaseReg) [all...] |
H A D | AArch64RegisterInfo.cpp | 398 unsigned BaseReg, 405 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx 408 unsigned BaseReg, 420 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); 423 BuildMI(*MBB, Ins, DL, MCID, BaseReg) 429 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 443 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 345 unsigned BaseReg, IndexReg, TmpReg, Scale; member in class:__anon2455::X86AsmParser::IntelExprStateMachine 368 : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), 377 unsigned getBaseReg() { return BaseReg; } 477 // If we already have a BaseReg, then assume this is the IndexReg with 479 if (!BaseReg) { 480 BaseReg = TmpReg; 483 ErrMsg = "BaseReg/IndexReg already set!"; 532 // If we already have a BaseReg, then assume this is the IndexReg with 534 if (!BaseReg) { 535 BaseReg 1043 CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg, unsigned Scale, bool Is64BitMode, StringRef &ErrMsg) argument 1408 CreateMemForInlineAsm( unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier, const InlineAsmIdentifierInfo &Info) argument 1970 unsigned BaseReg = SM.getBaseReg(); local 2294 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; local [all...] |
H A D | X86Operand.h | 62 unsigned BaseReg; member in struct:llvm::final::MemOp 135 if (Mem.BaseReg) 136 OS << ",BaseReg=" << X86IntelInstPrinter::getRegisterName(Mem.BaseReg); 185 return Mem.BaseReg; 635 Res->Mem.BaseReg = 0; 650 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc, 655 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!"); 663 Res->Mem.BaseReg = BaseReg; 649 CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc, SMLoc EndLoc, unsigned Size = 0, StringRef SymName = StringRef(), void *OpDecl = nullptr, unsigned FrontendSize = 0) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/MCParser/ |
H A D | MCTargetAsmParser.h | 45 AOK_IntelExpr // SizeDirective SymDisp [BaseReg + IndexReg * Scale + ImmDisp] 67 StringRef BaseReg; member in struct:llvm::IntelExpr 73 : NeedBracs(false), Imm(0), BaseReg(StringRef()), IndexReg(StringRef()), 75 // [BaseReg + IndexReg * ScaleExpression + OFFSET name + ImmediateExpression] 78 : NeedBracs(needBracs), Imm(imm), BaseReg(baseReg), IndexReg(indexReg), 83 bool hasBaseReg() const { return !BaseReg.empty(); }
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.h | 136 unsigned BaseReg, int FrameIdx, 138 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 140 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 186 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); 190 if (STI.hasFeature(X86::Mode16Bit) && BaseReg.getReg() == 0 && Disp.isImm() && 193 if ((BaseReg.getReg() != 0 && 194 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || 205 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); 208 if ((BaseReg.getReg() != 0 && 209 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || 213 if (BaseReg.getReg() == X86::EIP) { 227 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); 230 if ((BaseReg 378 unsigned BaseReg = Base.getReg(); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/ |
H A D | LanaiAsmParser.cpp | 129 unsigned BaseReg; member in struct:__anon2281::LanaiOperand::MemOp 171 return Mem.BaseReg; 614 Op->Mem.BaseReg = 0; 622 MorphToMemRegReg(unsigned BaseReg, std::unique_ptr<LanaiOperand> Op, argument 626 Op->Mem.BaseReg = BaseReg; 634 MorphToMemRegImm(unsigned BaseReg, std::unique_ptr<LanaiOperand> Op, argument 638 Op->Mem.BaseReg = BaseReg; 885 unsigned BaseReg local [all...] |