1276479Sdim//==- AArch64RegisterInfo.h - AArch64 Register Information Impl --*- C++ -*-==// 2249259Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6249259Sdim// 7249259Sdim//===----------------------------------------------------------------------===// 8249259Sdim// 9276479Sdim// This file contains the AArch64 implementation of the MRegisterInfo class. 10249259Sdim// 11249259Sdim//===----------------------------------------------------------------------===// 12249259Sdim 13280031Sdim#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H 14280031Sdim#define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H 15249259Sdim 16249259Sdim#define GET_REGINFO_HEADER 17249259Sdim#include "AArch64GenRegisterInfo.inc" 18249259Sdim 19249259Sdimnamespace llvm { 20249259Sdim 21276479Sdimclass MachineFunction; 22276479Sdimclass RegScavenger; 23276479Sdimclass TargetRegisterClass; 24288943Sdimclass Triple; 25249259Sdim 26314564Sdimclass AArch64RegisterInfo final : public AArch64GenRegisterInfo { 27288943Sdim const Triple &TT; 28249259Sdim 29276479Sdimpublic: 30288943Sdim AArch64RegisterInfo(const Triple &TT); 31249259Sdim 32344779Sdim // FIXME: This should be tablegen'd like getDwarfRegNum is 33344779Sdim int getSEHRegNum(unsigned i) const { 34344779Sdim return getEncodingValue(i); 35344779Sdim } 36344779Sdim 37276479Sdim bool isReservedReg(const MachineFunction &MF, unsigned Reg) const; 38344779Sdim bool isAnyArgRegReserved(const MachineFunction &MF) const; 39344779Sdim void emitReservedArgRegCallError(const MachineFunction &MF) const; 40249259Sdim 41344779Sdim void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const; 42344779Sdim void UpdateCustomCallPreservedMask(MachineFunction &MF, 43344779Sdim const uint32_t **Mask) const; 44344779Sdim 45276479Sdim /// Code Generation virtual methods... 46288943Sdim const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override; 47296417Sdim const MCPhysReg * 48314564Sdim getCalleeSavedRegsViaCopy(const MachineFunction *MF) const; 49288943Sdim const uint32_t *getCallPreservedMask(const MachineFunction &MF, 50288943Sdim CallingConv::ID) const override; 51249259Sdim 52276479Sdim unsigned getCSRFirstUseCost() const override { 53276479Sdim // The cost will be compared against BlockFrequency where entry has the 54276479Sdim // value of 1 << 14. A value of 5 will choose to spill or split really 55276479Sdim // cold path instead of using a callee-saved register. 56276479Sdim return 5; 57276479Sdim } 58249259Sdim 59341825Sdim const TargetRegisterClass * 60341825Sdim getSubClassWithSubReg(const TargetRegisterClass *RC, 61341825Sdim unsigned Idx) const override; 62341825Sdim 63276479Sdim // Calls involved in thread-local variable lookup save more registers than 64276479Sdim // normal calls, so they need a different mask to represent this. 65276479Sdim const uint32_t *getTLSCallPreservedMask() const; 66276479Sdim 67344779Sdim // Funclets on ARM64 Windows don't preserve any registers. 68344779Sdim const uint32_t *getNoPreservedMask() const override; 69344779Sdim 70276479Sdim /// getThisReturnPreservedMask - Returns a call preserved mask specific to the 71276479Sdim /// case that 'returned' is on an i64 first argument if the calling convention 72276479Sdim /// is one that can (partially) model this attribute with a preserved mask 73276479Sdim /// (i.e. it is a calling convention that uses the same register for the first 74276479Sdim /// i64 argument and an i64 return value) 75276479Sdim /// 76276479Sdim /// Should return NULL in the case that the calling convention does not have 77276479Sdim /// this property 78288943Sdim const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF, 79288943Sdim CallingConv::ID) const; 80276479Sdim 81341825Sdim /// Stack probing calls preserve different CSRs to the normal CC. 82341825Sdim const uint32_t *getWindowsStackProbePreservedMask() const; 83341825Sdim 84276479Sdim BitVector getReservedRegs(const MachineFunction &MF) const override; 85344779Sdim bool isAsmClobberable(const MachineFunction &MF, 86344779Sdim unsigned PhysReg) const override; 87314564Sdim bool isConstantPhysReg(unsigned PhysReg) const override; 88249259Sdim const TargetRegisterClass * 89276479Sdim getPointerRegClass(const MachineFunction &MF, 90276479Sdim unsigned Kind = 0) const override; 91276479Sdim const TargetRegisterClass * 92276479Sdim getCrossCopyRegClass(const TargetRegisterClass *RC) const override; 93249259Sdim 94276479Sdim bool requiresRegisterScavenging(const MachineFunction &MF) const override; 95276479Sdim bool useFPForScavengingIndex(const MachineFunction &MF) const override; 96276479Sdim bool requiresFrameIndexScavenging(const MachineFunction &MF) const override; 97249259Sdim 98276479Sdim bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override; 99288943Sdim bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, 100276479Sdim int64_t Offset) const override; 101276479Sdim void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, 102276479Sdim int FrameIdx, 103276479Sdim int64_t Offset) const override; 104276479Sdim void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 105276479Sdim int64_t Offset) const override; 106276479Sdim void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, 107276479Sdim unsigned FIOperandNum, 108276479Sdim RegScavenger *RS = nullptr) const override; 109276479Sdim bool cannotEliminateFrame(const MachineFunction &MF) const; 110249259Sdim 111276479Sdim bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override; 112276479Sdim bool hasBasePointer(const MachineFunction &MF) const; 113276479Sdim unsigned getBaseRegister() const; 114249259Sdim 115276479Sdim // Debug information queries. 116353358Sdim Register getFrameRegister(const MachineFunction &MF) const override; 117249259Sdim 118276479Sdim unsigned getRegPressureLimit(const TargetRegisterClass *RC, 119276479Sdim MachineFunction &MF) const override; 120314564Sdim 121314564Sdim bool trackLivenessAfterRegAlloc(const MachineFunction&) const override { 122314564Sdim return true; 123314564Sdim } 124353358Sdim 125353358Sdim unsigned getLocalAddressRegister(const MachineFunction &MF) const; 126249259Sdim}; 127249259Sdim 128249259Sdim} // end namespace llvm 129249259Sdim 130280031Sdim#endif 131