1326938Sdim//===- ARCRegisterInfo.cpp - ARC Register Information -----------*- C++ -*-===// 2326938Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6326938Sdim// 7326938Sdim//===----------------------------------------------------------------------===// 8326938Sdim// 9326938Sdim// This file contains the ARC implementation of the MRegisterInfo class. 10326938Sdim// 11326938Sdim//===----------------------------------------------------------------------===// 12326938Sdim 13326938Sdim#include "ARCRegisterInfo.h" 14326938Sdim#include "ARC.h" 15326938Sdim#include "ARCInstrInfo.h" 16326938Sdim#include "ARCMachineFunctionInfo.h" 17326938Sdim#include "ARCSubtarget.h" 18326938Sdim#include "llvm/ADT/BitVector.h" 19326938Sdim#include "llvm/CodeGen/MachineFrameInfo.h" 20326938Sdim#include "llvm/CodeGen/MachineFunction.h" 21326938Sdim#include "llvm/CodeGen/MachineInstrBuilder.h" 22326938Sdim#include "llvm/CodeGen/MachineModuleInfo.h" 23326938Sdim#include "llvm/CodeGen/MachineRegisterInfo.h" 24326938Sdim#include "llvm/CodeGen/RegisterScavenging.h" 25326938Sdim#include "llvm/IR/Function.h" 26326938Sdim#include "llvm/Support/Debug.h" 27326938Sdim#include "llvm/CodeGen/TargetFrameLowering.h" 28326938Sdim#include "llvm/Target/TargetMachine.h" 29326938Sdim#include "llvm/Target/TargetOptions.h" 30326938Sdim 31326938Sdimusing namespace llvm; 32326938Sdim 33326938Sdim#define DEBUG_TYPE "arc-reg-info" 34326938Sdim 35326938Sdim#define GET_REGINFO_TARGET_DESC 36326938Sdim#include "ARCGenRegisterInfo.inc" 37326938Sdim 38326938Sdimstatic void ReplaceFrameIndex(MachineBasicBlock::iterator II, 39326938Sdim const ARCInstrInfo &TII, unsigned Reg, 40326938Sdim unsigned FrameReg, int Offset, int StackSize, 41326938Sdim int ObjSize, RegScavenger *RS, int SPAdj) { 42326938Sdim assert(RS && "Need register scavenger."); 43326938Sdim MachineInstr &MI = *II; 44326938Sdim MachineBasicBlock &MBB = *MI.getParent(); 45326938Sdim DebugLoc dl = MI.getDebugLoc(); 46326938Sdim unsigned BaseReg = FrameReg; 47326938Sdim unsigned KillState = 0; 48326938Sdim if (MI.getOpcode() == ARC::LD_rs9 && (Offset >= 256 || Offset < -256)) { 49326938Sdim // Loads can always be reached with LD_rlimm. 50326938Sdim BuildMI(MBB, II, dl, TII.get(ARC::LD_rlimm), Reg) 51326938Sdim .addReg(BaseReg) 52326938Sdim .addImm(Offset) 53326938Sdim .addMemOperand(*MI.memoperands_begin()); 54326938Sdim MBB.erase(II); 55326938Sdim return; 56326938Sdim } 57326938Sdim 58326938Sdim if (MI.getOpcode() != ARC::GETFI && (Offset >= 256 || Offset < -256)) { 59326938Sdim // We need to use a scratch register to reach the far-away frame indexes. 60326938Sdim BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass); 61326938Sdim if (!BaseReg) { 62326938Sdim // We can be sure that the scavenged-register slot is within the range 63326938Sdim // of the load offset. 64326938Sdim const TargetRegisterInfo *TRI = 65326938Sdim MBB.getParent()->getSubtarget().getRegisterInfo(); 66326938Sdim BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj); 67326938Sdim assert(BaseReg && "Register scavenging failed."); 68341825Sdim LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI) 69341825Sdim << " for FrameReg=" << printReg(FrameReg, TRI) 70341825Sdim << "+Offset=" << Offset << "\n"); 71326938Sdim (void)TRI; 72326938Sdim RS->setRegUsed(BaseReg); 73326938Sdim } 74326938Sdim unsigned AddOpc = isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm; 75326938Sdim BuildMI(MBB, II, dl, TII.get(AddOpc)) 76326938Sdim .addReg(BaseReg, RegState::Define) 77326938Sdim .addReg(FrameReg) 78326938Sdim .addImm(Offset); 79326938Sdim Offset = 0; 80326938Sdim KillState = RegState::Kill; 81326938Sdim } 82326938Sdim switch (MI.getOpcode()) { 83326938Sdim case ARC::LD_rs9: 84326938Sdim assert((Offset % 4 == 0) && "LD needs 4 byte alignment."); 85353358Sdim LLVM_FALLTHROUGH; 86326938Sdim case ARC::LDH_rs9: 87326938Sdim case ARC::LDH_X_rs9: 88326938Sdim assert((Offset % 2 == 0) && "LDH needs 2 byte alignment."); 89353358Sdim LLVM_FALLTHROUGH; 90326938Sdim case ARC::LDB_rs9: 91326938Sdim case ARC::LDB_X_rs9: 92341825Sdim LLVM_DEBUG(dbgs() << "Building LDFI\n"); 93326938Sdim BuildMI(MBB, II, dl, TII.get(MI.getOpcode()), Reg) 94326938Sdim .addReg(BaseReg, KillState) 95326938Sdim .addImm(Offset) 96326938Sdim .addMemOperand(*MI.memoperands_begin()); 97326938Sdim break; 98326938Sdim case ARC::ST_rs9: 99326938Sdim assert((Offset % 4 == 0) && "ST needs 4 byte alignment."); 100353358Sdim LLVM_FALLTHROUGH; 101326938Sdim case ARC::STH_rs9: 102326938Sdim assert((Offset % 2 == 0) && "STH needs 2 byte alignment."); 103353358Sdim LLVM_FALLTHROUGH; 104326938Sdim case ARC::STB_rs9: 105341825Sdim LLVM_DEBUG(dbgs() << "Building STFI\n"); 106326938Sdim BuildMI(MBB, II, dl, TII.get(MI.getOpcode())) 107326938Sdim .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) 108326938Sdim .addReg(BaseReg, KillState) 109326938Sdim .addImm(Offset) 110326938Sdim .addMemOperand(*MI.memoperands_begin()); 111326938Sdim break; 112326938Sdim case ARC::GETFI: 113341825Sdim LLVM_DEBUG(dbgs() << "Building GETFI\n"); 114326938Sdim BuildMI(MBB, II, dl, 115326938Sdim TII.get(isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm)) 116326938Sdim .addReg(Reg, RegState::Define) 117326938Sdim .addReg(FrameReg) 118326938Sdim .addImm(Offset); 119326938Sdim break; 120326938Sdim default: 121326938Sdim llvm_unreachable("Unhandled opcode."); 122326938Sdim } 123326938Sdim 124326938Sdim // Erase old instruction. 125326938Sdim MBB.erase(II); 126326938Sdim} 127326938Sdim 128326938SdimARCRegisterInfo::ARCRegisterInfo() : ARCGenRegisterInfo(ARC::BLINK) {} 129326938Sdim 130326938Sdimbool ARCRegisterInfo::needsFrameMoves(const MachineFunction &MF) { 131360784Sdim return MF.needsFrameMoves(); 132326938Sdim} 133326938Sdim 134326938Sdimconst MCPhysReg * 135326938SdimARCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 136326938Sdim return CSR_ARC_SaveList; 137326938Sdim} 138326938Sdim 139326938SdimBitVector ARCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 140326938Sdim BitVector Reserved(getNumRegs()); 141326938Sdim 142326938Sdim Reserved.set(ARC::ILINK); 143326938Sdim Reserved.set(ARC::SP); 144326938Sdim Reserved.set(ARC::GP); 145326938Sdim Reserved.set(ARC::R25); 146326938Sdim Reserved.set(ARC::BLINK); 147326938Sdim Reserved.set(ARC::FP); 148326938Sdim return Reserved; 149326938Sdim} 150326938Sdim 151326938Sdimbool ARCRegisterInfo::requiresRegisterScavenging( 152326938Sdim const MachineFunction &MF) const { 153326938Sdim return true; 154326938Sdim} 155326938Sdim 156326938Sdimbool ARCRegisterInfo::trackLivenessAfterRegAlloc( 157326938Sdim const MachineFunction &MF) const { 158326938Sdim return true; 159326938Sdim} 160326938Sdim 161326938Sdimbool ARCRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const { 162326938Sdim return true; 163326938Sdim} 164326938Sdim 165326938Sdimvoid ARCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 166326938Sdim int SPAdj, unsigned FIOperandNum, 167326938Sdim RegScavenger *RS) const { 168326938Sdim assert(SPAdj == 0 && "Unexpected"); 169326938Sdim MachineInstr &MI = *II; 170326938Sdim MachineOperand &FrameOp = MI.getOperand(FIOperandNum); 171326938Sdim int FrameIndex = FrameOp.getIndex(); 172326938Sdim 173326938Sdim MachineFunction &MF = *MI.getParent()->getParent(); 174326938Sdim const ARCInstrInfo &TII = *MF.getSubtarget<ARCSubtarget>().getInstrInfo(); 175326938Sdim const ARCFrameLowering *TFI = getFrameLowering(MF); 176326938Sdim int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex); 177326938Sdim int ObjSize = MF.getFrameInfo().getObjectSize(FrameIndex); 178326938Sdim int StackSize = MF.getFrameInfo().getStackSize(); 179326938Sdim int LocalFrameSize = MF.getFrameInfo().getLocalFrameSize(); 180326938Sdim 181341825Sdim LLVM_DEBUG(dbgs() << "\nFunction : " << MF.getName() << "\n"); 182341825Sdim LLVM_DEBUG(dbgs() << "<--------->\n"); 183341825Sdim LLVM_DEBUG(dbgs() << MI << "\n"); 184341825Sdim LLVM_DEBUG(dbgs() << "FrameIndex : " << FrameIndex << "\n"); 185341825Sdim LLVM_DEBUG(dbgs() << "ObjSize : " << ObjSize << "\n"); 186341825Sdim LLVM_DEBUG(dbgs() << "FrameOffset : " << Offset << "\n"); 187341825Sdim LLVM_DEBUG(dbgs() << "StackSize : " << StackSize << "\n"); 188341825Sdim LLVM_DEBUG(dbgs() << "LocalFrameSize : " << LocalFrameSize << "\n"); 189326938Sdim (void)LocalFrameSize; 190326938Sdim 191326938Sdim // Special handling of DBG_VALUE instructions. 192326938Sdim if (MI.isDebugValue()) { 193353358Sdim Register FrameReg = getFrameRegister(MF); 194326938Sdim MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/); 195326938Sdim MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 196326938Sdim return; 197326938Sdim } 198326938Sdim 199326938Sdim // fold constant into offset. 200326938Sdim Offset += MI.getOperand(FIOperandNum + 1).getImm(); 201326938Sdim 202326938Sdim // TODO: assert based on the load type: 203326938Sdim // ldb needs no alignment, 204326938Sdim // ldh needs 2 byte alignment 205326938Sdim // ld needs 4 byte alignment 206341825Sdim LLVM_DEBUG(dbgs() << "Offset : " << Offset << "\n" 207341825Sdim << "<--------->\n"); 208326938Sdim 209360784Sdim Register Reg = MI.getOperand(0).getReg(); 210326938Sdim assert(ARC::GPR32RegClass.contains(Reg) && "Unexpected register operand"); 211326938Sdim 212326938Sdim if (!TFI->hasFP(MF)) { 213326938Sdim Offset = StackSize + Offset; 214326938Sdim if (FrameIndex >= 0) 215326938Sdim assert((Offset >= 0 && Offset < StackSize) && "SP Offset not in bounds."); 216326938Sdim } else { 217326938Sdim if (FrameIndex >= 0) { 218326938Sdim assert((Offset < 0 && -Offset <= StackSize) && 219326938Sdim "FP Offset not in bounds."); 220326938Sdim } 221326938Sdim } 222326938Sdim ReplaceFrameIndex(II, TII, Reg, getFrameRegister(MF), Offset, StackSize, 223326938Sdim ObjSize, RS, SPAdj); 224326938Sdim} 225326938Sdim 226353358SdimRegister ARCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 227326938Sdim const ARCFrameLowering *TFI = getFrameLowering(MF); 228326938Sdim return TFI->hasFP(MF) ? ARC::FP : ARC::SP; 229326938Sdim} 230326938Sdim 231326938Sdimconst uint32_t * 232326938SdimARCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, 233326938Sdim CallingConv::ID CC) const { 234326938Sdim return CSR_ARC_RegMask; 235326938Sdim} 236