Searched refs:BUILD_VECTOR (Results 1 - 25 of 32) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h375 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the
381 BUILD_VECTOR, enumerator in enum:llvm::ISD::NodeType
H A DSelectionDAG.h581 /// If VT is a vector type, the constant is splatted into a BUILD_VECTOR.
623 /// If VT is a vector type, the constant is splatted into a BUILD_VECTOR.
754 /// Return an ISD::BUILD_VECTOR node. The number of elements in VT,
759 // VerifySDNode (via InsertNode) checks BUILD_VECTOR later.
760 return getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
763 /// Return an ISD::BUILD_VECTOR node. The number of elements in VT,
768 // VerifySDNode (via InsertNode) checks BUILD_VECTOR later.
769 return getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
772 /// Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all
776 // VerifySDNode (via InsertNode) checks BUILD_VECTOR late
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H A DSelectionDAGNodes.h87 /// If N is a BUILD_VECTOR node whose elements are all the same constant or
91 /// Return true if the specified node is a BUILD_VECTOR where all of the
95 /// Return true if the specified node is a BUILD_VECTOR where all of the
99 /// Return true if the specified node is a BUILD_VECTOR node of all
103 /// Return true if the specified node is a BUILD_VECTOR node of all
1997 return N->getOpcode() == ISD::BUILD_VECTOR;
2664 /// every element of a constant BUILD_VECTOR.
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp94 setOperationAction(ISD::BUILD_VECTOR, T, Custom);
125 // Custom-lower BUILD_VECTOR for vector pairs. The standard (target-
128 setOperationAction(ISD::BUILD_VECTOR, T, Custom);
186 setOperationAction(ISD::BUILD_VECTOR, BoolV, Custom);
1263 // Do not use DAG.getNOT, because that would create BUILD_VECTOR with
1563 case ISD::BUILD_VECTOR: return LowerHvxBuildVector(Op, DAG);
H A DHexagonISelLowering.cpp1490 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR,
1537 setOperationAction(ISD::BUILD_VECTOR, NativeVT, Custom);
1987 // (into BUILD_VECTOR) should be adequate.
2908 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp106 assert(N->getOpcode() == ISD::BUILD_VECTOR && N->getNumOperands() == 2);
509 case ISD::BUILD_VECTOR:
789 case ISD::BUILD_VECTOR: {
793 if (Opc == ISD::BUILD_VECTOR && NumVectorElts == 2) {
2479 if (Src.getOpcode() == ISD::BUILD_VECTOR) {
2788 case ISD::BUILD_VECTOR: {
2792 // BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
2804 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
H A DR600ISelLowering.cpp1898 // If we can't generate a legal BUILD_VECTOR, exit
1899 if (!isOperationLegal(ISD::BUILD_VECTOR, VT))
1907 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
1908 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
1911 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
1923 // All the operands of BUILD_VECTOR must have the same type;
1941 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1948 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
2008 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
2026 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
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H A DAMDGPUISelLowering.cpp3070 isOperationLegal(ISD::BUILD_VECTOR, MVT::v2i16)) {
3207 if (Vec.getOpcode() == ISD::BUILD_VECTOR) {
3228 if (BV.getOpcode() == ISD::BUILD_VECTOR &&
3920 if (Src.getOpcode() == ISD::BUILD_VECTOR) {
3951 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
3962 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
H A DSIISelLowering.cpp268 case ISD::BUILD_VECTOR:
294 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
295 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32);
312 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f16, Custom);
313 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
530 case ISD::BUILD_VECTOR:
592 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i16, Custom);
593 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f16, Custom);
4072 case ISD::BUILD_VECTOR:
4760 = DAG.getNode(ISD::BUILD_VECTOR, S
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp134 setOperationAction(ISD::BUILD_VECTOR, T, Custom);
137 setOperationAction(ISD::BUILD_VECTOR, T, Custom);
1026 case ISD::BUILD_VECTOR:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp161 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
205 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
238 if (N->getOpcode() != ISD::BUILD_VECTOR)
251 if (N->getOpcode() != ISD::BUILD_VECTOR)
280 if (ISD::BUILD_VECTOR != Op.getOpcode())
311 if (ISD::BUILD_VECTOR != LHS.getOpcode() ||
312 ISD::BUILD_VECTOR != RHS.getOpcode())
824 case ISD::BUILD_VECTOR: {
1745 // BUILD_VECTOR may not match the type of the shuffle.
2293 case ISD::BUILD_VECTOR
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H A DSelectionDAGDumper.cpp155 case ISD::BUILD_VECTOR: return "BUILD_VECTOR";
H A DDAGCombiner.cpp866 if (N.getOpcode() != ISD::BUILD_VECTOR)
880 // Determines if a BUILD_VECTOR is composed of all-constants possibly mixed with
883 if (V.getOpcode() != ISD::BUILD_VECTOR)
1607 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
2953 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
8709 Cond.getOpcode() == ISD::BUILD_VECTOR);
10840 // Attempt to pre-truncate BUILD_VECTOR sources.
10841 if (N0.getOpcode() == ISD::BUILD_VECTOR && !LegalOperations &&
10859 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
11153 // If the input is a BUILD_VECTOR wit
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H A DTargetLowering.cpp870 case ISD::BUILD_VECTOR:
2279 case ISD::BUILD_VECTOR: {
5523 case ISD::BUILD_VECTOR: {
5524 // Only permit BUILD_VECTOR of constants.
5532 isOperationLegal(ISD::BUILD_VECTOR, VT))
5627 case ISD::BUILD_VECTOR: {
H A DLegalizeVectorTypes.cpp52 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
289 // The BUILD_VECTOR operands may be of wider element types and
680 /// The vectors to concatenate have length one - use a BUILD_VECTOR instead.
831 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
1359 // Create a new BUILD_VECTOR node
1780 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1823 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1859 // Construct the Lo/Hi output using a BUILD_VECTOR.
2689 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
3555 // Integer BUILD_VECTOR operand
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H A DLegalizeIntegerTypes.cpp101 case ISD::BUILD_VECTOR:
1269 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
3773 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
4266 // BUILD_VECTOR integer operand types are allowed to be larger than the
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h230 // Operands of the standard BUILD_VECTOR node are not legalized, which
234 // BUILD_VECTOR for this purpose.
235 BUILD_VECTOR,
H A DARMISelLowering.cpp182 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
261 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
324 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
325 setOperationAction(ISD::BUILD_VECTOR, VT.getVectorElementType(), Custom);
370 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
409 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
939 setTargetDAGCombine(ISD::BUILD_VECTOR);
1675 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
7245 // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp676 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
773 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
774 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
775 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
776 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
906 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
907 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1012 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
1060 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
1101 setOperationAction(ISD::BUILD_VECTOR, MV
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp510 // * N is a ISD::BUILD_VECTOR representing a constant splat
967 case ISD::BUILD_VECTOR: {
H A DMipsSEISelLowering.cpp330 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
384 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
466 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
528 // * N is a ISD::BUILD_VECTOR representing a constant splat
1393 // value as the lower - this results in the BUILD_VECTOR node not being
1436 // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
2190 // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
2447 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
2929 // BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp388 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f16, Custom);
2183 case ISD::BUILD_VECTOR:
2379 SDValue V2 = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f16, E0, E1);
4752 return DCI.DAG.getNode(ISD::BUILD_VECTOR, DL, CCType, CCNode.getValue(0),
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp845 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
941 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
948 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1344 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1380 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i1, Custom);
1429 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1616 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1747 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1806 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
5636 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp894 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
2775 if (N->getOpcode() != ISD::BUILD_VECTOR)
2804 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
3221 case ISD::BUILD_VECTOR:
6540 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
6568 // First gather all vectors used as an immediate source for this BUILD_VECTOR
6628 // the original, but with a total width matching the BUILD_VECTOR output.
6708 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
7234 // Test if V1 is a BUILD_VECTOR an
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp344 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
798 assert(BVN->isConstant() && "Expected a constant BUILD_VECTOR");
4622 // Return true if the given BUILD_VECTOR is a scalar-to-vector conversion.
4635 // BUILD_VECTOR lowering take care of it.
4681 // If a BUILD_VECTOR contains some EXTRACT_VECTOR_ELTs, it's usually
4682 // better to use VECTOR_SHUFFLEs on them, only using BUILD_VECTOR for
4683 // the non-EXTRACT_VECTOR_ELT elements. See if the given BUILD_VECTOR
4690 // Represent the BUILD_VECTOR as an N-operand VECTOR_SHUFFLE-like operation
4692 // need a BUILD_VECTOR, add an additional placeholder operand for that
4693 // BUILD_VECTOR an
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