Searched refs:BITREVERSE (Results 1 - 20 of 20) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1890 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll
1910 { ISD::BITREVERSE, MVT::v8i64, 5 },
1911 { ISD::BITREVERSE, MVT::v16i32, 5 },
1912 { ISD::BITREVERSE, MVT::v32i16, 5 },
1913 { ISD::BITREVERSE, MVT::v64i8, 5 },
1936 { ISD::BITREVERSE, MVT::v8i64, 36 },
1937 { ISD::BITREVERSE, MVT::v16i32, 24 },
1954 { ISD::BITREVERSE, MVT::v4i64, 4 },
1955 { ISD::BITREVERSE, MVT::v8i32, 4 },
1956 { ISD::BITREVERSE, MV
[all...]
H A DX86ISelLowering.cpp1056 setOperationAction(ISD::BITREVERSE, MVT::v16i8, Custom);
1137 // XOP can efficiently perform BITREVERSE with VPPERM.
1139 setOperationAction(ISD::BITREVERSE, VT, Custom);
1143 setOperationAction(ISD::BITREVERSE, VT, Custom);
1243 setOperationAction(ISD::BITREVERSE, MVT::v32i8, Custom);
1632 setOperationAction(ISD::BITREVERSE, MVT::v8i64, Custom);
1633 setOperationAction(ISD::BITREVERSE, MVT::v16i32, Custom);
1798 setOperationAction(ISD::BITREVERSE, MVT::v64i8, Custom);
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h474 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp394 case ISD::BITREVERSE:
890 case ISD::BITREVERSE:
1204 if (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, VT.getScalarType())) {
1211 // to BSWAP shuffle the bytes and then perform the BITREVERSE on the byte
1220 (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, ByteVT) ||
1229 Op = DAG.getNode(ISD::BITREVERSE, DL, ByteVT, Op);
H A DSelectionDAGDumper.cpp393 case ISD::BITREVERSE: return "bitreverse";
H A DLegalizeIntegerTypes.cpp59 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
398 // Helper for BSWAP/BITREVERSE promotion to ensure we can fit any shift amount
432 DAG.getNode(ISD::BITREVERSE, dl, NVT, Op),
1817 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
2584 Lo = DAG.getNode(ISD::BITREVERSE, dl, Lo.getValueType(), Lo);
2585 Hi = DAG.getNode(ISD::BITREVERSE, dl, Hi.getValueType(), Hi);
H A DLegalizeVectorTypes.cpp73 case ISD::BITREVERSE:
866 case ISD::BITREVERSE:
2837 case ISD::BITREVERSE:
H A DLegalizeDAG.cpp2599 /// Legalize a BITREVERSE scalar/vector operation as a series of mask + shifts.
2740 case ISD::BITREVERSE:
4266 case ISD::BITREVERSE:
H A DSelectionDAG.cpp3302 case ISD::BITREVERSE: {
4419 case ISD::BITREVERSE:
4539 case ISD::BITREVERSE:
4712 case ISD::BITREVERSE:
4714 "Invalid BITREVERSE!");
H A DDAGCombiner.cpp1555 case ISD::BITREVERSE: return visitBITREVERSE(N);
8234 return DAG.getNode(ISD::BITREVERSE, SDLoc(N), VT, N0);
8236 if (N0.getOpcode() == ISD::BITREVERSE)
H A DTargetLowering.cpp1578 case ISD::BITREVERSE: {
H A DSelectionDAGBuilder.cpp6311 setValue(&I, DAG.getNode(ISD::BITREVERSE, sdl,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp687 setOperationAction(ISD::BITREVERSE, VT, Expand);
H A DCodeGenPrepare.cpp7198 !TLI.isOperationLegalOrCustom(ISD::BITREVERSE,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1417 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1418 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp418 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
419 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp275 setOperationAction(ISD::BITREVERSE, VT, Legal);
1091 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
5998 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, VT, N->getOperand(0));
7828 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, MVT::i32, cast);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp220 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
221 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp365 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
467 setOperationAction(ISD::BITREVERSE, MVT::i16, Promote);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp157 // Match BITREVERSE to customized fast code sequence in the td file.
158 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
159 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);

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