Searched refs:BITCAST (Results 1 - 25 of 38) sorted by relevance

12

/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp57 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
58 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
68 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
69 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
76 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
77 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
82 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
83 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
86 assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST");
93 Lo = DAG.getNode(ISD::BITCAST, d
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H A DLegalizeVectorOps.cpp601 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(j));
614 Res = DAG.getNode(ISD::BITCAST, dl, VT, Res);
1040 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
1041 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
1050 return DAG.getNode(ISD::BITCAST, DL, Node->getValueType(0), Val);
1106 ISD::BITCAST, DL, VT,
1170 return DAG.getNode(ISD::BITCAST, DL, VT,
1194 SDValue Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Node->getOperand(0));
1196 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
1226 SDValue Op = DAG.getNode(ISD::BITCAST, D
[all...]
H A DLegalizeDAG.cpp530 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
703 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
1452 State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value);
1498 return DAG.getNode(ISD::BITCAST, DL, State.FloatVT, NewIntValue);
2896 case ISD::BITCAST:
3010 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3059 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3060 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3105 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
4297 TruncOp = ISD::BITCAST;
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H A DLegalizeVectorTypes.cpp51 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
282 return DAG.getNode(ISD::BITCAST, SDLoc(N),
564 case ISD::BITCAST:
641 return DAG.getNode(ISD::BITCAST, SDLoc(N),
830 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
1046 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
1047 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
1055 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
1056 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
1070 Lo = DAG.getNode(ISD::BITCAST, d
[all...]
H A DSelectionDAGBuilder.cpp239 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
240 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
273 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
274 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
305 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
335 Val = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Val);
448 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
461 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
467 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
540 Val = DAG.getNode(ISD::BITCAST, D
[all...]
H A DLegalizeTypes.cpp843 return DAG.getNode(ISD::BITCAST, SDLoc(Op),
853 return DAG.getNode(ISD::BITCAST, SDLoc(Op),
H A DLegalizeFloatTypes.cpp62 case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break;
775 case ISD::BITCAST: Res = SoftenFloatOp_BITCAST(N); break;
818 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), Op0);
1122 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1654 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
1970 case ISD::BITCAST: R = PromoteFloatOp_BITCAST(N, OpNo); break;
2099 case ISD::BITCAST: R = PromoteFloatRes_BITCAST(N); break;
H A DFastISel.cpp1549 // Bitcasts of other values become reg-reg copies or BITCAST operators.
1577 // If the reg-reg copy failed, select a BITCAST opcode.
1579 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
1749 ISD::BITCAST, OpReg, OpRegIsKill);
1759 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST,
H A DSelectionDAG.cpp158 while (N->getOpcode() == ISD::BITCAST)
202 while (N->getOpcode() == ISD::BITCAST)
1285 // to the endianness of the elements (because the BITCAST is itself a
1295 SDValue V = getNode(ISD::BITCAST, DL, VT, getBuildVector(ViaVecVT, DL, Ops));
1712 while (V.getOpcode() == ISD::BITCAST)
1747 NewBV = getNode(ISD::BITCAST, dl, VT, NewBV);
1900 return getNode(ISD::BITCAST, SDLoc(V), VT, V);
2686 case ISD::BITCAST: {
3584 case ISD::BITCAST: {
4406 case ISD::BITCAST
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H A DSelectionDAGDumper.cpp341 case ISD::BITCAST: return "bitcast";
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp486 setTargetDAGCombine(ISD::BITCAST);
569 case ISD::BITCAST:
1230 SDValue Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(0));
1231 SDValue Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(1));
1234 return DAG.getNode(ISD::BITCAST, SL, VT, BV);
1333 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1347 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1355 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1666 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV));
1667 Results.push_back(DAG.getNode(ISD::BITCAST, D
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H A DSIISelLowering.cpp269 case ISD::BITCAST:
531 case ISD::BITCAST:
1497 ArgVal = DAG.getNode(ISD::BITCAST, SL, MemVT, ArgVal);
2202 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
2330 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2409 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2800 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
4128 return DAG.getNode(ISD::BITCAST, DL, LoadVT, Result);
4132 return DAG.getNode(ISD::BITCAST, DL, LoadVT, Result);
4199 {DAG.getNode(ISD::BITCAST, D
[all...]
H A DAMDGPUISelLowering.h161 return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val;
H A DR600ISelLowering.cpp1035 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
1036 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
1055 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
1947 if (Arg.getOpcode() == ISD::BITCAST &&
1953 return DAG.getNode(ISD::BITCAST, DL, N->getVTList(),
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h612 /// BITCAST - This operator converts between integer, vector and FP
625 BITCAST, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp542 // This function looks through ISD::BITCAST nodes.
543 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
556 if (N->getOpcode() == ISD::BITCAST)
625 // This function looks through ISD::BITCAST nodes.
626 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
632 if (N->getOpcode() == ISD::BITCAST)
656 // This function looks through ISD::BITCAST nodes.
657 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
663 if (N->getOpcode() == ISD::BITCAST)
690 // This function looks through ISD::BITCAST node
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H A DMipsISelLowering.cpp2332 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2336 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2359 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2376 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2377 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2393 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2414 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2433 ? DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0))
2450 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
2468 SDValue X = DAG.getNode(ISD::BITCAST, D
[all...]
H A DMipsSEISelLowering.cpp99 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
219 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
325 setOperationAction(ISD::BITCAST, Ty, Legal);
381 setOperationAction(ISD::BITCAST, Ty, Legal);
469 case ISD::BITCAST: return lowerBITCAST(Op, DAG);
557 if (N->getOpcode() == ISD::BITCAST)
1412 Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy,
1459 Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
1485 ISD::BITCAST, DL, MVT::v2i64,
2510 Result = DAG.getNode(ISD::BITCAST, SDLo
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp339 setOperationAction(ISD::BITCAST, VT, Legal);
621 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
622 setOperationAction(ISD::BITCAST, MVT::f32, Custom);
1291 Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value);
1314 Value = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Value);
3293 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
3301 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
3712 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Op);
3718 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op);
4407 Op0 = DAG.getNode(ISD::BITCAST, D
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp406 setOperationAction(ISD::BITCAST, MVT::f32, Legal);
407 setOperationAction(ISD::BITCAST, MVT::i32, Legal);
408 setOperationAction(ISD::BITCAST, MVT::i64, Legal);
409 setOperationAction(ISD::BITCAST, MVT::f64, Legal);
421 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
422 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
423 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
424 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
958 setOperationAction(ISD::BITCAST, MVT::i128, Custom);
3048 return DAG.getNode(ISD::BITCAST, d
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp240 setOperationAction(ISD::BITCAST, VT, Legal);
720 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
721 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
722 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
1286 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
2031 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
2187 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2802 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
2806 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
2819 Arg = DAG.getNode(ISD::BITCAST, d
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp444 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue);
452 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
500 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), WholeValue);
815 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
858 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg);
907 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
1161 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
1520 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
1521 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
1558 setOperationAction(ISD::BITCAST, MV
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp597 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
598 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
2730 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
2937 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
2939 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
2955 SDValue Result = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64,
2958 return DAG.getNode(ISD::BITCAST, dl, MVT::i64, Result);
3092 Trunc = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Trunc);
3154 case ISD::BITCAST:
3440 ArgValue = DAG.getNode(ISD::BITCAST, D
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp182 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
418 case ISD::BITCAST: {
954 case ISD::BITCAST: {
1725 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
1780 Val = DAG.getNode(ISD::BITCAST, DL, LocVT, Val);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1629 case PtrToInt: return ISD::BITCAST;
1630 case IntToPtr: return ISD::BITCAST;
1631 case BitCast: return ISD::BITCAST;

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