Searched refs:SETCC (Results 1 - 25 of 33) sorted by relevance

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/freebsd-10.0-release/contrib/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp444 { ISD::SETCC, MVT::v2f64, 1 },
445 { ISD::SETCC, MVT::v4f32, 1 },
446 { ISD::SETCC, MVT::v2i64, 1 },
447 { ISD::SETCC, MVT::v4i32, 1 },
448 { ISD::SETCC, MVT::v8i16, 1 },
449 { ISD::SETCC, MVT::v16i8, 1 },
453 { ISD::SETCC, MVT::v4f64, 1 },
454 { ISD::SETCC, MVT::v8f32, 1 },
456 { ISD::SETCC, MVT::v4i64, 4 },
457 { ISD::SETCC, MV
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H A DX86ISelLowering.cpp480 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
481 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
482 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
483 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
484 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
485 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
488 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
811 setOperationAction(ISD::SETCC, VT, Expand);
921 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
922 setOperationAction(ISD::SETCC, MV
[all...]
H A DX86ISelLowering.h91 SETCC, enumerator in enum:llvm::X86ISD::NodeType
93 // Same as SETCC except it's materialized with a sbb and the value is all
97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
565 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
/freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h351 SETCC, enumerator in enum:llvm::ISD::NodeType
H A DSelectionDAG.h617 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h32 SETCC, enumerator in enum:llvm::HexagonISD::__anon2398
/freebsd-10.0-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h52 SETCC, enumerator in enum:llvm::MSP430ISD::__anon2425
H A DMSP430ISelLowering.cpp112 setOperationAction(ISD::SETCC, MVT::i8, Custom);
113 setOperationAction(ISD::SETCC, MVT::i16, Custom);
195 case ISD::SETCC: return LowerSETCC(Op, DAG);
/freebsd-10.0-release/contrib/llvm/lib/Target/R600/
H A DSIISelLowering.cpp80 setTargetDAGCombine(ISD::SETCC);
274 if (Intr->getOpcode() == ISD::SETCC) {
382 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
407 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
413 case ISD::SETCC: {
H A DR600ISelLowering.cpp62 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
80 setOperationAction(ISD::SETCC, MVT::i32, Expand);
81 setOperationAction(ISD::SETCC, MVT::f32, Expand);
483 ISD::SETCC,
/freebsd-10.0-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h73 /// This serves most of the functions of the LLVM SETCC instruction, for two
81 SETCC, enumerator in enum:llvm::AArch64ISD::NodeType
H A DAArch64ISelLowering.cpp101 setOperationAction(ISD::SETCC, MVT::i32, Custom);
102 setOperationAction(ISD::SETCC, MVT::i64, Custom);
103 setOperationAction(ISD::SETCC, MVT::f32, Custom);
104 setOperationAction(ISD::SETCC, MVT::f64, Custom);
219 setOperationAction(ISD::SETCC, MVT::f128, Custom);
780 case AArch64ISD::SETCC: return "AArch64ISD::SETCC";
1629 return DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
1707 SDValue A64CMP = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, TheBit,
1756 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, d
[all...]
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp221 case ISD::SETCC:
296 else if (Node->getOpcode() == ISD::SETCC)
756 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
H A DLegalizeVectorTypes.cpp64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
308 // Turn it into a scalar SETCC.
309 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
335 // Turn it into a scalar SETCC.
336 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
512 case ISD::SETCC:
1044 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1369 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1370 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1432 case ISD::SETCC
[all...]
H A DDAGCombiner.cpp547 if (N.getOpcode() == ISD::SETCC) {
1132 case ISD::SETCC: return visitSETCC(N);
2638 TLI.isOperationLegal(ISD::SETCC,
3150 TLI.isOperationLegal(ISD::SETCC,
3419 case ISD::SETCC:
4151 if (N0.getOpcode() == ISD::SETCC) {
4178 if (N0.getOpcode() == ISD::SETCC) {
4232 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
4269 // FIXME: Only extend SETCC N, N and SETCC
9580 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), local
[all...]
H A DTargetLowering.cpp101 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
190 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, getSetCCResultType(RetVT),
193 NewLHS = DAG.getNode(ISD::SETCC, dl, getSetCCResultType(RetVT), NewLHS,
1165 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1270 (isOperationLegal(ISD::SETCC, newVT) &&
1312 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1313 if (N0.getOpcode() == ISD::SETCC &&
1361 Op0.getOperand(0).getOpcode() == ISD::SETCC
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H A DSelectionDAGDumper.cpp187 case ISD::SETCC: return "setcc";
H A DLegalizeDAG.cpp1186 case ISD::SETCC:
1189 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1591 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1592 /// condition code CC on the current target. This routine expands SETCC with
1593 /// illegal condition code into AND / OR of multiple SETCC values.
3555 if (Tmp1.getOpcode() == ISD::SETCC) {
3602 if (Tmp2.getOpcode() == ISD::SETCC) {
3619 case ISD::SETCC: {
3625 // If we expanded the SETCC into an AND/OR, return the new node
3631 // Otherwise, SETCC fo
[all...]
H A DLegalizeFloatTypes.cpp616 case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break;
1258 case ISD::SETCC: Res = ExpandFloatOp_SETCC(N); break;
1279 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
H A DLegalizeIntegerTypes.cpp70 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
524 // Get the SETCC result using the canonical SETCC type.
785 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
818 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
2464 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2497 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2566 Tmp2 = DAG.getNode(ISD::SETCC, dl,
/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp59 setTargetDAGCombine(ISD::SETCC);
443 case ISD::SETCC: {
H A DMipsISelLowering.cpp233 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
247 setOperationAction(ISD::SETCC, MVT::f32, Custom);
248 setOperationAction(ISD::SETCC, MVT::f64, Custom);
495 // must be a SETCC node
496 if (Op.getOpcode() != ISD::SETCC)
533 if ((SetCC.getOpcode() != ISD::SETCC) ||
733 case ISD::SETCC: return lowerSETCC(Op, DAG);
1420 SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty),
/freebsd-10.0-release/contrib/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1286 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1287 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1288 setOperationAction(ISD::SETCC, MVT::f64, Expand);
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1231 case ICmp: return ISD::SETCC;
1232 case FCmp: return ISD::SETCC;
/freebsd-10.0-release/contrib/llvm/lib/Target/MBlaze/
H A DMBlazeISelLowering.cpp143 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);

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