126497Sache//===-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ----*- C++ -*-===// 226497Sache// 326497Sache// The LLVM Compiler Infrastructure 426497Sache// 526497Sache// This file is distributed under the University of Illinois Open Source 626497Sache// License. See LICENSE.TXT for details. 726497Sache// 8157184Sache//===----------------------------------------------------------------------===// 926497Sache// 10157184Sache// This file defines the interfaces that MSP430 uses to lower LLVM code into a 11157184Sache// selection DAG. 12157184Sache// 13157184Sache//===----------------------------------------------------------------------===// 14157184Sache 15157184Sache#ifndef LLVM_TARGET_MSP430_ISELLOWERING_H 16157184Sache#define LLVM_TARGET_MSP430_ISELLOWERING_H 17157184Sache 18157184Sache#include "MSP430.h" 19157184Sache#include "llvm/CodeGen/SelectionDAG.h" 20157184Sache#include "llvm/Target/TargetLowering.h" 21157184Sache 22157184Sachenamespace llvm { 23157184Sache namespace MSP430ISD { 24157184Sache enum { 25165670Sache FIRST_NUMBER = ISD::BUILTIN_OP_END, 26157184Sache 27165670Sache /// Return with a flag operand. Operand 0 is the chain operand. 28157184Sache RET_FLAG, 2926497Sache 30119610Sache /// Same as RET_FLAG, but used for returning from ISRs. 3126497Sache RETI_FLAG, 32119610Sache 3326497Sache /// Y = R{R,L}A X, rotate right (left) arithmetically 34119610Sache RRA, RLA, 3526497Sache 36119610Sache /// Y = RRC X, rotate right via carry 37165670Sache RRC, 38119610Sache 3926497Sache /// CALL - These operations represent an abstract call 4026497Sache /// instruction, which includes a bunch of information. 4135486Sache CALL, 4235486Sache 43157184Sache /// Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, 4435486Sache /// and TargetGlobalAddress. 4535486Sache Wrapper, 46119610Sache 47157184Sache /// CMP - Compare instruction. 4835486Sache CMP, 4935486Sache 5035486Sache /// SetCC - Operand 0 is condition code, and operand 1 is the flag 5135486Sache /// operand produced by a CMP instruction. 5235486Sache SETCC, 53157184Sache 54157184Sache /// MSP430 conditional branches. Operand 0 is the chain operand, operand 1 55157184Sache /// is the block to branch if condition is true, operand 2 is the 56157184Sache /// condition code, and operand 3 is the flag operand produced by a CMP 57157184Sache /// instruction. 58157184Sache BR_CC, 59119610Sache 60136644Sache /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 61119610Sache /// is condition code and operand 4 is flag operand. 62119610Sache SELECT_CC, 63119610Sache 64136644Sache /// SHL, SRA, SRL - Non-constant shifts. 65119610Sache SHL, SRA, SRL 66119610Sache }; 67119610Sache } 68136644Sache 69136644Sache class MSP430Subtarget; 70136644Sache class MSP430TargetMachine; 71136644Sache 72157184Sache class MSP430TargetLowering : public TargetLowering { 73157184Sache public: 74157184Sache explicit MSP430TargetLowering(MSP430TargetMachine &TM); 75157184Sache 76157184Sache virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i8; } 77157184Sache 78165670Sache /// LowerOperation - Provide custom lowering hooks for some operations. 79157184Sache virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 80157184Sache 81157184Sache /// getTargetNodeName - This method returns the name of a target specific 82157184Sache /// DAG node. 83157184Sache virtual const char *getTargetNodeName(unsigned Opcode) const; 84157184Sache 85157184Sache SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const; 86157184Sache SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 87157184Sache SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 88157184Sache SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const; 89157184Sache SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 90157184Sache SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 91157184Sache SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 92157184Sache SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const; 93157184Sache SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 94157184Sache SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 95157184Sache SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 96157184Sache SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; 97157184Sache 98157184Sache TargetLowering::ConstraintType 99157184Sache getConstraintType(const std::string &Constraint) const; 100157184Sache std::pair<unsigned, const TargetRegisterClass*> 101157184Sache getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const; 102119610Sache 103119610Sache /// isTruncateFree - Return true if it's free to truncate a value of type 104119610Sache /// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in 105119610Sache /// register R15W to i8 by referencing its sub-register R15B. 10626497Sache virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const; 10726497Sache virtual bool isTruncateFree(EVT VT1, EVT VT2) const; 10826497Sache 10975406Sache /// isZExtFree - Return true if any actual instruction that defines a value 11026497Sache /// of type Ty1 implicit zero-extends the value to Ty2 in the result 11158310Sache /// register. This does not necessarily include registers defined in unknown 11235486Sache /// ways, such as incoming arguments, or copies from unknown virtual 11326497Sache /// registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not 11426497Sache /// necessarily apply to truncate instructions. e.g. on msp430, all 11526497Sache /// instructions that define 8-bit values implicit zero-extend the result 11626497Sache /// out to 16 bits. 11726497Sache virtual bool isZExtFree(Type *Ty1, Type *Ty2) const; 11826497Sache virtual bool isZExtFree(EVT VT1, EVT VT2) const; 119119610Sache virtual bool isZExtFree(SDValue Val, EVT VT2) const; 12047558Sache 12147558Sache MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI, 12247558Sache MachineBasicBlock *BB) const; 12326497Sache MachineBasicBlock* EmitShiftInstr(MachineInstr *MI, 12426497Sache MachineBasicBlock *BB) const; 12547558Sache 12647558Sache private: 12747558Sache SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee, 128119610Sache CallingConv::ID CallConv, bool isVarArg, 129119610Sache bool isTailCall, 130119610Sache const SmallVectorImpl<ISD::OutputArg> &Outs, 13126497Sache const SmallVectorImpl<SDValue> &OutVals, 132119610Sache const SmallVectorImpl<ISD::InputArg> &Ins, 133119610Sache DebugLoc dl, SelectionDAG &DAG, 134119610Sache SmallVectorImpl<SDValue> &InVals) const; 135119610Sache 136119610Sache SDValue LowerCCCArguments(SDValue Chain, 137136644Sache CallingConv::ID CallConv, 138136644Sache bool isVarArg, 13926497Sache const SmallVectorImpl<ISD::InputArg> &Ins, 14026497Sache DebugLoc dl, 14126497Sache SelectionDAG &DAG, 142157184Sache SmallVectorImpl<SDValue> &InVals) const; 143157184Sache 144157184Sache SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 145157184Sache CallingConv::ID CallConv, bool isVarArg, 146157184Sache const SmallVectorImpl<ISD::InputArg> &Ins, 14726497Sache DebugLoc dl, SelectionDAG &DAG, 14826497Sache SmallVectorImpl<SDValue> &InVals) const; 14926497Sache 150157184Sache virtual SDValue 151157184Sache LowerFormalArguments(SDValue Chain, 152157184Sache CallingConv::ID CallConv, bool isVarArg, 15326497Sache const SmallVectorImpl<ISD::InputArg> &Ins, 154157184Sache DebugLoc dl, SelectionDAG &DAG, 155157184Sache SmallVectorImpl<SDValue> &InVals) const; 156157184Sache virtual SDValue 157157184Sache LowerCall(TargetLowering::CallLoweringInfo &CLI, 158157184Sache SmallVectorImpl<SDValue> &InVals) const; 159157184Sache 160157184Sache virtual SDValue 161119610Sache LowerReturn(SDValue Chain, 162119610Sache CallingConv::ID CallConv, bool isVarArg, 16326497Sache const SmallVectorImpl<ISD::OutputArg> &Outs, 16426497Sache const SmallVectorImpl<SDValue> &OutVals, 16526497Sache DebugLoc dl, SelectionDAG &DAG) const; 16626497Sache 167136644Sache virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 16826497Sache SDValue &Base, 169119610Sache SDValue &Offset, 170119610Sache ISD::MemIndexedMode &AM, 171119610Sache SelectionDAG &DAG) const; 172119610Sache 17326497Sache const MSP430Subtarget &Subtarget; 17426497Sache const DataLayout *TD; 17526497Sache }; 176119610Sache} // namespace llvm 17735486Sache 17826497Sache#endif // LLVM_TARGET_MSP430_ISELLOWERING_H 17926497Sache