1//===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Custom DAG lowering for SI
12//
13//===----------------------------------------------------------------------===//
14
15#include "SIISelLowering.h"
16#include "AMDIL.h"
17#include "AMDGPU.h"
18#include "AMDILIntrinsicInfo.h"
19#include "SIInstrInfo.h"
20#include "SIMachineFunctionInfo.h"
21#include "SIRegisterInfo.h"
22#include "llvm/IR/Function.h"
23#include "llvm/CodeGen/CallingConvLower.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/SelectionDAG.h"
27
28using namespace llvm;
29
30SITargetLowering::SITargetLowering(TargetMachine &TM) :
31    AMDGPUTargetLowering(TM),
32    TII(static_cast<const SIInstrInfo*>(TM.getInstrInfo())),
33    TRI(TM.getRegisterInfo()) {
34
35  addRegisterClass(MVT::i1, &AMDGPU::SReg_64RegClass);
36  addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
37
38  addRegisterClass(MVT::v16i8, &AMDGPU::SReg_128RegClass);
39  addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
40  addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
41
42  addRegisterClass(MVT::i32, &AMDGPU::VReg_32RegClass);
43  addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
44
45  addRegisterClass(MVT::v1i32, &AMDGPU::VReg_32RegClass);
46
47  addRegisterClass(MVT::v2i32, &AMDGPU::VReg_64RegClass);
48  addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
49
50  addRegisterClass(MVT::v4i32, &AMDGPU::VReg_128RegClass);
51  addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
52  addRegisterClass(MVT::i128, &AMDGPU::SReg_128RegClass);
53
54  addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
55  addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
56
57  addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass);
58  addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
59
60  computeRegisterProperties();
61
62  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
63  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
64  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
65  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
66
67  setOperationAction(ISD::ADD, MVT::i64, Legal);
68  setOperationAction(ISD::ADD, MVT::i32, Legal);
69
70  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
71  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
72
73  setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
74
75  setOperationAction(ISD::STORE, MVT::i32, Custom);
76  setOperationAction(ISD::STORE, MVT::i64, Custom);
77
78  setTargetDAGCombine(ISD::SELECT_CC);
79
80  setTargetDAGCombine(ISD::SETCC);
81
82  setSchedulingPreference(Sched::RegPressure);
83}
84
85SDValue SITargetLowering::LowerFormalArguments(
86                                      SDValue Chain,
87                                      CallingConv::ID CallConv,
88                                      bool isVarArg,
89                                      const SmallVectorImpl<ISD::InputArg> &Ins,
90                                      DebugLoc DL, SelectionDAG &DAG,
91                                      SmallVectorImpl<SDValue> &InVals) const {
92
93  const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
94
95  MachineFunction &MF = DAG.getMachineFunction();
96  FunctionType *FType = MF.getFunction()->getFunctionType();
97  SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
98
99  assert(CallConv == CallingConv::C);
100
101  SmallVector<ISD::InputArg, 16> Splits;
102  uint32_t Skipped = 0;
103
104  for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
105    const ISD::InputArg &Arg = Ins[i];
106
107    // First check if it's a PS input addr
108    if (Info->ShaderType == ShaderType::PIXEL && !Arg.Flags.isInReg()) {
109
110      assert((PSInputNum <= 15) && "Too many PS inputs!");
111
112      if (!Arg.Used) {
113        // We can savely skip PS inputs
114        Skipped |= 1 << i;
115        ++PSInputNum;
116        continue;
117      }
118
119      Info->PSInputAddr |= 1 << PSInputNum++;
120    }
121
122    // Second split vertices into their elements
123    if (Arg.VT.isVector()) {
124      ISD::InputArg NewArg = Arg;
125      NewArg.Flags.setSplit();
126      NewArg.VT = Arg.VT.getVectorElementType();
127
128      // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
129      // three or five element vertex only needs three or five registers,
130      // NOT four or eigth.
131      Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
132      unsigned NumElements = ParamType->getVectorNumElements();
133
134      for (unsigned j = 0; j != NumElements; ++j) {
135        Splits.push_back(NewArg);
136        NewArg.PartOffset += NewArg.VT.getStoreSize();
137      }
138
139    } else {
140      Splits.push_back(Arg);
141    }
142  }
143
144  SmallVector<CCValAssign, 16> ArgLocs;
145  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
146                 getTargetMachine(), ArgLocs, *DAG.getContext());
147
148  // At least one interpolation mode must be enabled or else the GPU will hang.
149  if (Info->ShaderType == ShaderType::PIXEL && (Info->PSInputAddr & 0x7F) == 0) {
150    Info->PSInputAddr |= 1;
151    CCInfo.AllocateReg(AMDGPU::VGPR0);
152    CCInfo.AllocateReg(AMDGPU::VGPR1);
153  }
154
155  AnalyzeFormalArguments(CCInfo, Splits);
156
157  for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
158
159    if (Skipped & (1 << i)) {
160      InVals.push_back(SDValue());
161      continue;
162    }
163
164    CCValAssign &VA = ArgLocs[ArgIdx++];
165    assert(VA.isRegLoc() && "Parameter must be in a register!");
166
167    unsigned Reg = VA.getLocReg();
168    MVT VT = VA.getLocVT();
169
170    if (VT == MVT::i64) {
171      // For now assume it is a pointer
172      Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
173                                     &AMDGPU::SReg_64RegClass);
174      Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
175      InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
176      continue;
177    }
178
179    const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
180
181    Reg = MF.addLiveIn(Reg, RC);
182    SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
183
184    const ISD::InputArg &Arg = Ins[i];
185    if (Arg.VT.isVector()) {
186
187      // Build a vector from the registers
188      Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
189      unsigned NumElements = ParamType->getVectorNumElements();
190
191      SmallVector<SDValue, 4> Regs;
192      Regs.push_back(Val);
193      for (unsigned j = 1; j != NumElements; ++j) {
194        Reg = ArgLocs[ArgIdx++].getLocReg();
195        Reg = MF.addLiveIn(Reg, RC);
196        Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
197      }
198
199      // Fill up the missing vector elements
200      NumElements = Arg.VT.getVectorNumElements() - NumElements;
201      for (unsigned j = 0; j != NumElements; ++j)
202        Regs.push_back(DAG.getUNDEF(VT));
203
204      InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT,
205                                   Regs.data(), Regs.size()));
206      continue;
207    }
208
209    InVals.push_back(Val);
210  }
211  return Chain;
212}
213
214MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
215    MachineInstr * MI, MachineBasicBlock * BB) const {
216
217  switch (MI->getOpcode()) {
218  default:
219    return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
220  case AMDGPU::BRANCH: return BB;
221  }
222  return BB;
223}
224
225EVT SITargetLowering::getSetCCResultType(EVT VT) const {
226  return MVT::i1;
227}
228
229MVT SITargetLowering::getScalarShiftAmountTy(EVT VT) const {
230  return MVT::i32;
231}
232
233//===----------------------------------------------------------------------===//
234// Custom DAG Lowering Operations
235//===----------------------------------------------------------------------===//
236
237SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
238  switch (Op.getOpcode()) {
239  default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
240  case ISD::BRCOND: return LowerBRCOND(Op, DAG);
241  case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
242  case ISD::STORE: return LowerSTORE(Op, DAG);
243  }
244  return SDValue();
245}
246
247/// \brief Helper function for LowerBRCOND
248static SDNode *findUser(SDValue Value, unsigned Opcode) {
249
250  SDNode *Parent = Value.getNode();
251  for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
252       I != E; ++I) {
253
254    if (I.getUse().get() != Value)
255      continue;
256
257    if (I->getOpcode() == Opcode)
258      return *I;
259  }
260  return 0;
261}
262
263/// This transforms the control flow intrinsics to get the branch destination as
264/// last parameter, also switches branch target with BR if the need arise
265SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
266                                      SelectionDAG &DAG) const {
267
268  DebugLoc DL = BRCOND.getDebugLoc();
269
270  SDNode *Intr = BRCOND.getOperand(1).getNode();
271  SDValue Target = BRCOND.getOperand(2);
272  SDNode *BR = 0;
273
274  if (Intr->getOpcode() == ISD::SETCC) {
275    // As long as we negate the condition everything is fine
276    SDNode *SetCC = Intr;
277    assert(SetCC->getConstantOperandVal(1) == 1);
278    assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
279           ISD::SETNE);
280    Intr = SetCC->getOperand(0).getNode();
281
282  } else {
283    // Get the target from BR if we don't negate the condition
284    BR = findUser(BRCOND, ISD::BR);
285    Target = BR->getOperand(1);
286  }
287
288  assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
289
290  // Build the result and
291  SmallVector<EVT, 4> Res;
292  for (unsigned i = 1, e = Intr->getNumValues(); i != e; ++i)
293    Res.push_back(Intr->getValueType(i));
294
295  // operands of the new intrinsic call
296  SmallVector<SDValue, 4> Ops;
297  Ops.push_back(BRCOND.getOperand(0));
298  for (unsigned i = 1, e = Intr->getNumOperands(); i != e; ++i)
299    Ops.push_back(Intr->getOperand(i));
300  Ops.push_back(Target);
301
302  // build the new intrinsic call
303  SDNode *Result = DAG.getNode(
304    Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
305    DAG.getVTList(Res.data(), Res.size()), Ops.data(), Ops.size()).getNode();
306
307  if (BR) {
308    // Give the branch instruction our target
309    SDValue Ops[] = {
310      BR->getOperand(0),
311      BRCOND.getOperand(2)
312    };
313    DAG.MorphNodeTo(BR, ISD::BR, BR->getVTList(), Ops, 2);
314  }
315
316  SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
317
318  // Copy the intrinsic results to registers
319  for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
320    SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
321    if (!CopyToReg)
322      continue;
323
324    Chain = DAG.getCopyToReg(
325      Chain, DL,
326      CopyToReg->getOperand(1),
327      SDValue(Result, i - 1),
328      SDValue());
329
330    DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
331  }
332
333  // Remove the old intrinsic from the chain
334  DAG.ReplaceAllUsesOfValueWith(
335    SDValue(Intr, Intr->getNumValues() - 1),
336    Intr->getOperand(0));
337
338  return Chain;
339}
340
341#define RSRC_DATA_FORMAT 0xf00000000000
342
343SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
344  StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
345  SDValue Chain = Op.getOperand(0);
346  SDValue Value = Op.getOperand(1);
347  SDValue VirtualAddress = Op.getOperand(2);
348  DebugLoc DL = Op.getDebugLoc();
349
350  if (StoreNode->getAddressSpace() != AMDGPUAS::GLOBAL_ADDRESS) {
351    return SDValue();
352  }
353
354  SDValue SrcSrc = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i128,
355                               DAG.getConstant(0, MVT::i64),
356			       DAG.getConstant(RSRC_DATA_FORMAT, MVT::i64));
357
358  SDValue Ops[2];
359  Ops[0] = DAG.getNode(AMDGPUISD::BUFFER_STORE, DL, MVT::Other, Chain,
360                       Value, SrcSrc, VirtualAddress);
361  Ops[1] = Chain;
362
363  return DAG.getMergeValues(Ops, 2, DL);
364
365}
366
367SDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
368  SDValue LHS = Op.getOperand(0);
369  SDValue RHS = Op.getOperand(1);
370  SDValue True = Op.getOperand(2);
371  SDValue False = Op.getOperand(3);
372  SDValue CC = Op.getOperand(4);
373  EVT VT = Op.getValueType();
374  DebugLoc DL = Op.getDebugLoc();
375
376  // Possible Min/Max pattern
377  SDValue MinMax = LowerMinMax(Op, DAG);
378  if (MinMax.getNode()) {
379    return MinMax;
380  }
381
382  SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
383  return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
384}
385
386//===----------------------------------------------------------------------===//
387// Custom DAG optimizations
388//===----------------------------------------------------------------------===//
389
390SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
391                                            DAGCombinerInfo &DCI) const {
392  SelectionDAG &DAG = DCI.DAG;
393  DebugLoc DL = N->getDebugLoc();
394  EVT VT = N->getValueType(0);
395
396  switch (N->getOpcode()) {
397    default: break;
398    case ISD::SELECT_CC: {
399      N->dump();
400      ConstantSDNode *True, *False;
401      // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
402      if ((True = dyn_cast<ConstantSDNode>(N->getOperand(2)))
403          && (False = dyn_cast<ConstantSDNode>(N->getOperand(3)))
404          && True->isAllOnesValue()
405          && False->isNullValue()
406          && VT == MVT::i1) {
407        return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
408                           N->getOperand(1), N->getOperand(4));
409
410      }
411      break;
412    }
413    case ISD::SETCC: {
414      SDValue Arg0 = N->getOperand(0);
415      SDValue Arg1 = N->getOperand(1);
416      SDValue CC = N->getOperand(2);
417      ConstantSDNode * C = NULL;
418      ISD::CondCode CCOp = dyn_cast<CondCodeSDNode>(CC)->get();
419
420      // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
421      if (VT == MVT::i1
422          && Arg0.getOpcode() == ISD::SIGN_EXTEND
423          && Arg0.getOperand(0).getValueType() == MVT::i1
424          && (C = dyn_cast<ConstantSDNode>(Arg1))
425          && C->isNullValue()
426          && CCOp == ISD::SETNE) {
427        return SimplifySetCC(VT, Arg0.getOperand(0),
428                             DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL);
429      }
430      break;
431    }
432  }
433  return SDValue();
434}
435
436/// \brief Test if RegClass is one of the VSrc classes
437static bool isVSrc(unsigned RegClass) {
438  return AMDGPU::VSrc_32RegClassID == RegClass ||
439         AMDGPU::VSrc_64RegClassID == RegClass;
440}
441
442/// \brief Test if RegClass is one of the SSrc classes
443static bool isSSrc(unsigned RegClass) {
444  return AMDGPU::SSrc_32RegClassID == RegClass ||
445         AMDGPU::SSrc_64RegClassID == RegClass;
446}
447
448/// \brief Analyze the possible immediate value Op
449///
450/// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
451/// and the immediate value if it's a literal immediate
452int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
453
454  union {
455    int32_t I;
456    float F;
457  } Imm;
458
459  if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
460    if (Node->getZExtValue() >> 32) {
461        return -1;
462    }
463    Imm.I = Node->getSExtValue();
464  } else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N))
465    Imm.F = Node->getValueAPF().convertToFloat();
466  else
467    return -1; // It isn't an immediate
468
469  if ((Imm.I >= -16 && Imm.I <= 64) ||
470      Imm.F == 0.5f || Imm.F == -0.5f ||
471      Imm.F == 1.0f || Imm.F == -1.0f ||
472      Imm.F == 2.0f || Imm.F == -2.0f ||
473      Imm.F == 4.0f || Imm.F == -4.0f)
474    return 0; // It's an inline immediate
475
476  return Imm.I; // It's a literal immediate
477}
478
479/// \brief Try to fold an immediate directly into an instruction
480bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
481                               bool &ScalarSlotUsed) const {
482
483  MachineSDNode *Mov = dyn_cast<MachineSDNode>(Operand);
484  if (Mov == 0 || !TII->isMov(Mov->getMachineOpcode()))
485    return false;
486
487  const SDValue &Op = Mov->getOperand(0);
488  int32_t Value = analyzeImmediate(Op.getNode());
489  if (Value == -1) {
490    // Not an immediate at all
491    return false;
492
493  } else if (Value == 0) {
494    // Inline immediates can always be fold
495    Operand = Op;
496    return true;
497
498  } else if (Value == Immediate) {
499    // Already fold literal immediate
500    Operand = Op;
501    return true;
502
503  } else if (!ScalarSlotUsed && !Immediate) {
504    // Fold this literal immediate
505    ScalarSlotUsed = true;
506    Immediate = Value;
507    Operand = Op;
508    return true;
509
510  }
511
512  return false;
513}
514
515/// \brief Does "Op" fit into register class "RegClass" ?
516bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, SDValue &Op,
517                                    unsigned RegClass) const {
518
519  MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
520  SDNode *Node = Op.getNode();
521
522  const TargetRegisterClass *OpClass;
523  if (MachineSDNode *MN = dyn_cast<MachineSDNode>(Node)) {
524    const MCInstrDesc &Desc = TII->get(MN->getMachineOpcode());
525    int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
526    if (OpClassID == -1)
527      OpClass = getRegClassFor(Op.getSimpleValueType());
528    else
529      OpClass = TRI->getRegClass(OpClassID);
530
531  } else if (Node->getOpcode() == ISD::CopyFromReg) {
532    RegisterSDNode *Reg = cast<RegisterSDNode>(Node->getOperand(1).getNode());
533    OpClass = MRI.getRegClass(Reg->getReg());
534
535  } else
536    return false;
537
538  return TRI->getRegClass(RegClass)->hasSubClassEq(OpClass);
539}
540
541/// \brief Make sure that we don't exeed the number of allowed scalars
542void SITargetLowering::ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
543                                       unsigned RegClass,
544                                       bool &ScalarSlotUsed) const {
545
546  // First map the operands register class to a destination class
547  if (RegClass == AMDGPU::VSrc_32RegClassID)
548    RegClass = AMDGPU::VReg_32RegClassID;
549  else if (RegClass == AMDGPU::VSrc_64RegClassID)
550    RegClass = AMDGPU::VReg_64RegClassID;
551  else
552    return;
553
554  // Nothing todo if they fit naturaly
555  if (fitsRegClass(DAG, Operand, RegClass))
556    return;
557
558  // If the scalar slot isn't used yet use it now
559  if (!ScalarSlotUsed) {
560    ScalarSlotUsed = true;
561    return;
562  }
563
564  // This is a conservative aproach, it is possible that we can't determine
565  // the correct register class and copy too often, but better save than sorry.
566  SDValue RC = DAG.getTargetConstant(RegClass, MVT::i32);
567  SDNode *Node = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, DebugLoc(),
568                                    Operand.getValueType(), Operand, RC);
569  Operand = SDValue(Node, 0);
570}
571
572/// \brief Try to fold the Nodes operands into the Node
573SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
574                                       SelectionDAG &DAG) const {
575
576  // Original encoding (either e32 or e64)
577  int Opcode = Node->getMachineOpcode();
578  const MCInstrDesc *Desc = &TII->get(Opcode);
579
580  unsigned NumDefs = Desc->getNumDefs();
581  unsigned NumOps = Desc->getNumOperands();
582
583  // Commuted opcode if available
584  int OpcodeRev = Desc->isCommutable() ? TII->commuteOpcode(Opcode) : -1;
585  const MCInstrDesc *DescRev = OpcodeRev == -1 ? 0 : &TII->get(OpcodeRev);
586
587  assert(!DescRev || DescRev->getNumDefs() == NumDefs);
588  assert(!DescRev || DescRev->getNumOperands() == NumOps);
589
590  // e64 version if available, -1 otherwise
591  int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
592  const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? 0 : &TII->get(OpcodeE64);
593
594  assert(!DescE64 || DescE64->getNumDefs() == NumDefs);
595  assert(!DescE64 || DescE64->getNumOperands() == (NumOps + 4));
596
597  int32_t Immediate = Desc->getSize() == 4 ? 0 : -1;
598  bool HaveVSrc = false, HaveSSrc = false;
599
600  // First figure out what we alread have in this instruction
601  for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
602       i != e && Op < NumOps; ++i, ++Op) {
603
604    unsigned RegClass = Desc->OpInfo[Op].RegClass;
605    if (isVSrc(RegClass))
606      HaveVSrc = true;
607    else if (isSSrc(RegClass))
608      HaveSSrc = true;
609    else
610      continue;
611
612    int32_t Imm = analyzeImmediate(Node->getOperand(i).getNode());
613    if (Imm != -1 && Imm != 0) {
614      // Literal immediate
615      Immediate = Imm;
616    }
617  }
618
619  // If we neither have VSrc nor SSrc it makes no sense to continue
620  if (!HaveVSrc && !HaveSSrc)
621    return Node;
622
623  // No scalar allowed when we have both VSrc and SSrc
624  bool ScalarSlotUsed = HaveVSrc && HaveSSrc;
625
626  // Second go over the operands and try to fold them
627  std::vector<SDValue> Ops;
628  bool Promote2e64 = false;
629  for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
630       i != e && Op < NumOps; ++i, ++Op) {
631
632    const SDValue &Operand = Node->getOperand(i);
633    Ops.push_back(Operand);
634
635    // Already folded immediate ?
636    if (isa<ConstantSDNode>(Operand.getNode()) ||
637        isa<ConstantFPSDNode>(Operand.getNode()))
638      continue;
639
640    // Is this a VSrc or SSrc operand ?
641    unsigned RegClass = Desc->OpInfo[Op].RegClass;
642    if (isVSrc(RegClass) || isSSrc(RegClass)) {
643      // Try to fold the immediates
644      if (!foldImm(Ops[i], Immediate, ScalarSlotUsed)) {
645        // Folding didn't worked, make sure we don't hit the SReg limit
646        ensureSRegLimit(DAG, Ops[i], RegClass, ScalarSlotUsed);
647      }
648      continue;
649    }
650
651    if (i == 1 && DescRev && fitsRegClass(DAG, Ops[0], RegClass)) {
652
653      unsigned OtherRegClass = Desc->OpInfo[NumDefs].RegClass;
654      assert(isVSrc(OtherRegClass) || isSSrc(OtherRegClass));
655
656      // Test if it makes sense to swap operands
657      if (foldImm(Ops[1], Immediate, ScalarSlotUsed) ||
658          (!fitsRegClass(DAG, Ops[1], RegClass) &&
659           fitsRegClass(DAG, Ops[1], OtherRegClass))) {
660
661        // Swap commutable operands
662        SDValue Tmp = Ops[1];
663        Ops[1] = Ops[0];
664        Ops[0] = Tmp;
665
666        Desc = DescRev;
667        DescRev = 0;
668        continue;
669      }
670    }
671
672    if (DescE64 && !Immediate) {
673
674      // Test if it makes sense to switch to e64 encoding
675      unsigned OtherRegClass = DescE64->OpInfo[Op].RegClass;
676      if (!isVSrc(OtherRegClass) && !isSSrc(OtherRegClass))
677        continue;
678
679      int32_t TmpImm = -1;
680      if (foldImm(Ops[i], TmpImm, ScalarSlotUsed) ||
681          (!fitsRegClass(DAG, Ops[i], RegClass) &&
682           fitsRegClass(DAG, Ops[1], OtherRegClass))) {
683
684        // Switch to e64 encoding
685        Immediate = -1;
686        Promote2e64 = true;
687        Desc = DescE64;
688        DescE64 = 0;
689      }
690    }
691  }
692
693  if (Promote2e64) {
694    // Add the modifier flags while promoting
695    for (unsigned i = 0; i < 4; ++i)
696      Ops.push_back(DAG.getTargetConstant(0, MVT::i32));
697  }
698
699  // Add optional chain and glue
700  for (unsigned i = NumOps - NumDefs, e = Node->getNumOperands(); i < e; ++i)
701    Ops.push_back(Node->getOperand(i));
702
703  // Create a complete new instruction
704  return DAG.getMachineNode(Desc->Opcode, Node->getDebugLoc(),
705                            Node->getVTList(), Ops);
706}
707
708/// \brief Helper function for adjustWritemask
709unsigned SubIdx2Lane(unsigned Idx) {
710  switch (Idx) {
711  default: return 0;
712  case AMDGPU::sub0: return 0;
713  case AMDGPU::sub1: return 1;
714  case AMDGPU::sub2: return 2;
715  case AMDGPU::sub3: return 3;
716  }
717}
718
719/// \brief Adjust the writemask of MIMG instructions
720void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
721                                       SelectionDAG &DAG) const {
722  SDNode *Users[4] = { };
723  unsigned Writemask = 0, Lane = 0;
724
725  // Try to figure out the used register components
726  for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
727       I != E; ++I) {
728
729    // Abort if we can't understand the usage
730    if (!I->isMachineOpcode() ||
731        I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
732      return;
733
734    Lane = SubIdx2Lane(I->getConstantOperandVal(1));
735
736    // Abort if we have more than one user per component
737    if (Users[Lane])
738      return;
739
740    Users[Lane] = *I;
741    Writemask |= 1 << Lane;
742  }
743
744  // Abort if all components are used
745  if (Writemask == 0xf)
746    return;
747
748  // Adjust the writemask in the node
749  std::vector<SDValue> Ops;
750  Ops.push_back(DAG.getTargetConstant(Writemask, MVT::i32));
751  for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
752    Ops.push_back(Node->getOperand(i));
753  Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size());
754
755  // If we only got one lane, replace it with a copy
756  if (Writemask == (1U << Lane)) {
757    SDValue RC = DAG.getTargetConstant(AMDGPU::VReg_32RegClassID, MVT::i32);
758    SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
759                                      DebugLoc(), Users[Lane]->getValueType(0),
760                                      SDValue(Node, 0), RC);
761    DAG.ReplaceAllUsesWith(Users[Lane], Copy);
762    return;
763  }
764
765  // Update the users of the node with the new indices
766  for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
767
768    SDNode *User = Users[i];
769    if (!User)
770      continue;
771
772    SDValue Op = DAG.getTargetConstant(Idx, MVT::i32);
773    DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
774
775    switch (Idx) {
776    default: break;
777    case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
778    case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
779    case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
780    }
781  }
782}
783
784/// \brief Fold the instructions after slecting them
785SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
786                                          SelectionDAG &DAG) const {
787
788  if (AMDGPU::isMIMG(Node->getMachineOpcode()) != -1)
789    adjustWritemask(Node, DAG);
790
791  return foldOperands(Node, DAG);
792}
793
794/// \brief Assign the register class depending on the number of
795/// bits set in the writemask
796void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
797                                                     SDNode *Node) const {
798  if (AMDGPU::isMIMG(MI->getOpcode()) == -1)
799    return;
800
801  unsigned VReg = MI->getOperand(0).getReg();
802  unsigned Writemask = MI->getOperand(1).getImm();
803  unsigned BitsSet = 0;
804  for (unsigned i = 0; i < 4; ++i)
805    BitsSet += Writemask & (1 << i) ? 1 : 0;
806
807  const TargetRegisterClass *RC;
808  switch (BitsSet) {
809  default: return;
810  case 1:  RC = &AMDGPU::VReg_32RegClass; break;
811  case 2:  RC = &AMDGPU::VReg_64RegClass; break;
812  case 3:  RC = &AMDGPU::VReg_96RegClass; break;
813  }
814
815  MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
816  MRI.setRegClass(VReg, RC);
817}
818