Searched refs:REG_SET (Results 1 - 10 of 10) sorted by relevance

/freebsd-10-stable/sys/dev/drm2/radeon/
H A Dr300d.h64 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
65 REG_SET(PACKET0_COUNT, (n)))
66 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
68 REG_SET(PACKET3_IT_OPCODE, (op)) | \
69 REG_SET(PACKET3_COUNT, (n)))
H A Drv515d.h204 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
205 REG_SET(PACKET0_COUNT, (n)))
206 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
208 REG_SET(PACKET3_IT_OPCODE, (op)) | \
209 REG_SET(PACKET3_COUNT, (n)))
H A Drs400.c152 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
153 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
H A Dr100d.h63 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
64 REG_SET(PACKET0_COUNT, (n)))
65 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
67 REG_SET(PACKET3_IT_OPCODE, (op)) | \
68 REG_SET(PACKET3_COUNT, (n)))
H A Dnid.h500 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
H A Dr100.c1155 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1156 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1157 REG_SET(RADEON_MAX_FETCH, max_fetch));
1189 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1190 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
H A Dsid.h807 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
H A Dradeon.h1694 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) macro
H A Devergreend.h1003 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
H A Dr600d.h37 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

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