1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2008 Advanced Micro Devices, Inc. 3254885Sdumbbell * Copyright 2008 Red Hat Inc. 4254885Sdumbbell * Copyright 2009 Jerome Glisse. 5254885Sdumbbell * 6254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 7254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 8254885Sdumbbell * to deal in the Software without restriction, including without limitation 9254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 11254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 12254885Sdumbbell * 13254885Sdumbbell * The above copyright notice and this permission notice shall be included in 14254885Sdumbbell * all copies or substantial portions of the Software. 15254885Sdumbbell * 16254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19254885Sdumbbell * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22254885Sdumbbell * OTHER DEALINGS IN THE SOFTWARE. 23254885Sdumbbell * 24254885Sdumbbell * Authors: Dave Airlie 25254885Sdumbbell * Alex Deucher 26254885Sdumbbell * Jerome Glisse 27254885Sdumbbell */ 28254885Sdumbbell 29254885Sdumbbell#include <sys/cdefs.h> 30254885Sdumbbell__FBSDID("$FreeBSD$"); 31254885Sdumbbell 32254885Sdumbbell#ifndef __RADEON_H__ 33254885Sdumbbell#define __RADEON_H__ 34254885Sdumbbell 35254885Sdumbbell/* TODO: Here are things that needs to be done : 36254885Sdumbbell * - surface allocator & initializer : (bit like scratch reg) should 37254885Sdumbbell * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 38254885Sdumbbell * related to surface 39254885Sdumbbell * - WB : write back stuff (do it bit like scratch reg things) 40254885Sdumbbell * - Vblank : look at Jesse's rework and what we should do 41254885Sdumbbell * - r600/r700: gart & cp 42254885Sdumbbell * - cs : clean cs ioctl use bitmap & things like that. 43254885Sdumbbell * - power management stuff 44254885Sdumbbell * - Barrier in gart code 45254885Sdumbbell * - Unmappabled vram ? 46254885Sdumbbell * - TESTING, TESTING, TESTING 47254885Sdumbbell */ 48254885Sdumbbell 49254885Sdumbbell/* Initialization path: 50254885Sdumbbell * We expect that acceleration initialization might fail for various 51254885Sdumbbell * reasons even thought we work hard to make it works on most 52254885Sdumbbell * configurations. In order to still have a working userspace in such 53254885Sdumbbell * situation the init path must succeed up to the memory controller 54254885Sdumbbell * initialization point. Failure before this point are considered as 55254885Sdumbbell * fatal error. Here is the init callchain : 56254885Sdumbbell * radeon_device_init perform common structure, mutex initialization 57254885Sdumbbell * asic_init setup the GPU memory layout and perform all 58254885Sdumbbell * one time initialization (failure in this 59254885Sdumbbell * function are considered fatal) 60254885Sdumbbell * asic_startup setup the GPU acceleration, in order to 61254885Sdumbbell * follow guideline the first thing this 62254885Sdumbbell * function should do is setting the GPU 63254885Sdumbbell * memory controller (only MC setup failure 64254885Sdumbbell * are considered as fatal) 65254885Sdumbbell */ 66254885Sdumbbell 67254885Sdumbbell#include <sys/cdefs.h> 68254885Sdumbbell__FBSDID("$FreeBSD$"); 69254885Sdumbbell 70254885Sdumbbell#include <sys/param.h> 71254885Sdumbbell#include <sys/systm.h> 72254885Sdumbbell#include <sys/linker.h> 73254885Sdumbbell#include <sys/firmware.h> 74254885Sdumbbell 75282199Sdumbbell#if defined(CONFIG_ACPI) 76254885Sdumbbell#include <contrib/dev/acpica/include/acpi.h> 77254885Sdumbbell#include <dev/acpica/acpivar.h> 78282199Sdumbbell#endif 79254885Sdumbbell 80254885Sdumbbell#include <dev/drm2/ttm/ttm_bo_api.h> 81254885Sdumbbell#include <dev/drm2/ttm/ttm_bo_driver.h> 82254885Sdumbbell#include <dev/drm2/ttm/ttm_placement.h> 83254885Sdumbbell#include <dev/drm2/ttm/ttm_module.h> 84254885Sdumbbell#include <dev/drm2/ttm/ttm_execbuf_util.h> 85254885Sdumbbell 86254885Sdumbbell#include "radeon_family.h" 87254885Sdumbbell#include "radeon_mode.h" 88254885Sdumbbell#include "radeon_reg.h" 89254885Sdumbbell 90254885Sdumbbell/* 91254885Sdumbbell * Modules parameters. 92254885Sdumbbell */ 93254885Sdumbbellextern int radeon_no_wb; 94254885Sdumbbellextern int radeon_modeset; 95254885Sdumbbellextern int radeon_dynclks; 96254885Sdumbbellextern int radeon_r4xx_atom; 97254885Sdumbbellextern int radeon_agpmode; 98254885Sdumbbellextern int radeon_vram_limit; 99254885Sdumbbellextern int radeon_gart_size; 100254885Sdumbbellextern int radeon_benchmarking; 101254885Sdumbbellextern int radeon_testing; 102254885Sdumbbellextern int radeon_connector_table; 103254885Sdumbbellextern int radeon_tv; 104254885Sdumbbellextern int radeon_audio; 105254885Sdumbbellextern int radeon_disp_priority; 106254885Sdumbbellextern int radeon_hw_i2c; 107254885Sdumbbellextern int radeon_pcie_gen2; 108254885Sdumbbellextern int radeon_msi; 109254885Sdumbbellextern int radeon_lockup_timeout; 110254885Sdumbbell 111254885Sdumbbell/* 112254885Sdumbbell * Copy from radeon_drv.h so we don't have to include both and have conflicting 113254885Sdumbbell * symbol; 114254885Sdumbbell */ 115254885Sdumbbell#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 116282199Sdumbbell#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 117254885Sdumbbell/* RADEON_IB_POOL_SIZE must be a power of 2 */ 118254885Sdumbbell#define RADEON_IB_POOL_SIZE 16 119254885Sdumbbell#define RADEON_DEBUGFS_MAX_COMPONENTS 32 120254885Sdumbbell#define RADEONFB_CONN_LIMIT 4 121254885Sdumbbell#define RADEON_BIOS_NUM_SCRATCH 8 122254885Sdumbbell 123254885Sdumbbell/* max number of rings */ 124254885Sdumbbell#define RADEON_NUM_RINGS 5 125254885Sdumbbell 126254885Sdumbbell/* fence seq are set to this number when signaled */ 127254885Sdumbbell#define RADEON_FENCE_SIGNALED_SEQ 0LL 128254885Sdumbbell 129254885Sdumbbell/* internal ring indices */ 130254885Sdumbbell/* r1xx+ has gfx CP ring */ 131254885Sdumbbell#define RADEON_RING_TYPE_GFX_INDEX 0 132254885Sdumbbell 133254885Sdumbbell/* cayman has 2 compute CP rings */ 134254885Sdumbbell#define CAYMAN_RING_TYPE_CP1_INDEX 1 135254885Sdumbbell#define CAYMAN_RING_TYPE_CP2_INDEX 2 136254885Sdumbbell 137254885Sdumbbell/* R600+ has an async dma ring */ 138254885Sdumbbell#define R600_RING_TYPE_DMA_INDEX 3 139254885Sdumbbell/* cayman add a second async dma ring */ 140254885Sdumbbell#define CAYMAN_RING_TYPE_DMA1_INDEX 4 141254885Sdumbbell 142254885Sdumbbell/* hardcode those limit for now */ 143254885Sdumbbell#define RADEON_VA_IB_OFFSET (1 << 20) 144254885Sdumbbell#define RADEON_VA_RESERVED_SIZE (8 << 20) 145254885Sdumbbell#define RADEON_IB_VM_MAX_SIZE (64 << 10) 146254885Sdumbbell 147254885Sdumbbell/* reset flags */ 148254885Sdumbbell#define RADEON_RESET_GFX (1 << 0) 149254885Sdumbbell#define RADEON_RESET_COMPUTE (1 << 1) 150254885Sdumbbell#define RADEON_RESET_DMA (1 << 2) 151254885Sdumbbell 152254885Sdumbbell/* 153254885Sdumbbell * Errata workarounds. 154254885Sdumbbell */ 155254885Sdumbbellenum radeon_pll_errata { 156254885Sdumbbell CHIP_ERRATA_R300_CG = 0x00000001, 157254885Sdumbbell CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 158254885Sdumbbell CHIP_ERRATA_PLL_DELAY = 0x00000004 159254885Sdumbbell}; 160254885Sdumbbell 161254885Sdumbbell 162254885Sdumbbellstruct radeon_device; 163254885Sdumbbell 164254885Sdumbbell 165254885Sdumbbell/* 166254885Sdumbbell * BIOS. 167254885Sdumbbell */ 168254885Sdumbbellbool radeon_get_bios(struct radeon_device *rdev); 169254885Sdumbbell 170254885Sdumbbell/* 171254885Sdumbbell * Dummy page 172254885Sdumbbell */ 173254885Sdumbbellstruct radeon_dummy_page { 174254885Sdumbbell drm_dma_handle_t *dmah; 175254885Sdumbbell dma_addr_t addr; 176254885Sdumbbell}; 177254885Sdumbbellint radeon_dummy_page_init(struct radeon_device *rdev); 178254885Sdumbbellvoid radeon_dummy_page_fini(struct radeon_device *rdev); 179254885Sdumbbell 180254885Sdumbbell 181254885Sdumbbell/* 182254885Sdumbbell * Clocks 183254885Sdumbbell */ 184254885Sdumbbellstruct radeon_clock { 185254885Sdumbbell struct radeon_pll p1pll; 186254885Sdumbbell struct radeon_pll p2pll; 187254885Sdumbbell struct radeon_pll dcpll; 188254885Sdumbbell struct radeon_pll spll; 189254885Sdumbbell struct radeon_pll mpll; 190254885Sdumbbell /* 10 Khz units */ 191254885Sdumbbell uint32_t default_mclk; 192254885Sdumbbell uint32_t default_sclk; 193254885Sdumbbell uint32_t default_dispclk; 194254885Sdumbbell uint32_t dp_extclk; 195254885Sdumbbell uint32_t max_pixel_clock; 196254885Sdumbbell}; 197254885Sdumbbell 198254885Sdumbbell/* 199254885Sdumbbell * Power management 200254885Sdumbbell */ 201254885Sdumbbellint radeon_pm_init(struct radeon_device *rdev); 202254885Sdumbbellvoid radeon_pm_fini(struct radeon_device *rdev); 203254885Sdumbbellvoid radeon_pm_compute_clocks(struct radeon_device *rdev); 204254885Sdumbbellvoid radeon_pm_suspend(struct radeon_device *rdev); 205254885Sdumbbellvoid radeon_pm_resume(struct radeon_device *rdev); 206254885Sdumbbellvoid radeon_combios_get_power_modes(struct radeon_device *rdev); 207254885Sdumbbellvoid radeon_atombios_get_power_modes(struct radeon_device *rdev); 208254885Sdumbbellvoid radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 209254885Sdumbbellvoid rs690_pm_info(struct radeon_device *rdev); 210254885Sdumbbellextern int rv6xx_get_temp(struct radeon_device *rdev); 211254885Sdumbbellextern int rv770_get_temp(struct radeon_device *rdev); 212254885Sdumbbellextern int evergreen_get_temp(struct radeon_device *rdev); 213254885Sdumbbellextern int sumo_get_temp(struct radeon_device *rdev); 214254885Sdumbbellextern int si_get_temp(struct radeon_device *rdev); 215254885Sdumbbellextern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 216254885Sdumbbell unsigned *bankh, unsigned *mtaspect, 217254885Sdumbbell unsigned *tile_split); 218254885Sdumbbell 219254885Sdumbbell/* 220254885Sdumbbell * Fences. 221254885Sdumbbell */ 222254885Sdumbbellstruct radeon_fence_driver { 223254885Sdumbbell uint32_t scratch_reg; 224254885Sdumbbell uint64_t gpu_addr; 225254885Sdumbbell volatile uint32_t *cpu_addr; 226254885Sdumbbell /* sync_seq is protected by ring emission lock */ 227254885Sdumbbell uint64_t sync_seq[RADEON_NUM_RINGS]; 228254885Sdumbbell atomic64_t last_seq; 229254885Sdumbbell unsigned long last_activity; 230254885Sdumbbell bool initialized; 231254885Sdumbbell}; 232254885Sdumbbell 233254885Sdumbbellstruct radeon_fence { 234254885Sdumbbell struct radeon_device *rdev; 235254885Sdumbbell unsigned int kref; 236254885Sdumbbell /* protected by radeon_fence.lock */ 237254885Sdumbbell uint64_t seq; 238254885Sdumbbell /* RB, DMA, etc. */ 239254885Sdumbbell unsigned ring; 240254885Sdumbbell}; 241254885Sdumbbell 242254885Sdumbbellint radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 243254885Sdumbbellint radeon_fence_driver_init(struct radeon_device *rdev); 244254885Sdumbbellvoid radeon_fence_driver_fini(struct radeon_device *rdev); 245254885Sdumbbellvoid radeon_fence_driver_force_completion(struct radeon_device *rdev); 246254885Sdumbbellint radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 247254885Sdumbbellvoid radeon_fence_process(struct radeon_device *rdev, int ring); 248254885Sdumbbellbool radeon_fence_signaled(struct radeon_fence *fence); 249254885Sdumbbellint radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 250254885Sdumbbellint radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); 251254885Sdumbbellint radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); 252254885Sdumbbellint radeon_fence_wait_any(struct radeon_device *rdev, 253254885Sdumbbell struct radeon_fence **fences, 254254885Sdumbbell bool intr); 255254885Sdumbbellstruct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 256254885Sdumbbellvoid radeon_fence_unref(struct radeon_fence **fence); 257254885Sdumbbellunsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 258254885Sdumbbellbool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 259254885Sdumbbellvoid radeon_fence_note_sync(struct radeon_fence *fence, int ring); 260254885Sdumbbellstatic inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 261254885Sdumbbell struct radeon_fence *b) 262254885Sdumbbell{ 263254885Sdumbbell if (!a) { 264254885Sdumbbell return b; 265254885Sdumbbell } 266254885Sdumbbell 267254885Sdumbbell if (!b) { 268254885Sdumbbell return a; 269254885Sdumbbell } 270254885Sdumbbell 271254885Sdumbbell KASSERT(a->ring == b->ring, ("\"a\" and \"b\" belongs to different rings")); 272254885Sdumbbell 273254885Sdumbbell if (a->seq > b->seq) { 274254885Sdumbbell return a; 275254885Sdumbbell } else { 276254885Sdumbbell return b; 277254885Sdumbbell } 278254885Sdumbbell} 279254885Sdumbbell 280254885Sdumbbellstatic inline bool radeon_fence_is_earlier(struct radeon_fence *a, 281254885Sdumbbell struct radeon_fence *b) 282254885Sdumbbell{ 283254885Sdumbbell if (!a) { 284254885Sdumbbell return false; 285254885Sdumbbell } 286254885Sdumbbell 287254885Sdumbbell if (!b) { 288254885Sdumbbell return true; 289254885Sdumbbell } 290254885Sdumbbell 291254885Sdumbbell KASSERT(a->ring == b->ring, ("\"a\" and \"b\" belongs to different rings")); 292254885Sdumbbell 293254885Sdumbbell return a->seq < b->seq; 294254885Sdumbbell} 295254885Sdumbbell 296254885Sdumbbell/* 297254885Sdumbbell * Tiling registers 298254885Sdumbbell */ 299254885Sdumbbellstruct radeon_surface_reg { 300254885Sdumbbell struct radeon_bo *bo; 301254885Sdumbbell}; 302254885Sdumbbell 303254885Sdumbbell#define RADEON_GEM_MAX_SURFACES 8 304254885Sdumbbell 305254885Sdumbbell/* 306254885Sdumbbell * TTM. 307254885Sdumbbell */ 308254885Sdumbbellstruct radeon_mman { 309254885Sdumbbell struct ttm_bo_global_ref bo_global_ref; 310254885Sdumbbell struct drm_global_reference mem_global_ref; 311254885Sdumbbell struct ttm_bo_device bdev; 312254885Sdumbbell bool mem_global_referenced; 313254885Sdumbbell bool initialized; 314254885Sdumbbell}; 315254885Sdumbbell 316254885Sdumbbell/* bo virtual address in a specific vm */ 317254885Sdumbbellstruct radeon_bo_va { 318254885Sdumbbell /* protected by bo being reserved */ 319254885Sdumbbell struct list_head bo_list; 320254885Sdumbbell uint64_t soffset; 321254885Sdumbbell uint64_t eoffset; 322254885Sdumbbell uint32_t flags; 323254885Sdumbbell bool valid; 324254885Sdumbbell unsigned ref_count; 325254885Sdumbbell 326254885Sdumbbell /* protected by vm mutex */ 327254885Sdumbbell struct list_head vm_list; 328254885Sdumbbell 329254885Sdumbbell /* constant after initialization */ 330254885Sdumbbell struct radeon_vm *vm; 331254885Sdumbbell struct radeon_bo *bo; 332254885Sdumbbell}; 333254885Sdumbbell 334254885Sdumbbellstruct radeon_bo { 335254885Sdumbbell /* Protected by gem.mutex */ 336254885Sdumbbell struct list_head list; 337254885Sdumbbell /* Protected by tbo.reserved */ 338254885Sdumbbell u32 placements[3]; 339254885Sdumbbell struct ttm_placement placement; 340254885Sdumbbell struct ttm_buffer_object tbo; 341254885Sdumbbell struct ttm_bo_kmap_obj kmap; 342254885Sdumbbell unsigned pin_count; 343254885Sdumbbell void *kptr; 344254885Sdumbbell u32 tiling_flags; 345254885Sdumbbell u32 pitch; 346254885Sdumbbell int surface_reg; 347254885Sdumbbell /* list of all virtual address to which this bo 348254885Sdumbbell * is associated to 349254885Sdumbbell */ 350254885Sdumbbell struct list_head va; 351254885Sdumbbell /* Constant after initialization */ 352254885Sdumbbell struct radeon_device *rdev; 353254885Sdumbbell struct drm_gem_object gem_base; 354254885Sdumbbell 355254885Sdumbbell struct ttm_bo_kmap_obj dma_buf_vmap; 356254885Sdumbbell int vmapping_count; 357254885Sdumbbell}; 358254885Sdumbbell#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 359254885Sdumbbell 360254885Sdumbbellstruct radeon_bo_list { 361254885Sdumbbell struct ttm_validate_buffer tv; 362254885Sdumbbell struct radeon_bo *bo; 363254885Sdumbbell uint64_t gpu_offset; 364254885Sdumbbell unsigned rdomain; 365254885Sdumbbell unsigned wdomain; 366254885Sdumbbell u32 tiling_flags; 367254885Sdumbbell}; 368254885Sdumbbell 369254885Sdumbbell/* sub-allocation manager, it has to be protected by another lock. 370254885Sdumbbell * By conception this is an helper for other part of the driver 371254885Sdumbbell * like the indirect buffer or semaphore, which both have their 372254885Sdumbbell * locking. 373254885Sdumbbell * 374254885Sdumbbell * Principe is simple, we keep a list of sub allocation in offset 375254885Sdumbbell * order (first entry has offset == 0, last entry has the highest 376254885Sdumbbell * offset). 377254885Sdumbbell * 378254885Sdumbbell * When allocating new object we first check if there is room at 379254885Sdumbbell * the end total_size - (last_object_offset + last_object_size) >= 380254885Sdumbbell * alloc_size. If so we allocate new object there. 381254885Sdumbbell * 382254885Sdumbbell * When there is not enough room at the end, we start waiting for 383254885Sdumbbell * each sub object until we reach object_offset+object_size >= 384254885Sdumbbell * alloc_size, this object then become the sub object we return. 385254885Sdumbbell * 386254885Sdumbbell * Alignment can't be bigger than page size. 387254885Sdumbbell * 388254885Sdumbbell * Hole are not considered for allocation to keep things simple. 389254885Sdumbbell * Assumption is that there won't be hole (all object on same 390254885Sdumbbell * alignment). 391254885Sdumbbell */ 392254885Sdumbbellstruct radeon_sa_manager { 393254885Sdumbbell struct cv wq; 394254885Sdumbbell struct sx wq_lock; 395254885Sdumbbell struct radeon_bo *bo; 396254885Sdumbbell struct list_head *hole; 397254885Sdumbbell struct list_head flist[RADEON_NUM_RINGS]; 398254885Sdumbbell struct list_head olist; 399254885Sdumbbell unsigned size; 400254885Sdumbbell uint64_t gpu_addr; 401254885Sdumbbell void *cpu_ptr; 402254885Sdumbbell uint32_t domain; 403254885Sdumbbell}; 404254885Sdumbbell 405254885Sdumbbellstruct radeon_sa_bo; 406254885Sdumbbell 407254885Sdumbbell/* sub-allocation buffer */ 408254885Sdumbbellstruct radeon_sa_bo { 409254885Sdumbbell struct list_head olist; 410254885Sdumbbell struct list_head flist; 411254885Sdumbbell struct radeon_sa_manager *manager; 412254885Sdumbbell unsigned soffset; 413254885Sdumbbell unsigned eoffset; 414254885Sdumbbell struct radeon_fence *fence; 415254885Sdumbbell}; 416254885Sdumbbell 417254885Sdumbbell/* 418254885Sdumbbell * GEM objects. 419254885Sdumbbell */ 420254885Sdumbbellstruct radeon_gem { 421254885Sdumbbell struct sx mutex; 422254885Sdumbbell struct list_head objects; 423254885Sdumbbell}; 424254885Sdumbbell 425254885Sdumbbellint radeon_gem_init(struct radeon_device *rdev); 426254885Sdumbbellvoid radeon_gem_fini(struct radeon_device *rdev); 427254885Sdumbbellint radeon_gem_object_create(struct radeon_device *rdev, int size, 428254885Sdumbbell int alignment, int initial_domain, 429254885Sdumbbell bool discardable, bool kernel, 430254885Sdumbbell struct drm_gem_object **obj); 431254885Sdumbbell 432254885Sdumbbellint radeon_mode_dumb_create(struct drm_file *file_priv, 433254885Sdumbbell struct drm_device *dev, 434254885Sdumbbell struct drm_mode_create_dumb *args); 435254885Sdumbbellint radeon_mode_dumb_mmap(struct drm_file *filp, 436254885Sdumbbell struct drm_device *dev, 437254885Sdumbbell uint32_t handle, uint64_t *offset_p); 438254885Sdumbbellint radeon_mode_dumb_destroy(struct drm_file *file_priv, 439254885Sdumbbell struct drm_device *dev, 440254885Sdumbbell uint32_t handle); 441254885Sdumbbell 442254885Sdumbbell/* 443254885Sdumbbell * Semaphores. 444254885Sdumbbell */ 445254885Sdumbbell/* everything here is constant */ 446254885Sdumbbellstruct radeon_semaphore { 447254885Sdumbbell struct radeon_sa_bo *sa_bo; 448254885Sdumbbell signed waiters; 449254885Sdumbbell uint64_t gpu_addr; 450254885Sdumbbell}; 451254885Sdumbbell 452254885Sdumbbellint radeon_semaphore_create(struct radeon_device *rdev, 453254885Sdumbbell struct radeon_semaphore **semaphore); 454254885Sdumbbellvoid radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 455254885Sdumbbell struct radeon_semaphore *semaphore); 456254885Sdumbbellvoid radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 457254885Sdumbbell struct radeon_semaphore *semaphore); 458254885Sdumbbellint radeon_semaphore_sync_rings(struct radeon_device *rdev, 459254885Sdumbbell struct radeon_semaphore *semaphore, 460254885Sdumbbell int signaler, int waiter); 461254885Sdumbbellvoid radeon_semaphore_free(struct radeon_device *rdev, 462254885Sdumbbell struct radeon_semaphore **semaphore, 463254885Sdumbbell struct radeon_fence *fence); 464254885Sdumbbell 465254885Sdumbbell/* 466254885Sdumbbell * GART structures, functions & helpers 467254885Sdumbbell */ 468254885Sdumbbellstruct radeon_mc; 469254885Sdumbbell 470254885Sdumbbell#define RADEON_GPU_PAGE_SIZE 4096 471254885Sdumbbell#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 472254885Sdumbbell#define RADEON_GPU_PAGE_SHIFT 12 473254885Sdumbbell#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 474254885Sdumbbell 475254885Sdumbbellstruct radeon_gart { 476254885Sdumbbell drm_dma_handle_t *dmah; 477254885Sdumbbell dma_addr_t table_addr; 478254885Sdumbbell struct radeon_bo *robj; 479254885Sdumbbell void *ptr; 480254885Sdumbbell unsigned num_gpu_pages; 481254885Sdumbbell unsigned num_cpu_pages; 482254885Sdumbbell unsigned table_size; 483254885Sdumbbell vm_page_t *pages; 484254885Sdumbbell dma_addr_t *pages_addr; 485254885Sdumbbell bool ready; 486254885Sdumbbell}; 487254885Sdumbbell 488254885Sdumbbellint radeon_gart_table_ram_alloc(struct radeon_device *rdev); 489254885Sdumbbellvoid radeon_gart_table_ram_free(struct radeon_device *rdev); 490254885Sdumbbellint radeon_gart_table_vram_alloc(struct radeon_device *rdev); 491254885Sdumbbellvoid radeon_gart_table_vram_free(struct radeon_device *rdev); 492254885Sdumbbellint radeon_gart_table_vram_pin(struct radeon_device *rdev); 493254885Sdumbbellvoid radeon_gart_table_vram_unpin(struct radeon_device *rdev); 494254885Sdumbbellint radeon_gart_init(struct radeon_device *rdev); 495254885Sdumbbellvoid radeon_gart_fini(struct radeon_device *rdev); 496254885Sdumbbellvoid radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 497254885Sdumbbell int pages); 498254885Sdumbbellint radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 499254885Sdumbbell int pages, vm_page_t *pagelist, 500254885Sdumbbell dma_addr_t *dma_addr); 501254885Sdumbbellvoid radeon_gart_restore(struct radeon_device *rdev); 502254885Sdumbbell 503254885Sdumbbell 504254885Sdumbbell/* 505254885Sdumbbell * GPU MC structures, functions & helpers 506254885Sdumbbell */ 507254885Sdumbbellstruct radeon_mc { 508254885Sdumbbell resource_size_t aper_size; 509254885Sdumbbell resource_size_t aper_base; 510254885Sdumbbell resource_size_t agp_base; 511254885Sdumbbell /* for some chips with <= 32MB we need to lie 512254885Sdumbbell * about vram size near mc fb location */ 513254885Sdumbbell u64 mc_vram_size; 514254885Sdumbbell u64 visible_vram_size; 515254885Sdumbbell u64 gtt_size; 516254885Sdumbbell u64 gtt_start; 517254885Sdumbbell u64 gtt_end; 518254885Sdumbbell u64 vram_start; 519254885Sdumbbell u64 vram_end; 520254885Sdumbbell unsigned vram_width; 521254885Sdumbbell u64 real_vram_size; 522254885Sdumbbell int vram_mtrr; 523254885Sdumbbell bool vram_is_ddr; 524254885Sdumbbell bool igp_sideport_enabled; 525254885Sdumbbell u64 gtt_base_align; 526254885Sdumbbell}; 527254885Sdumbbell 528254885Sdumbbellbool radeon_combios_sideport_present(struct radeon_device *rdev); 529254885Sdumbbellbool radeon_atombios_sideport_present(struct radeon_device *rdev); 530254885Sdumbbell 531254885Sdumbbell/* 532254885Sdumbbell * GPU scratch registers structures, functions & helpers 533254885Sdumbbell */ 534254885Sdumbbellstruct radeon_scratch { 535254885Sdumbbell unsigned num_reg; 536254885Sdumbbell uint32_t reg_base; 537254885Sdumbbell bool free[32]; 538254885Sdumbbell uint32_t reg[32]; 539254885Sdumbbell}; 540254885Sdumbbell 541254885Sdumbbellint radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 542254885Sdumbbellvoid radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 543254885Sdumbbell 544254885Sdumbbell 545254885Sdumbbell/* 546254885Sdumbbell * IRQS. 547254885Sdumbbell */ 548254885Sdumbbell 549254885Sdumbbellstruct radeon_unpin_work { 550254885Sdumbbell struct task work; 551254885Sdumbbell struct radeon_device *rdev; 552254885Sdumbbell int crtc_id; 553254885Sdumbbell struct radeon_fence *fence; 554254885Sdumbbell struct drm_pending_vblank_event *event; 555254885Sdumbbell struct radeon_bo *old_rbo; 556254885Sdumbbell u64 new_crtc_base; 557254885Sdumbbell}; 558254885Sdumbbell 559254885Sdumbbellstruct r500_irq_stat_regs { 560254885Sdumbbell u32 disp_int; 561254885Sdumbbell u32 hdmi0_status; 562254885Sdumbbell}; 563254885Sdumbbell 564254885Sdumbbellstruct r600_irq_stat_regs { 565254885Sdumbbell u32 disp_int; 566254885Sdumbbell u32 disp_int_cont; 567254885Sdumbbell u32 disp_int_cont2; 568254885Sdumbbell u32 d1grph_int; 569254885Sdumbbell u32 d2grph_int; 570254885Sdumbbell u32 hdmi0_status; 571254885Sdumbbell u32 hdmi1_status; 572254885Sdumbbell}; 573254885Sdumbbell 574254885Sdumbbellstruct evergreen_irq_stat_regs { 575254885Sdumbbell u32 disp_int; 576254885Sdumbbell u32 disp_int_cont; 577254885Sdumbbell u32 disp_int_cont2; 578254885Sdumbbell u32 disp_int_cont3; 579254885Sdumbbell u32 disp_int_cont4; 580254885Sdumbbell u32 disp_int_cont5; 581254885Sdumbbell u32 d1grph_int; 582254885Sdumbbell u32 d2grph_int; 583254885Sdumbbell u32 d3grph_int; 584254885Sdumbbell u32 d4grph_int; 585254885Sdumbbell u32 d5grph_int; 586254885Sdumbbell u32 d6grph_int; 587254885Sdumbbell u32 afmt_status1; 588254885Sdumbbell u32 afmt_status2; 589254885Sdumbbell u32 afmt_status3; 590254885Sdumbbell u32 afmt_status4; 591254885Sdumbbell u32 afmt_status5; 592254885Sdumbbell u32 afmt_status6; 593254885Sdumbbell}; 594254885Sdumbbell 595254885Sdumbbellunion radeon_irq_stat_regs { 596254885Sdumbbell struct r500_irq_stat_regs r500; 597254885Sdumbbell struct r600_irq_stat_regs r600; 598254885Sdumbbell struct evergreen_irq_stat_regs evergreen; 599254885Sdumbbell}; 600254885Sdumbbell 601254885Sdumbbell#define RADEON_MAX_HPD_PINS 6 602254885Sdumbbell#define RADEON_MAX_CRTCS 6 603254885Sdumbbell#define RADEON_MAX_AFMT_BLOCKS 6 604254885Sdumbbell 605254885Sdumbbellstruct radeon_irq { 606254885Sdumbbell bool installed; 607254885Sdumbbell struct mtx lock; 608254885Sdumbbell atomic_t ring_int[RADEON_NUM_RINGS]; 609254885Sdumbbell bool crtc_vblank_int[RADEON_MAX_CRTCS]; 610254885Sdumbbell atomic_t pflip[RADEON_MAX_CRTCS]; 611254885Sdumbbell wait_queue_head_t vblank_queue; 612254885Sdumbbell bool hpd[RADEON_MAX_HPD_PINS]; 613254885Sdumbbell bool afmt[RADEON_MAX_AFMT_BLOCKS]; 614254885Sdumbbell union radeon_irq_stat_regs stat_regs; 615254885Sdumbbell}; 616254885Sdumbbell 617254885Sdumbbellint radeon_irq_kms_init(struct radeon_device *rdev); 618254885Sdumbbellvoid radeon_irq_kms_fini(struct radeon_device *rdev); 619254885Sdumbbellvoid radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 620254885Sdumbbellvoid radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 621254885Sdumbbellvoid radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 622254885Sdumbbellvoid radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 623254885Sdumbbellvoid radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 624254885Sdumbbellvoid radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 625254885Sdumbbellvoid radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 626254885Sdumbbellvoid radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 627254885Sdumbbell 628254885Sdumbbell/* 629254885Sdumbbell * CP & rings. 630254885Sdumbbell */ 631254885Sdumbbell 632254885Sdumbbellstruct radeon_ib { 633254885Sdumbbell struct radeon_sa_bo *sa_bo; 634254885Sdumbbell uint32_t length_dw; 635254885Sdumbbell uint64_t gpu_addr; 636254885Sdumbbell uint32_t *ptr; 637254885Sdumbbell int ring; 638254885Sdumbbell struct radeon_fence *fence; 639254885Sdumbbell struct radeon_vm *vm; 640254885Sdumbbell bool is_const_ib; 641254885Sdumbbell struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 642254885Sdumbbell struct radeon_semaphore *semaphore; 643254885Sdumbbell}; 644254885Sdumbbell 645254885Sdumbbellstruct radeon_ring { 646254885Sdumbbell struct radeon_bo *ring_obj; 647254885Sdumbbell volatile uint32_t *ring; 648254885Sdumbbell unsigned rptr; 649254885Sdumbbell unsigned rptr_offs; 650254885Sdumbbell unsigned rptr_reg; 651254885Sdumbbell unsigned rptr_save_reg; 652254885Sdumbbell u64 next_rptr_gpu_addr; 653254885Sdumbbell volatile u32 *next_rptr_cpu_addr; 654254885Sdumbbell unsigned wptr; 655254885Sdumbbell unsigned wptr_old; 656254885Sdumbbell unsigned wptr_reg; 657254885Sdumbbell unsigned ring_size; 658254885Sdumbbell unsigned ring_free_dw; 659254885Sdumbbell int count_dw; 660254885Sdumbbell unsigned long last_activity; 661254885Sdumbbell unsigned last_rptr; 662254885Sdumbbell uint64_t gpu_addr; 663254885Sdumbbell uint32_t align_mask; 664254885Sdumbbell uint32_t ptr_mask; 665254885Sdumbbell bool ready; 666254885Sdumbbell u32 ptr_reg_shift; 667254885Sdumbbell u32 ptr_reg_mask; 668254885Sdumbbell u32 nop; 669254885Sdumbbell u32 idx; 670254885Sdumbbell u64 last_semaphore_signal_addr; 671254885Sdumbbell u64 last_semaphore_wait_addr; 672254885Sdumbbell}; 673254885Sdumbbell 674254885Sdumbbell/* 675254885Sdumbbell * VM 676254885Sdumbbell */ 677254885Sdumbbell 678254885Sdumbbell/* maximum number of VMIDs */ 679254885Sdumbbell#define RADEON_NUM_VM 16 680254885Sdumbbell 681254885Sdumbbell/* defines number of bits in page table versus page directory, 682254885Sdumbbell * a page is 4KB so we have 12 bits offset, 9 bits in the page 683254885Sdumbbell * table and the remaining 19 bits are in the page directory */ 684254885Sdumbbell#define RADEON_VM_BLOCK_SIZE 9 685254885Sdumbbell 686254885Sdumbbell/* number of entries in page table */ 687254885Sdumbbell#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) 688254885Sdumbbell 689254885Sdumbbellstruct radeon_vm { 690254885Sdumbbell struct list_head list; 691254885Sdumbbell struct list_head va; 692254885Sdumbbell unsigned id; 693254885Sdumbbell 694254885Sdumbbell /* contains the page directory */ 695254885Sdumbbell struct radeon_sa_bo *page_directory; 696254885Sdumbbell uint64_t pd_gpu_addr; 697254885Sdumbbell 698254885Sdumbbell /* array of page tables, one for each page directory entry */ 699254885Sdumbbell struct radeon_sa_bo **page_tables; 700254885Sdumbbell 701254885Sdumbbell struct sx mutex; 702254885Sdumbbell /* last fence for cs using this vm */ 703254885Sdumbbell struct radeon_fence *fence; 704254885Sdumbbell /* last flush or NULL if we still need to flush */ 705254885Sdumbbell struct radeon_fence *last_flush; 706254885Sdumbbell}; 707254885Sdumbbell 708254885Sdumbbellstruct radeon_vm_manager { 709254885Sdumbbell struct sx lock; 710254885Sdumbbell struct list_head lru_vm; 711254885Sdumbbell struct radeon_fence *active[RADEON_NUM_VM]; 712254885Sdumbbell struct radeon_sa_manager sa_manager; 713254885Sdumbbell uint32_t max_pfn; 714254885Sdumbbell /* number of VMIDs */ 715254885Sdumbbell unsigned nvm; 716254885Sdumbbell /* vram base address for page table entry */ 717254885Sdumbbell u64 vram_base_offset; 718254885Sdumbbell /* is vm enabled? */ 719254885Sdumbbell bool enabled; 720254885Sdumbbell}; 721254885Sdumbbell 722254885Sdumbbell/* 723254885Sdumbbell * file private structure 724254885Sdumbbell */ 725254885Sdumbbellstruct radeon_fpriv { 726254885Sdumbbell struct radeon_vm vm; 727254885Sdumbbell}; 728254885Sdumbbell 729254885Sdumbbell/* 730254885Sdumbbell * R6xx+ IH ring 731254885Sdumbbell */ 732254885Sdumbbellstruct r600_ih { 733254885Sdumbbell struct radeon_bo *ring_obj; 734254885Sdumbbell volatile uint32_t *ring; 735254885Sdumbbell unsigned rptr; 736254885Sdumbbell unsigned ring_size; 737254885Sdumbbell uint64_t gpu_addr; 738254885Sdumbbell uint32_t ptr_mask; 739254885Sdumbbell atomic_t lock; 740254885Sdumbbell bool enabled; 741254885Sdumbbell}; 742254885Sdumbbell 743254885Sdumbbellstruct r600_blit_cp_primitives { 744254885Sdumbbell void (*set_render_target)(struct radeon_device *rdev, int format, 745254885Sdumbbell int w, int h, u64 gpu_addr); 746254885Sdumbbell void (*cp_set_surface_sync)(struct radeon_device *rdev, 747254885Sdumbbell u32 sync_type, u32 size, 748254885Sdumbbell u64 mc_addr); 749254885Sdumbbell void (*set_shaders)(struct radeon_device *rdev); 750254885Sdumbbell void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); 751254885Sdumbbell void (*set_tex_resource)(struct radeon_device *rdev, 752254885Sdumbbell int format, int w, int h, int pitch, 753254885Sdumbbell u64 gpu_addr, u32 size); 754254885Sdumbbell void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, 755254885Sdumbbell int x2, int y2); 756254885Sdumbbell void (*draw_auto)(struct radeon_device *rdev); 757254885Sdumbbell void (*set_default_state)(struct radeon_device *rdev); 758254885Sdumbbell}; 759254885Sdumbbell 760254885Sdumbbellstruct r600_blit { 761254885Sdumbbell struct radeon_bo *shader_obj; 762254885Sdumbbell struct r600_blit_cp_primitives primitives; 763254885Sdumbbell int max_dim; 764254885Sdumbbell int ring_size_common; 765254885Sdumbbell int ring_size_per_loop; 766254885Sdumbbell u64 shader_gpu_addr; 767254885Sdumbbell u32 vs_offset, ps_offset; 768254885Sdumbbell u32 state_offset; 769254885Sdumbbell u32 state_len; 770254885Sdumbbell}; 771254885Sdumbbell 772254885Sdumbbell/* 773254885Sdumbbell * SI RLC stuff 774254885Sdumbbell */ 775254885Sdumbbellstruct si_rlc { 776254885Sdumbbell /* for power gating */ 777254885Sdumbbell struct radeon_bo *save_restore_obj; 778254885Sdumbbell uint64_t save_restore_gpu_addr; 779254885Sdumbbell /* for clear state */ 780254885Sdumbbell struct radeon_bo *clear_state_obj; 781254885Sdumbbell uint64_t clear_state_gpu_addr; 782254885Sdumbbell}; 783254885Sdumbbell 784254885Sdumbbellint radeon_ib_get(struct radeon_device *rdev, int ring, 785254885Sdumbbell struct radeon_ib *ib, struct radeon_vm *vm, 786254885Sdumbbell unsigned size); 787254885Sdumbbellvoid radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 788254885Sdumbbellint radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 789254885Sdumbbell struct radeon_ib *const_ib); 790254885Sdumbbellint radeon_ib_pool_init(struct radeon_device *rdev); 791254885Sdumbbellvoid radeon_ib_pool_fini(struct radeon_device *rdev); 792254885Sdumbbellint radeon_ib_ring_tests(struct radeon_device *rdev); 793254885Sdumbbell/* Ring access between begin & end cannot sleep */ 794254885Sdumbbellbool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 795254885Sdumbbell struct radeon_ring *ring); 796254885Sdumbbellvoid radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 797254885Sdumbbellint radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 798254885Sdumbbellint radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 799254885Sdumbbellvoid radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); 800254885Sdumbbellvoid radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); 801254885Sdumbbellvoid radeon_ring_undo(struct radeon_ring *ring); 802254885Sdumbbellvoid radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 803254885Sdumbbellint radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 804254885Sdumbbellvoid radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); 805254885Sdumbbellvoid radeon_ring_lockup_update(struct radeon_ring *ring); 806254885Sdumbbellbool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 807254885Sdumbbellunsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 808254885Sdumbbell uint32_t **data); 809254885Sdumbbellint radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 810254885Sdumbbell unsigned size, uint32_t *data); 811254885Sdumbbellint radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 812254885Sdumbbell unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, 813254885Sdumbbell u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); 814254885Sdumbbellvoid radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 815254885Sdumbbell 816254885Sdumbbell 817254885Sdumbbell/* r600 async dma */ 818254885Sdumbbellvoid r600_dma_stop(struct radeon_device *rdev); 819254885Sdumbbellint r600_dma_resume(struct radeon_device *rdev); 820254885Sdumbbellvoid r600_dma_fini(struct radeon_device *rdev); 821254885Sdumbbell 822254885Sdumbbellvoid cayman_dma_stop(struct radeon_device *rdev); 823254885Sdumbbellint cayman_dma_resume(struct radeon_device *rdev); 824254885Sdumbbellvoid cayman_dma_fini(struct radeon_device *rdev); 825254885Sdumbbell 826254885Sdumbbell/* 827254885Sdumbbell * CS. 828254885Sdumbbell */ 829254885Sdumbbellstruct radeon_cs_reloc { 830254885Sdumbbell struct drm_gem_object *gobj; 831254885Sdumbbell struct radeon_bo *robj; 832254885Sdumbbell struct radeon_bo_list lobj; 833254885Sdumbbell uint32_t handle; 834254885Sdumbbell uint32_t flags; 835254885Sdumbbell}; 836254885Sdumbbell 837254885Sdumbbellstruct radeon_cs_chunk { 838254885Sdumbbell uint32_t chunk_id; 839254885Sdumbbell uint32_t length_dw; 840254885Sdumbbell int kpage_idx[2]; 841254885Sdumbbell uint32_t *kpage[2]; 842254885Sdumbbell uint32_t *kdata; 843254885Sdumbbell void __user *user_ptr; 844254885Sdumbbell int last_copied_page; 845254885Sdumbbell int last_page_index; 846254885Sdumbbell}; 847254885Sdumbbell 848254885Sdumbbellstruct radeon_cs_parser { 849254885Sdumbbell device_t dev; 850254885Sdumbbell struct radeon_device *rdev; 851254885Sdumbbell struct drm_file *filp; 852254885Sdumbbell /* chunks */ 853254885Sdumbbell unsigned nchunks; 854254885Sdumbbell struct radeon_cs_chunk *chunks; 855254885Sdumbbell uint64_t *chunks_array; 856254885Sdumbbell /* IB */ 857254885Sdumbbell unsigned idx; 858254885Sdumbbell /* relocations */ 859254885Sdumbbell unsigned nrelocs; 860254885Sdumbbell struct radeon_cs_reloc *relocs; 861254885Sdumbbell struct radeon_cs_reloc **relocs_ptr; 862254885Sdumbbell struct list_head validated; 863254885Sdumbbell unsigned dma_reloc_idx; 864254885Sdumbbell /* indices of various chunks */ 865254885Sdumbbell int chunk_ib_idx; 866254885Sdumbbell int chunk_relocs_idx; 867254885Sdumbbell int chunk_flags_idx; 868254885Sdumbbell int chunk_const_ib_idx; 869254885Sdumbbell struct radeon_ib ib; 870254885Sdumbbell struct radeon_ib const_ib; 871254885Sdumbbell void *track; 872254885Sdumbbell unsigned family; 873254885Sdumbbell int parser_error; 874254885Sdumbbell u32 cs_flags; 875254885Sdumbbell u32 ring; 876254885Sdumbbell s32 priority; 877254885Sdumbbell}; 878254885Sdumbbell 879254885Sdumbbellextern int radeon_cs_finish_pages(struct radeon_cs_parser *p); 880254885Sdumbbellextern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); 881254885Sdumbbell 882254885Sdumbbellstruct radeon_cs_packet { 883254885Sdumbbell unsigned idx; 884254885Sdumbbell unsigned type; 885254885Sdumbbell unsigned reg; 886254885Sdumbbell unsigned opcode; 887254885Sdumbbell int count; 888254885Sdumbbell unsigned one_reg_wr; 889254885Sdumbbell}; 890254885Sdumbbell 891254885Sdumbbelltypedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 892254885Sdumbbell struct radeon_cs_packet *pkt, 893254885Sdumbbell unsigned idx, unsigned reg); 894254885Sdumbbelltypedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 895254885Sdumbbell struct radeon_cs_packet *pkt); 896254885Sdumbbell 897254885Sdumbbell 898254885Sdumbbell/* 899254885Sdumbbell * AGP 900254885Sdumbbell */ 901254885Sdumbbellint radeon_agp_init(struct radeon_device *rdev); 902254885Sdumbbellvoid radeon_agp_resume(struct radeon_device *rdev); 903254885Sdumbbellvoid radeon_agp_suspend(struct radeon_device *rdev); 904254885Sdumbbellvoid radeon_agp_fini(struct radeon_device *rdev); 905254885Sdumbbell 906254885Sdumbbell 907254885Sdumbbell/* 908254885Sdumbbell * Writeback 909254885Sdumbbell */ 910254885Sdumbbellstruct radeon_wb { 911254885Sdumbbell struct radeon_bo *wb_obj; 912254885Sdumbbell volatile uint32_t *wb; 913254885Sdumbbell uint64_t gpu_addr; 914254885Sdumbbell bool enabled; 915254885Sdumbbell bool use_event; 916254885Sdumbbell}; 917254885Sdumbbell 918254885Sdumbbell#define RADEON_WB_SCRATCH_OFFSET 0 919254885Sdumbbell#define RADEON_WB_RING0_NEXT_RPTR 256 920254885Sdumbbell#define RADEON_WB_CP_RPTR_OFFSET 1024 921254885Sdumbbell#define RADEON_WB_CP1_RPTR_OFFSET 1280 922254885Sdumbbell#define RADEON_WB_CP2_RPTR_OFFSET 1536 923254885Sdumbbell#define R600_WB_DMA_RPTR_OFFSET 1792 924254885Sdumbbell#define R600_WB_IH_WPTR_OFFSET 2048 925254885Sdumbbell#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 926254885Sdumbbell#define R600_WB_EVENT_OFFSET 3072 927254885Sdumbbell 928254885Sdumbbell/** 929254885Sdumbbell * struct radeon_pm - power management datas 930254885Sdumbbell * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 931254885Sdumbbell * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 932254885Sdumbbell * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 933254885Sdumbbell * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 934254885Sdumbbell * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 935254885Sdumbbell * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 936254885Sdumbbell * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 937254885Sdumbbell * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 938254885Sdumbbell * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 939254885Sdumbbell * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 940254885Sdumbbell * @needed_bandwidth: current bandwidth needs 941254885Sdumbbell * 942254885Sdumbbell * It keeps track of various data needed to take powermanagement decision. 943254885Sdumbbell * Bandwidth need is used to determine minimun clock of the GPU and memory. 944254885Sdumbbell * Equation between gpu/memory clock and available bandwidth is hw dependent 945254885Sdumbbell * (type of memory, bus size, efficiency, ...) 946254885Sdumbbell */ 947254885Sdumbbell 948254885Sdumbbellenum radeon_pm_method { 949254885Sdumbbell PM_METHOD_PROFILE, 950254885Sdumbbell PM_METHOD_DYNPM, 951254885Sdumbbell}; 952254885Sdumbbell 953254885Sdumbbellenum radeon_dynpm_state { 954254885Sdumbbell DYNPM_STATE_DISABLED, 955254885Sdumbbell DYNPM_STATE_MINIMUM, 956254885Sdumbbell DYNPM_STATE_PAUSED, 957254885Sdumbbell DYNPM_STATE_ACTIVE, 958254885Sdumbbell DYNPM_STATE_SUSPENDED, 959254885Sdumbbell}; 960254885Sdumbbellenum radeon_dynpm_action { 961254885Sdumbbell DYNPM_ACTION_NONE, 962254885Sdumbbell DYNPM_ACTION_MINIMUM, 963254885Sdumbbell DYNPM_ACTION_DOWNCLOCK, 964254885Sdumbbell DYNPM_ACTION_UPCLOCK, 965254885Sdumbbell DYNPM_ACTION_DEFAULT 966254885Sdumbbell}; 967254885Sdumbbell 968254885Sdumbbellenum radeon_voltage_type { 969254885Sdumbbell VOLTAGE_NONE = 0, 970254885Sdumbbell VOLTAGE_GPIO, 971254885Sdumbbell VOLTAGE_VDDC, 972254885Sdumbbell VOLTAGE_SW 973254885Sdumbbell}; 974254885Sdumbbell 975254885Sdumbbellenum radeon_pm_state_type { 976254885Sdumbbell POWER_STATE_TYPE_DEFAULT, 977254885Sdumbbell POWER_STATE_TYPE_POWERSAVE, 978254885Sdumbbell POWER_STATE_TYPE_BATTERY, 979254885Sdumbbell POWER_STATE_TYPE_BALANCED, 980254885Sdumbbell POWER_STATE_TYPE_PERFORMANCE, 981254885Sdumbbell}; 982254885Sdumbbell 983254885Sdumbbellenum radeon_pm_profile_type { 984254885Sdumbbell PM_PROFILE_DEFAULT, 985254885Sdumbbell PM_PROFILE_AUTO, 986254885Sdumbbell PM_PROFILE_LOW, 987254885Sdumbbell PM_PROFILE_MID, 988254885Sdumbbell PM_PROFILE_HIGH, 989254885Sdumbbell}; 990254885Sdumbbell 991254885Sdumbbell#define PM_PROFILE_DEFAULT_IDX 0 992254885Sdumbbell#define PM_PROFILE_LOW_SH_IDX 1 993254885Sdumbbell#define PM_PROFILE_MID_SH_IDX 2 994254885Sdumbbell#define PM_PROFILE_HIGH_SH_IDX 3 995254885Sdumbbell#define PM_PROFILE_LOW_MH_IDX 4 996254885Sdumbbell#define PM_PROFILE_MID_MH_IDX 5 997254885Sdumbbell#define PM_PROFILE_HIGH_MH_IDX 6 998254885Sdumbbell#define PM_PROFILE_MAX 7 999254885Sdumbbell 1000254885Sdumbbellstruct radeon_pm_profile { 1001254885Sdumbbell int dpms_off_ps_idx; 1002254885Sdumbbell int dpms_on_ps_idx; 1003254885Sdumbbell int dpms_off_cm_idx; 1004254885Sdumbbell int dpms_on_cm_idx; 1005254885Sdumbbell}; 1006254885Sdumbbell 1007254885Sdumbbellenum radeon_int_thermal_type { 1008254885Sdumbbell THERMAL_TYPE_NONE, 1009254885Sdumbbell THERMAL_TYPE_RV6XX, 1010254885Sdumbbell THERMAL_TYPE_RV770, 1011254885Sdumbbell THERMAL_TYPE_EVERGREEN, 1012254885Sdumbbell THERMAL_TYPE_SUMO, 1013254885Sdumbbell THERMAL_TYPE_NI, 1014254885Sdumbbell THERMAL_TYPE_SI, 1015254885Sdumbbell}; 1016254885Sdumbbell 1017254885Sdumbbellstruct radeon_voltage { 1018254885Sdumbbell enum radeon_voltage_type type; 1019254885Sdumbbell /* gpio voltage */ 1020254885Sdumbbell struct radeon_gpio_rec gpio; 1021254885Sdumbbell u32 delay; /* delay in usec from voltage drop to sclk change */ 1022254885Sdumbbell bool active_high; /* voltage drop is active when bit is high */ 1023254885Sdumbbell /* VDDC voltage */ 1024254885Sdumbbell u8 vddc_id; /* index into vddc voltage table */ 1025254885Sdumbbell u8 vddci_id; /* index into vddci voltage table */ 1026254885Sdumbbell bool vddci_enabled; 1027254885Sdumbbell /* r6xx+ sw */ 1028254885Sdumbbell u16 voltage; 1029254885Sdumbbell /* evergreen+ vddci */ 1030254885Sdumbbell u16 vddci; 1031254885Sdumbbell}; 1032254885Sdumbbell 1033254885Sdumbbell/* clock mode flags */ 1034254885Sdumbbell#define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1035254885Sdumbbell 1036254885Sdumbbellstruct radeon_pm_clock_info { 1037254885Sdumbbell /* memory clock */ 1038254885Sdumbbell u32 mclk; 1039254885Sdumbbell /* engine clock */ 1040254885Sdumbbell u32 sclk; 1041254885Sdumbbell /* voltage info */ 1042254885Sdumbbell struct radeon_voltage voltage; 1043254885Sdumbbell /* standardized clock flags */ 1044254885Sdumbbell u32 flags; 1045254885Sdumbbell}; 1046254885Sdumbbell 1047254885Sdumbbell/* state flags */ 1048254885Sdumbbell#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1049254885Sdumbbell 1050254885Sdumbbellstruct radeon_power_state { 1051254885Sdumbbell enum radeon_pm_state_type type; 1052254885Sdumbbell struct radeon_pm_clock_info *clock_info; 1053254885Sdumbbell /* number of valid clock modes in this power state */ 1054254885Sdumbbell int num_clock_modes; 1055254885Sdumbbell struct radeon_pm_clock_info *default_clock_mode; 1056254885Sdumbbell /* standardized state flags */ 1057254885Sdumbbell u32 flags; 1058254885Sdumbbell u32 misc; /* vbios specific flags */ 1059254885Sdumbbell u32 misc2; /* vbios specific flags */ 1060254885Sdumbbell int pcie_lanes; /* pcie lanes */ 1061254885Sdumbbell}; 1062254885Sdumbbell 1063254885Sdumbbell/* 1064254885Sdumbbell * Some modes are overclocked by very low value, accept them 1065254885Sdumbbell */ 1066254885Sdumbbell#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1067254885Sdumbbell 1068254885Sdumbbellstruct radeon_pm { 1069254885Sdumbbell struct sx mutex; 1070254885Sdumbbell /* write locked while reprogramming mclk */ 1071254885Sdumbbell struct sx mclk_lock; 1072254885Sdumbbell u32 active_crtcs; 1073254885Sdumbbell int active_crtc_count; 1074254885Sdumbbell int req_vblank; 1075254885Sdumbbell bool vblank_sync; 1076254885Sdumbbell fixed20_12 max_bandwidth; 1077254885Sdumbbell fixed20_12 igp_sideport_mclk; 1078254885Sdumbbell fixed20_12 igp_system_mclk; 1079254885Sdumbbell fixed20_12 igp_ht_link_clk; 1080254885Sdumbbell fixed20_12 igp_ht_link_width; 1081254885Sdumbbell fixed20_12 k8_bandwidth; 1082254885Sdumbbell fixed20_12 sideport_bandwidth; 1083254885Sdumbbell fixed20_12 ht_bandwidth; 1084254885Sdumbbell fixed20_12 core_bandwidth; 1085254885Sdumbbell fixed20_12 sclk; 1086254885Sdumbbell fixed20_12 mclk; 1087254885Sdumbbell fixed20_12 needed_bandwidth; 1088254885Sdumbbell struct radeon_power_state *power_state; 1089254885Sdumbbell /* number of valid power states */ 1090254885Sdumbbell int num_power_states; 1091254885Sdumbbell int current_power_state_index; 1092254885Sdumbbell int current_clock_mode_index; 1093254885Sdumbbell int requested_power_state_index; 1094254885Sdumbbell int requested_clock_mode_index; 1095254885Sdumbbell int default_power_state_index; 1096254885Sdumbbell u32 current_sclk; 1097254885Sdumbbell u32 current_mclk; 1098254885Sdumbbell u16 current_vddc; 1099254885Sdumbbell u16 current_vddci; 1100254885Sdumbbell u32 default_sclk; 1101254885Sdumbbell u32 default_mclk; 1102254885Sdumbbell u16 default_vddc; 1103254885Sdumbbell u16 default_vddci; 1104254885Sdumbbell struct radeon_i2c_chan *i2c_bus; 1105254885Sdumbbell /* selected pm method */ 1106254885Sdumbbell enum radeon_pm_method pm_method; 1107254885Sdumbbell /* dynpm power management */ 1108282199Sdumbbell#ifdef FREEBSD_WIP 1109254885Sdumbbell struct delayed_work dynpm_idle_work; 1110282199Sdumbbell#endif /* FREEBSD_WIP */ 1111254885Sdumbbell enum radeon_dynpm_state dynpm_state; 1112254885Sdumbbell enum radeon_dynpm_action dynpm_planned_action; 1113254885Sdumbbell unsigned long dynpm_action_timeout; 1114254885Sdumbbell bool dynpm_can_upclock; 1115254885Sdumbbell bool dynpm_can_downclock; 1116254885Sdumbbell /* profile-based power management */ 1117254885Sdumbbell enum radeon_pm_profile_type profile; 1118254885Sdumbbell int profile_index; 1119254885Sdumbbell struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1120254885Sdumbbell /* internal thermal controller on rv6xx+ */ 1121254885Sdumbbell enum radeon_int_thermal_type int_thermal_type; 1122282199Sdumbbell#ifdef FREEBSD_WIP 1123254885Sdumbbell struct device *int_hwmon_dev; 1124282199Sdumbbell#endif /* FREEBSD_WIP */ 1125254885Sdumbbell}; 1126254885Sdumbbell 1127254885Sdumbbellint radeon_pm_get_type_index(struct radeon_device *rdev, 1128254885Sdumbbell enum radeon_pm_state_type ps_type, 1129254885Sdumbbell int instance); 1130254885Sdumbbell 1131254885Sdumbbellstruct r600_audio { 1132254885Sdumbbell int channels; 1133254885Sdumbbell int rate; 1134254885Sdumbbell int bits_per_sample; 1135254885Sdumbbell u8 status_bits; 1136254885Sdumbbell u8 category_code; 1137254885Sdumbbell}; 1138254885Sdumbbell 1139254885Sdumbbell/* 1140254885Sdumbbell * Benchmarking 1141254885Sdumbbell */ 1142254885Sdumbbellvoid radeon_benchmark(struct radeon_device *rdev, int test_number); 1143254885Sdumbbell 1144254885Sdumbbell 1145254885Sdumbbell/* 1146254885Sdumbbell * Testing 1147254885Sdumbbell */ 1148254885Sdumbbellvoid radeon_test_moves(struct radeon_device *rdev); 1149254885Sdumbbellvoid radeon_test_ring_sync(struct radeon_device *rdev, 1150254885Sdumbbell struct radeon_ring *cpA, 1151254885Sdumbbell struct radeon_ring *cpB); 1152254885Sdumbbellvoid radeon_test_syncing(struct radeon_device *rdev); 1153254885Sdumbbell 1154254885Sdumbbell 1155254885Sdumbbell/* 1156254885Sdumbbell * Debugfs 1157254885Sdumbbell */ 1158254885Sdumbbellstruct radeon_debugfs { 1159254885Sdumbbell struct drm_info_list *files; 1160254885Sdumbbell unsigned num_files; 1161254885Sdumbbell}; 1162254885Sdumbbell 1163254885Sdumbbellint radeon_debugfs_add_files(struct radeon_device *rdev, 1164254885Sdumbbell struct drm_info_list *files, 1165254885Sdumbbell unsigned nfiles); 1166254885Sdumbbellint radeon_debugfs_fence_init(struct radeon_device *rdev); 1167254885Sdumbbell 1168254885Sdumbbell 1169254885Sdumbbell/* 1170254885Sdumbbell * ASIC specific functions. 1171254885Sdumbbell */ 1172254885Sdumbbellstruct radeon_asic { 1173254885Sdumbbell int (*init)(struct radeon_device *rdev); 1174254885Sdumbbell void (*fini)(struct radeon_device *rdev); 1175254885Sdumbbell int (*resume)(struct radeon_device *rdev); 1176254885Sdumbbell int (*suspend)(struct radeon_device *rdev); 1177254885Sdumbbell void (*vga_set_state)(struct radeon_device *rdev, bool state); 1178254885Sdumbbell int (*asic_reset)(struct radeon_device *rdev); 1179254885Sdumbbell /* ioctl hw specific callback. Some hw might want to perform special 1180254885Sdumbbell * operation on specific ioctl. For instance on wait idle some hw 1181254885Sdumbbell * might want to perform and HDP flush through MMIO as it seems that 1182254885Sdumbbell * some R6XX/R7XX hw doesn't take HDP flush into account if programmed 1183254885Sdumbbell * through ring. 1184254885Sdumbbell */ 1185254885Sdumbbell void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); 1186254885Sdumbbell /* check if 3D engine is idle */ 1187254885Sdumbbell bool (*gui_idle)(struct radeon_device *rdev); 1188254885Sdumbbell /* wait for mc_idle */ 1189254885Sdumbbell int (*mc_wait_for_idle)(struct radeon_device *rdev); 1190254885Sdumbbell /* gart */ 1191254885Sdumbbell struct { 1192254885Sdumbbell void (*tlb_flush)(struct radeon_device *rdev); 1193254885Sdumbbell int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); 1194254885Sdumbbell } gart; 1195254885Sdumbbell struct { 1196254885Sdumbbell int (*init)(struct radeon_device *rdev); 1197254885Sdumbbell void (*fini)(struct radeon_device *rdev); 1198254885Sdumbbell 1199254885Sdumbbell u32 pt_ring_index; 1200254885Sdumbbell void (*set_page)(struct radeon_device *rdev, uint64_t pe, 1201254885Sdumbbell uint64_t addr, unsigned count, 1202254885Sdumbbell uint32_t incr, uint32_t flags); 1203254885Sdumbbell } vm; 1204254885Sdumbbell /* ring specific callbacks */ 1205254885Sdumbbell struct { 1206254885Sdumbbell void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1207254885Sdumbbell int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1208254885Sdumbbell void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1209254885Sdumbbell void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1210254885Sdumbbell struct radeon_semaphore *semaphore, bool emit_wait); 1211254885Sdumbbell int (*cs_parse)(struct radeon_cs_parser *p); 1212254885Sdumbbell void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1213254885Sdumbbell int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1214254885Sdumbbell int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1215254885Sdumbbell bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1216254885Sdumbbell void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1217254885Sdumbbell } ring[RADEON_NUM_RINGS]; 1218254885Sdumbbell /* irqs */ 1219254885Sdumbbell struct { 1220254885Sdumbbell int (*set)(struct radeon_device *rdev); 1221254885Sdumbbell irqreturn_t (*process)(struct radeon_device *rdev); 1222254885Sdumbbell } irq; 1223254885Sdumbbell /* displays */ 1224254885Sdumbbell struct { 1225254885Sdumbbell /* display watermarks */ 1226254885Sdumbbell void (*bandwidth_update)(struct radeon_device *rdev); 1227254885Sdumbbell /* get frame count */ 1228254885Sdumbbell u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1229254885Sdumbbell /* wait for vblank */ 1230254885Sdumbbell void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1231254885Sdumbbell /* set backlight level */ 1232254885Sdumbbell void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1233254885Sdumbbell /* get backlight level */ 1234254885Sdumbbell u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1235254885Sdumbbell } display; 1236254885Sdumbbell /* copy functions for bo handling */ 1237254885Sdumbbell struct { 1238254885Sdumbbell int (*blit)(struct radeon_device *rdev, 1239254885Sdumbbell uint64_t src_offset, 1240254885Sdumbbell uint64_t dst_offset, 1241254885Sdumbbell unsigned num_gpu_pages, 1242254885Sdumbbell struct radeon_fence **fence); 1243254885Sdumbbell u32 blit_ring_index; 1244254885Sdumbbell int (*dma)(struct radeon_device *rdev, 1245254885Sdumbbell uint64_t src_offset, 1246254885Sdumbbell uint64_t dst_offset, 1247254885Sdumbbell unsigned num_gpu_pages, 1248254885Sdumbbell struct radeon_fence **fence); 1249254885Sdumbbell u32 dma_ring_index; 1250254885Sdumbbell /* method used for bo copy */ 1251254885Sdumbbell int (*copy)(struct radeon_device *rdev, 1252254885Sdumbbell uint64_t src_offset, 1253254885Sdumbbell uint64_t dst_offset, 1254254885Sdumbbell unsigned num_gpu_pages, 1255254885Sdumbbell struct radeon_fence **fence); 1256254885Sdumbbell /* ring used for bo copies */ 1257254885Sdumbbell u32 copy_ring_index; 1258254885Sdumbbell } copy; 1259254885Sdumbbell /* surfaces */ 1260254885Sdumbbell struct { 1261254885Sdumbbell int (*set_reg)(struct radeon_device *rdev, int reg, 1262254885Sdumbbell uint32_t tiling_flags, uint32_t pitch, 1263254885Sdumbbell uint32_t offset, uint32_t obj_size); 1264254885Sdumbbell void (*clear_reg)(struct radeon_device *rdev, int reg); 1265254885Sdumbbell } surface; 1266254885Sdumbbell /* hotplug detect */ 1267254885Sdumbbell struct { 1268254885Sdumbbell void (*init)(struct radeon_device *rdev); 1269254885Sdumbbell void (*fini)(struct radeon_device *rdev); 1270254885Sdumbbell bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1271254885Sdumbbell void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1272254885Sdumbbell } hpd; 1273254885Sdumbbell /* power management */ 1274254885Sdumbbell struct { 1275254885Sdumbbell void (*misc)(struct radeon_device *rdev); 1276254885Sdumbbell void (*prepare)(struct radeon_device *rdev); 1277254885Sdumbbell void (*finish)(struct radeon_device *rdev); 1278254885Sdumbbell void (*init_profile)(struct radeon_device *rdev); 1279254885Sdumbbell void (*get_dynpm_state)(struct radeon_device *rdev); 1280254885Sdumbbell uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1281254885Sdumbbell void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1282254885Sdumbbell uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1283254885Sdumbbell void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1284254885Sdumbbell int (*get_pcie_lanes)(struct radeon_device *rdev); 1285254885Sdumbbell void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1286254885Sdumbbell void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1287254885Sdumbbell } pm; 1288254885Sdumbbell /* pageflipping */ 1289254885Sdumbbell struct { 1290254885Sdumbbell void (*pre_page_flip)(struct radeon_device *rdev, int crtc); 1291254885Sdumbbell u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1292254885Sdumbbell void (*post_page_flip)(struct radeon_device *rdev, int crtc); 1293254885Sdumbbell } pflip; 1294254885Sdumbbell}; 1295254885Sdumbbell 1296254885Sdumbbell/* 1297254885Sdumbbell * Asic structures 1298254885Sdumbbell */ 1299254885Sdumbbellstruct r100_asic { 1300254885Sdumbbell const unsigned *reg_safe_bm; 1301254885Sdumbbell unsigned reg_safe_bm_size; 1302254885Sdumbbell u32 hdp_cntl; 1303254885Sdumbbell}; 1304254885Sdumbbell 1305254885Sdumbbellstruct r300_asic { 1306254885Sdumbbell const unsigned *reg_safe_bm; 1307254885Sdumbbell unsigned reg_safe_bm_size; 1308254885Sdumbbell u32 resync_scratch; 1309254885Sdumbbell u32 hdp_cntl; 1310254885Sdumbbell}; 1311254885Sdumbbell 1312254885Sdumbbellstruct r600_asic { 1313254885Sdumbbell unsigned max_pipes; 1314254885Sdumbbell unsigned max_tile_pipes; 1315254885Sdumbbell unsigned max_simds; 1316254885Sdumbbell unsigned max_backends; 1317254885Sdumbbell unsigned max_gprs; 1318254885Sdumbbell unsigned max_threads; 1319254885Sdumbbell unsigned max_stack_entries; 1320254885Sdumbbell unsigned max_hw_contexts; 1321254885Sdumbbell unsigned max_gs_threads; 1322254885Sdumbbell unsigned sx_max_export_size; 1323254885Sdumbbell unsigned sx_max_export_pos_size; 1324254885Sdumbbell unsigned sx_max_export_smx_size; 1325254885Sdumbbell unsigned sq_num_cf_insts; 1326254885Sdumbbell unsigned tiling_nbanks; 1327254885Sdumbbell unsigned tiling_npipes; 1328254885Sdumbbell unsigned tiling_group_size; 1329254885Sdumbbell unsigned tile_config; 1330254885Sdumbbell unsigned backend_map; 1331254885Sdumbbell}; 1332254885Sdumbbell 1333254885Sdumbbellstruct rv770_asic { 1334254885Sdumbbell unsigned max_pipes; 1335254885Sdumbbell unsigned max_tile_pipes; 1336254885Sdumbbell unsigned max_simds; 1337254885Sdumbbell unsigned max_backends; 1338254885Sdumbbell unsigned max_gprs; 1339254885Sdumbbell unsigned max_threads; 1340254885Sdumbbell unsigned max_stack_entries; 1341254885Sdumbbell unsigned max_hw_contexts; 1342254885Sdumbbell unsigned max_gs_threads; 1343254885Sdumbbell unsigned sx_max_export_size; 1344254885Sdumbbell unsigned sx_max_export_pos_size; 1345254885Sdumbbell unsigned sx_max_export_smx_size; 1346254885Sdumbbell unsigned sq_num_cf_insts; 1347254885Sdumbbell unsigned sx_num_of_sets; 1348254885Sdumbbell unsigned sc_prim_fifo_size; 1349254885Sdumbbell unsigned sc_hiz_tile_fifo_size; 1350254885Sdumbbell unsigned sc_earlyz_tile_fifo_fize; 1351254885Sdumbbell unsigned tiling_nbanks; 1352254885Sdumbbell unsigned tiling_npipes; 1353254885Sdumbbell unsigned tiling_group_size; 1354254885Sdumbbell unsigned tile_config; 1355254885Sdumbbell unsigned backend_map; 1356254885Sdumbbell}; 1357254885Sdumbbell 1358254885Sdumbbellstruct evergreen_asic { 1359254885Sdumbbell unsigned num_ses; 1360254885Sdumbbell unsigned max_pipes; 1361254885Sdumbbell unsigned max_tile_pipes; 1362254885Sdumbbell unsigned max_simds; 1363254885Sdumbbell unsigned max_backends; 1364254885Sdumbbell unsigned max_gprs; 1365254885Sdumbbell unsigned max_threads; 1366254885Sdumbbell unsigned max_stack_entries; 1367254885Sdumbbell unsigned max_hw_contexts; 1368254885Sdumbbell unsigned max_gs_threads; 1369254885Sdumbbell unsigned sx_max_export_size; 1370254885Sdumbbell unsigned sx_max_export_pos_size; 1371254885Sdumbbell unsigned sx_max_export_smx_size; 1372254885Sdumbbell unsigned sq_num_cf_insts; 1373254885Sdumbbell unsigned sx_num_of_sets; 1374254885Sdumbbell unsigned sc_prim_fifo_size; 1375254885Sdumbbell unsigned sc_hiz_tile_fifo_size; 1376254885Sdumbbell unsigned sc_earlyz_tile_fifo_size; 1377254885Sdumbbell unsigned tiling_nbanks; 1378254885Sdumbbell unsigned tiling_npipes; 1379254885Sdumbbell unsigned tiling_group_size; 1380254885Sdumbbell unsigned tile_config; 1381254885Sdumbbell unsigned backend_map; 1382254885Sdumbbell}; 1383254885Sdumbbell 1384254885Sdumbbellstruct cayman_asic { 1385254885Sdumbbell unsigned max_shader_engines; 1386254885Sdumbbell unsigned max_pipes_per_simd; 1387254885Sdumbbell unsigned max_tile_pipes; 1388254885Sdumbbell unsigned max_simds_per_se; 1389254885Sdumbbell unsigned max_backends_per_se; 1390254885Sdumbbell unsigned max_texture_channel_caches; 1391254885Sdumbbell unsigned max_gprs; 1392254885Sdumbbell unsigned max_threads; 1393254885Sdumbbell unsigned max_gs_threads; 1394254885Sdumbbell unsigned max_stack_entries; 1395254885Sdumbbell unsigned sx_num_of_sets; 1396254885Sdumbbell unsigned sx_max_export_size; 1397254885Sdumbbell unsigned sx_max_export_pos_size; 1398254885Sdumbbell unsigned sx_max_export_smx_size; 1399254885Sdumbbell unsigned max_hw_contexts; 1400254885Sdumbbell unsigned sq_num_cf_insts; 1401254885Sdumbbell unsigned sc_prim_fifo_size; 1402254885Sdumbbell unsigned sc_hiz_tile_fifo_size; 1403254885Sdumbbell unsigned sc_earlyz_tile_fifo_size; 1404254885Sdumbbell 1405254885Sdumbbell unsigned num_shader_engines; 1406254885Sdumbbell unsigned num_shader_pipes_per_simd; 1407254885Sdumbbell unsigned num_tile_pipes; 1408254885Sdumbbell unsigned num_simds_per_se; 1409254885Sdumbbell unsigned num_backends_per_se; 1410254885Sdumbbell unsigned backend_disable_mask_per_asic; 1411254885Sdumbbell unsigned backend_map; 1412254885Sdumbbell unsigned num_texture_channel_caches; 1413254885Sdumbbell unsigned mem_max_burst_length_bytes; 1414254885Sdumbbell unsigned mem_row_size_in_kb; 1415254885Sdumbbell unsigned shader_engine_tile_size; 1416254885Sdumbbell unsigned num_gpus; 1417254885Sdumbbell unsigned multi_gpu_tile_size; 1418254885Sdumbbell 1419254885Sdumbbell unsigned tile_config; 1420254885Sdumbbell}; 1421254885Sdumbbell 1422254885Sdumbbellstruct si_asic { 1423254885Sdumbbell unsigned max_shader_engines; 1424254885Sdumbbell unsigned max_tile_pipes; 1425254885Sdumbbell unsigned max_cu_per_sh; 1426254885Sdumbbell unsigned max_sh_per_se; 1427254885Sdumbbell unsigned max_backends_per_se; 1428254885Sdumbbell unsigned max_texture_channel_caches; 1429254885Sdumbbell unsigned max_gprs; 1430254885Sdumbbell unsigned max_gs_threads; 1431254885Sdumbbell unsigned max_hw_contexts; 1432254885Sdumbbell unsigned sc_prim_fifo_size_frontend; 1433254885Sdumbbell unsigned sc_prim_fifo_size_backend; 1434254885Sdumbbell unsigned sc_hiz_tile_fifo_size; 1435254885Sdumbbell unsigned sc_earlyz_tile_fifo_size; 1436254885Sdumbbell 1437254885Sdumbbell unsigned num_tile_pipes; 1438254885Sdumbbell unsigned num_backends_per_se; 1439254885Sdumbbell unsigned backend_disable_mask_per_asic; 1440254885Sdumbbell unsigned backend_map; 1441254885Sdumbbell unsigned num_texture_channel_caches; 1442254885Sdumbbell unsigned mem_max_burst_length_bytes; 1443254885Sdumbbell unsigned mem_row_size_in_kb; 1444254885Sdumbbell unsigned shader_engine_tile_size; 1445254885Sdumbbell unsigned num_gpus; 1446254885Sdumbbell unsigned multi_gpu_tile_size; 1447254885Sdumbbell 1448254885Sdumbbell unsigned tile_config; 1449254885Sdumbbell}; 1450254885Sdumbbell 1451254885Sdumbbellunion radeon_asic_config { 1452254885Sdumbbell struct r300_asic r300; 1453254885Sdumbbell struct r100_asic r100; 1454254885Sdumbbell struct r600_asic r600; 1455254885Sdumbbell struct rv770_asic rv770; 1456254885Sdumbbell struct evergreen_asic evergreen; 1457254885Sdumbbell struct cayman_asic cayman; 1458254885Sdumbbell struct si_asic si; 1459254885Sdumbbell}; 1460254885Sdumbbell 1461254885Sdumbbell/* 1462254885Sdumbbell * asic initizalization from radeon_asic.c 1463254885Sdumbbell */ 1464254885Sdumbbellint radeon_asic_init(struct radeon_device *rdev); 1465254885Sdumbbell 1466254885Sdumbbell 1467254885Sdumbbell/* 1468254885Sdumbbell * IOCTL. 1469254885Sdumbbell */ 1470254885Sdumbbellint radeon_gem_info_ioctl(struct drm_device *dev, void *data, 1471254885Sdumbbell struct drm_file *filp); 1472254885Sdumbbellint radeon_gem_create_ioctl(struct drm_device *dev, void *data, 1473254885Sdumbbell struct drm_file *filp); 1474254885Sdumbbellint radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 1475254885Sdumbbell struct drm_file *file_priv); 1476254885Sdumbbellint radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 1477254885Sdumbbell struct drm_file *file_priv); 1478254885Sdumbbellint radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1479254885Sdumbbell struct drm_file *file_priv); 1480254885Sdumbbellint radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 1481254885Sdumbbell struct drm_file *file_priv); 1482254885Sdumbbellint radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1483254885Sdumbbell struct drm_file *filp); 1484254885Sdumbbellint radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 1485254885Sdumbbell struct drm_file *filp); 1486254885Sdumbbellint radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 1487254885Sdumbbell struct drm_file *filp); 1488254885Sdumbbellint radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1489254885Sdumbbell struct drm_file *filp); 1490254885Sdumbbellint radeon_gem_va_ioctl(struct drm_device *dev, void *data, 1491254885Sdumbbell struct drm_file *filp); 1492254885Sdumbbellint radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1493254885Sdumbbellint radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 1494254885Sdumbbell struct drm_file *filp); 1495254885Sdumbbellint radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 1496254885Sdumbbell struct drm_file *filp); 1497254885Sdumbbell 1498254885Sdumbbell/* VRAM scratch page for HDP bug, default vram page */ 1499254885Sdumbbellstruct r600_vram_scratch { 1500254885Sdumbbell struct radeon_bo *robj; 1501254885Sdumbbell volatile uint32_t *ptr; 1502254885Sdumbbell u64 gpu_addr; 1503254885Sdumbbell}; 1504254885Sdumbbell 1505254885Sdumbbell/* 1506254885Sdumbbell * ACPI 1507254885Sdumbbell */ 1508254885Sdumbbellstruct radeon_atif_notification_cfg { 1509254885Sdumbbell bool enabled; 1510254885Sdumbbell int command_code; 1511254885Sdumbbell}; 1512254885Sdumbbell 1513254885Sdumbbellstruct radeon_atif_notifications { 1514254885Sdumbbell bool display_switch; 1515254885Sdumbbell bool expansion_mode_change; 1516254885Sdumbbell bool thermal_state; 1517254885Sdumbbell bool forced_power_state; 1518254885Sdumbbell bool system_power_state; 1519254885Sdumbbell bool display_conf_change; 1520254885Sdumbbell bool px_gfx_switch; 1521254885Sdumbbell bool brightness_change; 1522254885Sdumbbell bool dgpu_display_event; 1523254885Sdumbbell}; 1524254885Sdumbbell 1525254885Sdumbbellstruct radeon_atif_functions { 1526254885Sdumbbell bool system_params; 1527254885Sdumbbell bool sbios_requests; 1528254885Sdumbbell bool select_active_disp; 1529254885Sdumbbell bool lid_state; 1530254885Sdumbbell bool get_tv_standard; 1531254885Sdumbbell bool set_tv_standard; 1532254885Sdumbbell bool get_panel_expansion_mode; 1533254885Sdumbbell bool set_panel_expansion_mode; 1534254885Sdumbbell bool temperature_change; 1535254885Sdumbbell bool graphics_device_types; 1536254885Sdumbbell}; 1537254885Sdumbbell 1538254885Sdumbbellstruct radeon_atif { 1539254885Sdumbbell struct radeon_atif_notifications notifications; 1540254885Sdumbbell struct radeon_atif_functions functions; 1541254885Sdumbbell struct radeon_atif_notification_cfg notification_cfg; 1542254885Sdumbbell struct radeon_encoder *encoder_for_bl; 1543254885Sdumbbell}; 1544254885Sdumbbell 1545254885Sdumbbellstruct radeon_atcs_functions { 1546254885Sdumbbell bool get_ext_state; 1547254885Sdumbbell bool pcie_perf_req; 1548254885Sdumbbell bool pcie_dev_rdy; 1549254885Sdumbbell bool pcie_bus_width; 1550254885Sdumbbell}; 1551254885Sdumbbell 1552254885Sdumbbellstruct radeon_atcs { 1553254885Sdumbbell struct radeon_atcs_functions functions; 1554254885Sdumbbell}; 1555254885Sdumbbell 1556254885Sdumbbell/* 1557254885Sdumbbell * Core structure, functions and helpers. 1558254885Sdumbbell */ 1559254885Sdumbbelltypedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 1560254885Sdumbbelltypedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 1561254885Sdumbbell 1562254885Sdumbbellstruct radeon_device { 1563254885Sdumbbell device_t dev; 1564254885Sdumbbell struct drm_device *ddev; 1565254885Sdumbbell struct sx exclusive_lock; 1566254885Sdumbbell /* ASIC */ 1567254885Sdumbbell union radeon_asic_config config; 1568254885Sdumbbell enum radeon_family family; 1569254885Sdumbbell unsigned long flags; 1570254885Sdumbbell int usec_timeout; 1571254885Sdumbbell enum radeon_pll_errata pll_errata; 1572254885Sdumbbell int num_gb_pipes; 1573254885Sdumbbell int num_z_pipes; 1574254885Sdumbbell int disp_priority; 1575254885Sdumbbell /* BIOS */ 1576254885Sdumbbell uint8_t *bios; 1577254885Sdumbbell bool is_atom_bios; 1578254885Sdumbbell uint16_t bios_header_start; 1579254885Sdumbbell struct radeon_bo *stollen_vga_memory; 1580254885Sdumbbell /* Register mmio */ 1581254885Sdumbbell resource_size_t rmmio_base; 1582254885Sdumbbell resource_size_t rmmio_size; 1583254885Sdumbbell /* protects concurrent MM_INDEX/DATA based register access */ 1584254885Sdumbbell struct mtx mmio_idx_lock; 1585254885Sdumbbell int rmmio_rid; 1586254885Sdumbbell struct resource *rmmio; 1587254885Sdumbbell radeon_rreg_t mc_rreg; 1588254885Sdumbbell radeon_wreg_t mc_wreg; 1589254885Sdumbbell radeon_rreg_t pll_rreg; 1590254885Sdumbbell radeon_wreg_t pll_wreg; 1591254885Sdumbbell uint32_t pcie_reg_mask; 1592254885Sdumbbell radeon_rreg_t pciep_rreg; 1593254885Sdumbbell radeon_wreg_t pciep_wreg; 1594254885Sdumbbell /* io port */ 1595254885Sdumbbell int rio_rid; 1596254885Sdumbbell struct resource *rio_mem; 1597254885Sdumbbell resource_size_t rio_mem_size; 1598254885Sdumbbell struct radeon_clock clock; 1599254885Sdumbbell struct radeon_mc mc; 1600254885Sdumbbell struct radeon_gart gart; 1601254885Sdumbbell struct radeon_mode_info mode_info; 1602254885Sdumbbell struct radeon_scratch scratch; 1603254885Sdumbbell struct radeon_mman mman; 1604254885Sdumbbell struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 1605254885Sdumbbell struct cv fence_queue; 1606254885Sdumbbell struct mtx fence_queue_mtx; 1607254885Sdumbbell struct sx ring_lock; 1608254885Sdumbbell struct radeon_ring ring[RADEON_NUM_RINGS]; 1609254885Sdumbbell bool ib_pool_ready; 1610254885Sdumbbell struct radeon_sa_manager ring_tmp_bo; 1611254885Sdumbbell struct radeon_irq irq; 1612254885Sdumbbell struct radeon_asic *asic; 1613254885Sdumbbell struct radeon_gem gem; 1614254885Sdumbbell struct radeon_pm pm; 1615254885Sdumbbell uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 1616254885Sdumbbell struct radeon_wb wb; 1617254885Sdumbbell struct radeon_dummy_page dummy_page; 1618254885Sdumbbell bool shutdown; 1619254885Sdumbbell bool suspend; 1620254885Sdumbbell bool need_dma32; 1621254885Sdumbbell bool accel_working; 1622254885Sdumbbell bool fictitious_range_registered; 1623275408Stijl bool fictitious_agp_range_registered; 1624254885Sdumbbell struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 1625254885Sdumbbell const struct firmware *me_fw; /* all family ME firmware */ 1626254885Sdumbbell const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 1627254885Sdumbbell const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 1628254885Sdumbbell const struct firmware *mc_fw; /* NI MC firmware */ 1629254885Sdumbbell const struct firmware *ce_fw; /* SI CE firmware */ 1630254885Sdumbbell struct r600_blit r600_blit; 1631254885Sdumbbell struct r600_vram_scratch vram_scratch; 1632254885Sdumbbell int msi_enabled; /* msi enabled */ 1633254885Sdumbbell struct r600_ih ih; /* r6/700 interrupt ring */ 1634254885Sdumbbell struct si_rlc rlc; 1635254885Sdumbbell struct taskqueue *tq; 1636254885Sdumbbell struct task hotplug_work; 1637254885Sdumbbell struct task audio_work; 1638254885Sdumbbell int num_crtc; /* number of crtcs */ 1639254885Sdumbbell struct sx dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 1640254885Sdumbbell bool audio_enabled; 1641254885Sdumbbell struct r600_audio audio_status; /* audio stuff */ 1642282199Sdumbbell#if defined(CONFIG_ACPI) 1643254885Sdumbbell struct { 1644254885Sdumbbell ACPI_HANDLE handle; 1645254885Sdumbbell ACPI_NOTIFY_HANDLER notifier_call; 1646254885Sdumbbell } acpi; 1647282199Sdumbbell#endif 1648254885Sdumbbell /* only one userspace can use Hyperz features or CMASK at a time */ 1649254885Sdumbbell struct drm_file *hyperz_filp; 1650254885Sdumbbell struct drm_file *cmask_filp; 1651254885Sdumbbell /* i2c buses */ 1652254885Sdumbbell struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 1653254885Sdumbbell /* debugfs */ 1654254885Sdumbbell struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 1655254885Sdumbbell unsigned debugfs_count; 1656254885Sdumbbell /* virtual memory */ 1657254885Sdumbbell struct radeon_vm_manager vm_manager; 1658254885Sdumbbell struct sx gpu_clock_mutex; 1659254885Sdumbbell /* ACPI interface */ 1660254885Sdumbbell struct radeon_atif atif; 1661254885Sdumbbell struct radeon_atcs atcs; 1662254885Sdumbbell}; 1663254885Sdumbbell 1664254885Sdumbbellint radeon_device_init(struct radeon_device *rdev, 1665254885Sdumbbell struct drm_device *ddev, 1666254885Sdumbbell uint32_t flags); 1667254885Sdumbbellvoid radeon_device_fini(struct radeon_device *rdev); 1668254885Sdumbbellint radeon_gpu_wait_for_idle(struct radeon_device *rdev); 1669254885Sdumbbell 1670254885Sdumbbelluint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 1671254885Sdumbbell bool always_indirect); 1672254885Sdumbbellvoid r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 1673254885Sdumbbell bool always_indirect); 1674254885Sdumbbellu32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 1675254885Sdumbbellvoid r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 1676254885Sdumbbell 1677254885Sdumbbell/* 1678254885Sdumbbell * Cast helper 1679254885Sdumbbell */ 1680254885Sdumbbell#define to_radeon_fence(p) ((struct radeon_fence *)(p)) 1681254885Sdumbbell 1682254885Sdumbbell/* 1683254885Sdumbbell * Registers read & write functions. 1684254885Sdumbbell */ 1685254885Sdumbbell#define RREG8(reg) bus_read_1((rdev->rmmio), (reg)) 1686254885Sdumbbell#define WREG8(reg, v) bus_write_1((rdev->rmmio), (reg), v) 1687254885Sdumbbell#define RREG16(reg) bus_read_2((rdev->rmmio), (reg)) 1688254885Sdumbbell#define WREG16(reg, v) bus_write_2((rdev->rmmio), (reg), v) 1689254885Sdumbbell#define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 1690254885Sdumbbell#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 1691254885Sdumbbell#define DREG32(reg) DRM_INFO("REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 1692254885Sdumbbell#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 1693254885Sdumbbell#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 1694254885Sdumbbell#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1695254885Sdumbbell#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1696254885Sdumbbell#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 1697254885Sdumbbell#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 1698254885Sdumbbell#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 1699254885Sdumbbell#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 1700254885Sdumbbell#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 1701254885Sdumbbell#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 1702254885Sdumbbell#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) 1703254885Sdumbbell#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 1704254885Sdumbbell#define WREG32_P(reg, val, mask) \ 1705254885Sdumbbell do { \ 1706254885Sdumbbell uint32_t tmp_ = RREG32(reg); \ 1707254885Sdumbbell tmp_ &= (mask); \ 1708254885Sdumbbell tmp_ |= ((val) & ~(mask)); \ 1709254885Sdumbbell WREG32(reg, tmp_); \ 1710254885Sdumbbell } while (0) 1711254885Sdumbbell#define WREG32_PLL_P(reg, val, mask) \ 1712254885Sdumbbell do { \ 1713254885Sdumbbell uint32_t tmp_ = RREG32_PLL(reg); \ 1714254885Sdumbbell tmp_ &= (mask); \ 1715254885Sdumbbell tmp_ |= ((val) & ~(mask)); \ 1716254885Sdumbbell WREG32_PLL(reg, tmp_); \ 1717254885Sdumbbell } while (0) 1718254885Sdumbbell#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 1719254885Sdumbbell#define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 1720254885Sdumbbell#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 1721254885Sdumbbell 1722254885Sdumbbell/* 1723254885Sdumbbell * Indirect registers accessor 1724254885Sdumbbell */ 1725254885Sdumbbellstatic inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 1726254885Sdumbbell{ 1727254885Sdumbbell uint32_t r; 1728254885Sdumbbell 1729254885Sdumbbell WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1730254885Sdumbbell r = RREG32(RADEON_PCIE_DATA); 1731254885Sdumbbell return r; 1732254885Sdumbbell} 1733254885Sdumbbell 1734254885Sdumbbellstatic inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1735254885Sdumbbell{ 1736254885Sdumbbell WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1737254885Sdumbbell WREG32(RADEON_PCIE_DATA, (v)); 1738254885Sdumbbell} 1739254885Sdumbbell 1740254885Sdumbbellvoid r100_pll_errata_after_index(struct radeon_device *rdev); 1741254885Sdumbbell 1742254885Sdumbbell 1743254885Sdumbbell/* 1744254885Sdumbbell * ASICs helpers. 1745254885Sdumbbell */ 1746254885Sdumbbell#define ASIC_IS_RN50(rdev) ((rdev->ddev->pci_device == 0x515e) || \ 1747254885Sdumbbell (rdev->ddev->pci_device == 0x5969)) 1748254885Sdumbbell#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 1749254885Sdumbbell (rdev->family == CHIP_RV200) || \ 1750254885Sdumbbell (rdev->family == CHIP_RS100) || \ 1751254885Sdumbbell (rdev->family == CHIP_RS200) || \ 1752254885Sdumbbell (rdev->family == CHIP_RV250) || \ 1753254885Sdumbbell (rdev->family == CHIP_RV280) || \ 1754254885Sdumbbell (rdev->family == CHIP_RS300)) 1755254885Sdumbbell#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 1756254885Sdumbbell (rdev->family == CHIP_RV350) || \ 1757254885Sdumbbell (rdev->family == CHIP_R350) || \ 1758254885Sdumbbell (rdev->family == CHIP_RV380) || \ 1759254885Sdumbbell (rdev->family == CHIP_R420) || \ 1760254885Sdumbbell (rdev->family == CHIP_R423) || \ 1761254885Sdumbbell (rdev->family == CHIP_RV410) || \ 1762254885Sdumbbell (rdev->family == CHIP_RS400) || \ 1763254885Sdumbbell (rdev->family == CHIP_RS480)) 1764254885Sdumbbell#define ASIC_IS_X2(rdev) ((rdev->ddev->pci_device == 0x9441) || \ 1765254885Sdumbbell (rdev->ddev->pci_device == 0x9443) || \ 1766254885Sdumbbell (rdev->ddev->pci_device == 0x944B) || \ 1767254885Sdumbbell (rdev->ddev->pci_device == 0x9506) || \ 1768254885Sdumbbell (rdev->ddev->pci_device == 0x9509) || \ 1769254885Sdumbbell (rdev->ddev->pci_device == 0x950F) || \ 1770254885Sdumbbell (rdev->ddev->pci_device == 0x689C) || \ 1771254885Sdumbbell (rdev->ddev->pci_device == 0x689D)) 1772254885Sdumbbell#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 1773254885Sdumbbell#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 1774254885Sdumbbell (rdev->family == CHIP_RS690) || \ 1775254885Sdumbbell (rdev->family == CHIP_RS740) || \ 1776254885Sdumbbell (rdev->family >= CHIP_R600)) 1777254885Sdumbbell#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 1778254885Sdumbbell#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 1779254885Sdumbbell#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 1780254885Sdumbbell#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 1781254885Sdumbbell (rdev->flags & RADEON_IS_IGP)) 1782254885Sdumbbell#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 1783254885Sdumbbell#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 1784254885Sdumbbell#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 1785254885Sdumbbell (rdev->flags & RADEON_IS_IGP)) 1786254885Sdumbbell 1787254885Sdumbbell/* 1788254885Sdumbbell * BIOS helpers. 1789254885Sdumbbell */ 1790254885Sdumbbell#define RBIOS8(i) (rdev->bios[i]) 1791254885Sdumbbell#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1792254885Sdumbbell#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1793254885Sdumbbell 1794254885Sdumbbellint radeon_combios_init(struct radeon_device *rdev); 1795254885Sdumbbellvoid radeon_combios_fini(struct radeon_device *rdev); 1796254885Sdumbbellint radeon_atombios_init(struct radeon_device *rdev); 1797254885Sdumbbellvoid radeon_atombios_fini(struct radeon_device *rdev); 1798254885Sdumbbell 1799254885Sdumbbell 1800254885Sdumbbell/* 1801254885Sdumbbell * RING helpers. 1802254885Sdumbbell */ 1803282199Sdumbbell#if DRM_DEBUG_CODE == 0 1804254885Sdumbbellstatic inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 1805254885Sdumbbell{ 1806254885Sdumbbell ring->ring[ring->wptr++] = v; 1807254885Sdumbbell ring->wptr &= ring->ptr_mask; 1808254885Sdumbbell ring->count_dw--; 1809254885Sdumbbell ring->ring_free_dw--; 1810254885Sdumbbell} 1811254885Sdumbbell#else 1812254885Sdumbbell/* With debugging this is just too big to inline */ 1813254885Sdumbbellvoid radeon_ring_write(struct radeon_ring *ring, uint32_t v); 1814254885Sdumbbell#endif 1815254885Sdumbbell 1816254885Sdumbbell/* 1817254885Sdumbbell * ASICs macro. 1818254885Sdumbbell */ 1819254885Sdumbbell#define radeon_init(rdev) (rdev)->asic->init((rdev)) 1820254885Sdumbbell#define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 1821254885Sdumbbell#define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 1822254885Sdumbbell#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 1823254885Sdumbbell#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) 1824254885Sdumbbell#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 1825254885Sdumbbell#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 1826254885Sdumbbell#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 1827254885Sdumbbell#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) 1828254885Sdumbbell#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 1829254885Sdumbbell#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 1830254885Sdumbbell#define radeon_asic_vm_set_page(rdev, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (pe), (addr), (count), (incr), (flags))) 1831254885Sdumbbell#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) 1832254885Sdumbbell#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) 1833254885Sdumbbell#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) 1834254885Sdumbbell#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) 1835254885Sdumbbell#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) 1836254885Sdumbbell#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) 1837254885Sdumbbell#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm)) 1838254885Sdumbbell#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 1839254885Sdumbbell#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 1840254885Sdumbbell#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 1841254885Sdumbbell#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 1842254885Sdumbbell#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 1843254885Sdumbbell#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) 1844254885Sdumbbell#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 1845254885Sdumbbell#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 1846254885Sdumbbell#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 1847254885Sdumbbell#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 1848254885Sdumbbell#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 1849254885Sdumbbell#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 1850254885Sdumbbell#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 1851254885Sdumbbell#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 1852254885Sdumbbell#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 1853254885Sdumbbell#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 1854254885Sdumbbell#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 1855254885Sdumbbell#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 1856254885Sdumbbell#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 1857254885Sdumbbell#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 1858254885Sdumbbell#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 1859254885Sdumbbell#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 1860254885Sdumbbell#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 1861254885Sdumbbell#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 1862254885Sdumbbell#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 1863254885Sdumbbell#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 1864254885Sdumbbell#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 1865254885Sdumbbell#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 1866254885Sdumbbell#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 1867254885Sdumbbell#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 1868254885Sdumbbell#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 1869254885Sdumbbell#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 1870254885Sdumbbell#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 1871254885Sdumbbell#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) 1872254885Sdumbbell#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 1873254885Sdumbbell#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) 1874254885Sdumbbell#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 1875254885Sdumbbell#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 1876254885Sdumbbell 1877254885Sdumbbell/* Common functions */ 1878254885Sdumbbell/* AGP */ 1879254885Sdumbbellextern int radeon_gpu_reset(struct radeon_device *rdev); 1880254885Sdumbbellextern void radeon_agp_disable(struct radeon_device *rdev); 1881254885Sdumbbellextern int radeon_modeset_init(struct radeon_device *rdev); 1882254885Sdumbbellextern void radeon_modeset_fini(struct radeon_device *rdev); 1883254885Sdumbbellextern bool radeon_card_posted(struct radeon_device *rdev); 1884254885Sdumbbellextern void radeon_update_bandwidth_info(struct radeon_device *rdev); 1885254885Sdumbbellextern void radeon_update_display_priority(struct radeon_device *rdev); 1886254885Sdumbbellextern bool radeon_boot_test_post_card(struct radeon_device *rdev); 1887254885Sdumbbellextern void radeon_scratch_init(struct radeon_device *rdev); 1888254885Sdumbbellextern void radeon_wb_fini(struct radeon_device *rdev); 1889254885Sdumbbellextern int radeon_wb_init(struct radeon_device *rdev); 1890254885Sdumbbellextern void radeon_wb_disable(struct radeon_device *rdev); 1891254885Sdumbbellextern void radeon_surface_init(struct radeon_device *rdev); 1892254885Sdumbbellextern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 1893254885Sdumbbellextern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 1894254885Sdumbbellextern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 1895254885Sdumbbellextern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 1896254885Sdumbbellextern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 1897254885Sdumbbellextern int radeon_resume_kms(struct drm_device *dev); 1898254885Sdumbbellextern int radeon_suspend_kms(struct drm_device *dev); 1899254885Sdumbbellextern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 1900254885Sdumbbell 1901254885Sdumbbell/* 1902254885Sdumbbell * vm 1903254885Sdumbbell */ 1904254885Sdumbbellint radeon_vm_manager_init(struct radeon_device *rdev); 1905254885Sdumbbellvoid radeon_vm_manager_fini(struct radeon_device *rdev); 1906254885Sdumbbellvoid radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 1907254885Sdumbbellvoid radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 1908254885Sdumbbellint radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); 1909254885Sdumbbellvoid radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm); 1910254885Sdumbbellstruct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 1911254885Sdumbbell struct radeon_vm *vm, int ring); 1912254885Sdumbbellvoid radeon_vm_fence(struct radeon_device *rdev, 1913254885Sdumbbell struct radeon_vm *vm, 1914254885Sdumbbell struct radeon_fence *fence); 1915254885Sdumbbelluint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 1916254885Sdumbbellint radeon_vm_bo_update_pte(struct radeon_device *rdev, 1917254885Sdumbbell struct radeon_vm *vm, 1918254885Sdumbbell struct radeon_bo *bo, 1919254885Sdumbbell struct ttm_mem_reg *mem); 1920254885Sdumbbellvoid radeon_vm_bo_invalidate(struct radeon_device *rdev, 1921254885Sdumbbell struct radeon_bo *bo); 1922254885Sdumbbellstruct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 1923254885Sdumbbell struct radeon_bo *bo); 1924254885Sdumbbellstruct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 1925254885Sdumbbell struct radeon_vm *vm, 1926254885Sdumbbell struct radeon_bo *bo); 1927254885Sdumbbellint radeon_vm_bo_set_addr(struct radeon_device *rdev, 1928254885Sdumbbell struct radeon_bo_va *bo_va, 1929254885Sdumbbell uint64_t offset, 1930254885Sdumbbell uint32_t flags); 1931254885Sdumbbellint radeon_vm_bo_rmv(struct radeon_device *rdev, 1932254885Sdumbbell struct radeon_bo_va *bo_va); 1933254885Sdumbbell 1934254885Sdumbbell/* audio */ 1935254885Sdumbbellvoid r600_audio_update_hdmi(void *arg, int pending); 1936254885Sdumbbell 1937254885Sdumbbell/* 1938254885Sdumbbell * R600 vram scratch functions 1939254885Sdumbbell */ 1940254885Sdumbbellint r600_vram_scratch_init(struct radeon_device *rdev); 1941254885Sdumbbellvoid r600_vram_scratch_fini(struct radeon_device *rdev); 1942254885Sdumbbell 1943254885Sdumbbell/* 1944254885Sdumbbell * r600 cs checking helper 1945254885Sdumbbell */ 1946254885Sdumbbellunsigned r600_mip_minify(unsigned size, unsigned level); 1947254885Sdumbbellbool r600_fmt_is_valid_color(u32 format); 1948254885Sdumbbellbool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 1949254885Sdumbbellint r600_fmt_get_blocksize(u32 format); 1950254885Sdumbbellint r600_fmt_get_nblocksx(u32 format, u32 w); 1951254885Sdumbbellint r600_fmt_get_nblocksy(u32 format, u32 h); 1952254885Sdumbbell 1953254885Sdumbbell/* 1954254885Sdumbbell * r600 functions used by radeon_encoder.c 1955254885Sdumbbell */ 1956254885Sdumbbellstruct radeon_hdmi_acr { 1957254885Sdumbbell u32 clock; 1958254885Sdumbbell 1959254885Sdumbbell int n_32khz; 1960254885Sdumbbell int cts_32khz; 1961254885Sdumbbell 1962254885Sdumbbell int n_44_1khz; 1963254885Sdumbbell int cts_44_1khz; 1964254885Sdumbbell 1965254885Sdumbbell int n_48khz; 1966254885Sdumbbell int cts_48khz; 1967254885Sdumbbell 1968254885Sdumbbell}; 1969254885Sdumbbell 1970254885Sdumbbellextern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 1971254885Sdumbbell 1972254885Sdumbbellextern void r600_hdmi_enable(struct drm_encoder *encoder); 1973254885Sdumbbellextern void r600_hdmi_disable(struct drm_encoder *encoder); 1974254885Sdumbbellextern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1975254885Sdumbbellextern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1976254885Sdumbbell u32 tiling_pipe_num, 1977254885Sdumbbell u32 max_rb_num, 1978254885Sdumbbell u32 total_max_rb_num, 1979254885Sdumbbell u32 enabled_rb_mask); 1980254885Sdumbbell 1981254885Sdumbbell/* 1982254885Sdumbbell * evergreen functions used by radeon_encoder.c 1983254885Sdumbbell */ 1984254885Sdumbbell 1985254885Sdumbbellextern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1986254885Sdumbbell 1987254885Sdumbbellextern int ni_init_microcode(struct radeon_device *rdev); 1988254885Sdumbbellextern int ni_mc_load_microcode(struct radeon_device *rdev); 1989254885Sdumbbellextern void ni_fini_microcode(struct radeon_device *rdev); 1990254885Sdumbbell 1991254885Sdumbbell/* radeon_acpi.c */ 1992282199Sdumbbell#if defined(CONFIG_ACPI) 1993254885Sdumbbellextern int radeon_acpi_init(struct radeon_device *rdev); 1994254885Sdumbbellextern void radeon_acpi_fini(struct radeon_device *rdev); 1995282199Sdumbbell#else 1996282199Sdumbbellstatic inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 1997282199Sdumbbellstatic inline void radeon_acpi_fini(struct radeon_device *rdev) { } 1998282199Sdumbbell#endif 1999254885Sdumbbell 2000254885Sdumbbell/* Prototypes added by @dumbbell. */ 2001254885Sdumbbell 2002254885Sdumbbell/* atombios_encoders.c */ 2003254885Sdumbbellvoid radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 2004254885Sdumbbell struct drm_connector *drm_connector); 2005254885Sdumbbellvoid radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 2006254885Sdumbbell uint32_t supported_device, u16 caps); 2007254885Sdumbbell 2008254885Sdumbbell/* radeon_atombios.c */ 2009254885Sdumbbellbool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 2010254885Sdumbbell struct drm_display_mode *mode); 2011254885Sdumbbell 2012254885Sdumbbell/* radeon_combios.c */ 2013254885Sdumbbellvoid radeon_combios_connected_scratch_regs(struct drm_connector *connector, 2014254885Sdumbbell struct drm_encoder *encoder, bool connected); 2015254885Sdumbbell 2016254885Sdumbbell/* radeon_connectors.c */ 2017254885Sdumbbellvoid radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 2018254885Sdumbbell struct drm_encoder *encoder, bool connected); 2019254885Sdumbbellvoid radeon_add_legacy_connector(struct drm_device *dev, 2020254885Sdumbbell uint32_t connector_id, 2021254885Sdumbbell uint32_t supported_device, 2022254885Sdumbbell int connector_type, 2023254885Sdumbbell struct radeon_i2c_bus_rec *i2c_bus, 2024254885Sdumbbell uint16_t connector_object_id, 2025254885Sdumbbell struct radeon_hpd *hpd); 2026254885Sdumbbellvoid radeon_add_atom_connector(struct drm_device *dev, 2027254885Sdumbbell uint32_t connector_id, 2028254885Sdumbbell uint32_t supported_device, 2029254885Sdumbbell int connector_type, 2030254885Sdumbbell struct radeon_i2c_bus_rec *i2c_bus, 2031254885Sdumbbell uint32_t igp_lane_info, 2032254885Sdumbbell uint16_t connector_object_id, 2033254885Sdumbbell struct radeon_hpd *hpd, 2034254885Sdumbbell struct radeon_router *router); 2035254885Sdumbbell 2036254885Sdumbbell/* radeon_encoders.c */ 2037254885Sdumbbelluint32_t radeon_get_encoder_enum(struct drm_device *dev, 2038254885Sdumbbell uint32_t supported_device, uint8_t dac); 2039254885Sdumbbellvoid radeon_link_encoder_connector(struct drm_device *dev); 2040254885Sdumbbell 2041254885Sdumbbell/* radeon_legacy_encoders.c */ 2042254885Sdumbbellvoid radeon_add_legacy_encoder(struct drm_device *dev, 2043254885Sdumbbell uint32_t encoder_enum, uint32_t supported_device); 2044254885Sdumbbellvoid radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 2045254885Sdumbbell struct drm_connector *drm_connector); 2046254885Sdumbbell 2047254885Sdumbbell/* radeon_pm.c */ 2048254885Sdumbbellvoid radeon_pm_acpi_event_handler(struct radeon_device *rdev); 2049254885Sdumbbell 2050254885Sdumbbell/* radeon_ttm.c */ 2051254885Sdumbbellint radeon_ttm_init(struct radeon_device *rdev); 2052254885Sdumbbellvoid radeon_ttm_fini(struct radeon_device *rdev); 2053254885Sdumbbell 2054262861Sjhb/* radeon_fb.c */ 2055262861Sjhbstruct fb_info * radeon_fb_helper_getinfo(device_t kdev); 2056262861Sjhb 2057254885Sdumbbell/* r600.c */ 2058254885Sdumbbellint r600_ih_ring_alloc(struct radeon_device *rdev); 2059254885Sdumbbellvoid r600_ih_ring_fini(struct radeon_device *rdev); 2060254885Sdumbbell 2061254885Sdumbbell#include "radeon_object.h" 2062254885Sdumbbell 2063254885Sdumbbell#endif 2064