1/* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24#ifndef NI_H 25#define NI_H 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#define CAYMAN_MAX_SH_GPRS 256 31#define CAYMAN_MAX_TEMP_GPRS 16 32#define CAYMAN_MAX_SH_THREADS 256 33#define CAYMAN_MAX_SH_STACK_ENTRIES 4096 34#define CAYMAN_MAX_FRC_EOV_CNT 16384 35#define CAYMAN_MAX_BACKENDS 8 36#define CAYMAN_MAX_BACKENDS_MASK 0xFF 37#define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF 38#define CAYMAN_MAX_SIMDS 16 39#define CAYMAN_MAX_SIMDS_MASK 0xFFFF 40#define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF 41#define CAYMAN_MAX_PIPES 8 42#define CAYMAN_MAX_PIPES_MASK 0xFF 43#define CAYMAN_MAX_LDS_NUM 0xFFFF 44#define CAYMAN_MAX_TCC 16 45#define CAYMAN_MAX_TCC_MASK 0xFF 46 47#define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 48#define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001 49 50#define DMIF_ADDR_CONFIG 0xBD4 51 52/* DCE6 only */ 53#define DMIF_ADDR_CALC 0xC00 54 55#define SRBM_GFX_CNTL 0x0E44 56#define RINGID(x) (((x) & 0x3) << 0) 57#define VMID(x) (((x) & 0x7) << 0) 58#define SRBM_STATUS 0x0E50 59 60#define SRBM_SOFT_RESET 0x0E60 61#define SOFT_RESET_BIF (1 << 1) 62#define SOFT_RESET_CG (1 << 2) 63#define SOFT_RESET_DC (1 << 5) 64#define SOFT_RESET_DMA1 (1 << 6) 65#define SOFT_RESET_GRBM (1 << 8) 66#define SOFT_RESET_HDP (1 << 9) 67#define SOFT_RESET_IH (1 << 10) 68#define SOFT_RESET_MC (1 << 11) 69#define SOFT_RESET_RLC (1 << 13) 70#define SOFT_RESET_ROM (1 << 14) 71#define SOFT_RESET_SEM (1 << 15) 72#define SOFT_RESET_VMC (1 << 17) 73#define SOFT_RESET_DMA (1 << 20) 74#define SOFT_RESET_TST (1 << 21) 75#define SOFT_RESET_REGBB (1 << 22) 76#define SOFT_RESET_ORB (1 << 23) 77 78#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 79#define REQUEST_TYPE(x) (((x) & 0xf) << 0) 80#define RESPONSE_TYPE_MASK 0x000000F0 81#define RESPONSE_TYPE_SHIFT 4 82#define VM_L2_CNTL 0x1400 83#define ENABLE_L2_CACHE (1 << 0) 84#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 85#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 86#define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 87#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 88#define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18) 89/* CONTEXT1_IDENTITY_ACCESS_MODE 90 * 0 physical = logical 91 * 1 logical via context1 page table 92 * 2 inside identity aperture use translation, outside physical = logical 93 * 3 inside identity aperture physical = logical, outside use translation 94 */ 95#define VM_L2_CNTL2 0x1404 96#define INVALIDATE_ALL_L1_TLBS (1 << 0) 97#define INVALIDATE_L2_CACHE (1 << 1) 98#define VM_L2_CNTL3 0x1408 99#define BANK_SELECT(x) ((x) << 0) 100#define CACHE_UPDATE_MODE(x) ((x) << 6) 101#define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 102#define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 103#define VM_L2_STATUS 0x140C 104#define L2_BUSY (1 << 0) 105#define VM_CONTEXT0_CNTL 0x1410 106#define ENABLE_CONTEXT (1 << 0) 107#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 108#define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 109#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 110#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 111#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 112#define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 113#define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 114#define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 115#define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 116#define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 117#define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 118#define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 119#define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 120#define VM_CONTEXT1_CNTL 0x1414 121#define VM_CONTEXT0_CNTL2 0x1430 122#define VM_CONTEXT1_CNTL2 0x1434 123#define VM_INVALIDATE_REQUEST 0x1478 124#define VM_INVALIDATE_RESPONSE 0x147c 125#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 126#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 127#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 128#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 129#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 130 131#define MC_SHARED_CHMAP 0x2004 132#define NOOFCHAN_SHIFT 12 133#define NOOFCHAN_MASK 0x00003000 134#define MC_SHARED_CHREMAP 0x2008 135 136#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 137#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 138#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 139#define MC_VM_MX_L1_TLB_CNTL 0x2064 140#define ENABLE_L1_TLB (1 << 0) 141#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 142#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 143#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 144#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 145#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 146#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 147#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 148#define FUS_MC_VM_FB_OFFSET 0x2068 149 150#define MC_SHARED_BLACKOUT_CNTL 0x20ac 151#define MC_ARB_RAMCFG 0x2760 152#define NOOFBANK_SHIFT 0 153#define NOOFBANK_MASK 0x00000003 154#define NOOFRANK_SHIFT 2 155#define NOOFRANK_MASK 0x00000004 156#define NOOFROWS_SHIFT 3 157#define NOOFROWS_MASK 0x00000038 158#define NOOFCOLS_SHIFT 6 159#define NOOFCOLS_MASK 0x000000C0 160#define CHANSIZE_SHIFT 8 161#define CHANSIZE_MASK 0x00000100 162#define BURSTLENGTH_SHIFT 9 163#define BURSTLENGTH_MASK 0x00000200 164#define CHANSIZE_OVERRIDE (1 << 11) 165#define MC_SEQ_SUP_CNTL 0x28c8 166#define RUN_MASK (1 << 0) 167#define MC_SEQ_SUP_PGM 0x28cc 168#define MC_IO_PAD_CNTL_D0 0x29d0 169#define MEM_FALL_OUT_CMD (1 << 8) 170#define MC_SEQ_MISC0 0x2a00 171#define MC_SEQ_MISC0_GDDR5_SHIFT 28 172#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 173#define MC_SEQ_MISC0_GDDR5_VALUE 5 174#define MC_SEQ_IO_DEBUG_INDEX 0x2a44 175#define MC_SEQ_IO_DEBUG_DATA 0x2a48 176 177#define HDP_HOST_PATH_CNTL 0x2C00 178#define HDP_NONSURFACE_BASE 0x2C04 179#define HDP_NONSURFACE_INFO 0x2C08 180#define HDP_NONSURFACE_SIZE 0x2C0C 181#define HDP_ADDR_CONFIG 0x2F48 182#define HDP_MISC_CNTL 0x2F4C 183#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 184 185#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 186#define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C 187#define CGTS_SYS_TCC_DISABLE 0x3F90 188#define CGTS_USER_SYS_TCC_DISABLE 0x3F94 189 190#define RLC_GFX_INDEX 0x3FC4 191 192#define CONFIG_MEMSIZE 0x5428 193 194#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 195#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 196 197#define GRBM_CNTL 0x8000 198#define GRBM_READ_TIMEOUT(x) ((x) << 0) 199#define GRBM_STATUS 0x8010 200#define CMDFIFO_AVAIL_MASK 0x0000000F 201#define RING2_RQ_PENDING (1 << 4) 202#define SRBM_RQ_PENDING (1 << 5) 203#define RING1_RQ_PENDING (1 << 6) 204#define CF_RQ_PENDING (1 << 7) 205#define PF_RQ_PENDING (1 << 8) 206#define GDS_DMA_RQ_PENDING (1 << 9) 207#define GRBM_EE_BUSY (1 << 10) 208#define SX_CLEAN (1 << 11) 209#define DB_CLEAN (1 << 12) 210#define CB_CLEAN (1 << 13) 211#define TA_BUSY (1 << 14) 212#define GDS_BUSY (1 << 15) 213#define VGT_BUSY_NO_DMA (1 << 16) 214#define VGT_BUSY (1 << 17) 215#define IA_BUSY_NO_DMA (1 << 18) 216#define IA_BUSY (1 << 19) 217#define SX_BUSY (1 << 20) 218#define SH_BUSY (1 << 21) 219#define SPI_BUSY (1 << 22) 220#define SC_BUSY (1 << 24) 221#define PA_BUSY (1 << 25) 222#define DB_BUSY (1 << 26) 223#define CP_COHERENCY_BUSY (1 << 28) 224#define CP_BUSY (1 << 29) 225#define CB_BUSY (1 << 30) 226#define GUI_ACTIVE (1U << 31) 227#define GRBM_STATUS_SE0 0x8014 228#define GRBM_STATUS_SE1 0x8018 229#define SE_SX_CLEAN (1 << 0) 230#define SE_DB_CLEAN (1 << 1) 231#define SE_CB_CLEAN (1 << 2) 232#define SE_VGT_BUSY (1 << 23) 233#define SE_PA_BUSY (1 << 24) 234#define SE_TA_BUSY (1 << 25) 235#define SE_SX_BUSY (1 << 26) 236#define SE_SPI_BUSY (1 << 27) 237#define SE_SH_BUSY (1 << 28) 238#define SE_SC_BUSY (1 << 29) 239#define SE_DB_BUSY (1 << 30) 240#define SE_CB_BUSY (1U << 31) 241#define GRBM_SOFT_RESET 0x8020 242#define SOFT_RESET_CP (1 << 0) 243#define SOFT_RESET_CB (1 << 1) 244#define SOFT_RESET_DB (1 << 3) 245#define SOFT_RESET_GDS (1 << 4) 246#define SOFT_RESET_PA (1 << 5) 247#define SOFT_RESET_SC (1 << 6) 248#define SOFT_RESET_SPI (1 << 8) 249#define SOFT_RESET_SH (1 << 9) 250#define SOFT_RESET_SX (1 << 10) 251#define SOFT_RESET_TC (1 << 11) 252#define SOFT_RESET_TA (1 << 12) 253#define SOFT_RESET_VGT (1 << 14) 254#define SOFT_RESET_IA (1 << 15) 255 256#define GRBM_GFX_INDEX 0x802C 257#define INSTANCE_INDEX(x) ((x) << 0) 258#define SE_INDEX(x) ((x) << 16) 259#define INSTANCE_BROADCAST_WRITES (1 << 30) 260#define SE_BROADCAST_WRITES (1U << 31) 261 262#define SCRATCH_REG0 0x8500 263#define SCRATCH_REG1 0x8504 264#define SCRATCH_REG2 0x8508 265#define SCRATCH_REG3 0x850C 266#define SCRATCH_REG4 0x8510 267#define SCRATCH_REG5 0x8514 268#define SCRATCH_REG6 0x8518 269#define SCRATCH_REG7 0x851C 270#define SCRATCH_UMSK 0x8540 271#define SCRATCH_ADDR 0x8544 272#define CP_SEM_WAIT_TIMER 0x85BC 273#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 274#define CP_COHER_CNTL2 0x85E8 275#define CP_STALLED_STAT1 0x8674 276#define CP_STALLED_STAT2 0x8678 277#define CP_BUSY_STAT 0x867C 278#define CP_STAT 0x8680 279#define CP_ME_CNTL 0x86D8 280#define CP_ME_HALT (1 << 28) 281#define CP_PFP_HALT (1 << 26) 282#define CP_RB2_RPTR 0x86f8 283#define CP_RB1_RPTR 0x86fc 284#define CP_RB0_RPTR 0x8700 285#define CP_RB_WPTR_DELAY 0x8704 286#define CP_MEQ_THRESHOLDS 0x8764 287#define MEQ1_START(x) ((x) << 0) 288#define MEQ2_START(x) ((x) << 8) 289#define CP_PERFMON_CNTL 0x87FC 290 291#define VGT_CACHE_INVALIDATION 0x88C4 292#define CACHE_INVALIDATION(x) ((x) << 0) 293#define VC_ONLY 0 294#define TC_ONLY 1 295#define VC_AND_TC 2 296#define AUTO_INVLD_EN(x) ((x) << 6) 297#define NO_AUTO 0 298#define ES_AUTO 1 299#define GS_AUTO 2 300#define ES_AND_GS_AUTO 3 301#define VGT_GS_VERTEX_REUSE 0x88D4 302 303#define CC_GC_SHADER_PIPE_CONFIG 0x8950 304#define GC_USER_SHADER_PIPE_CONFIG 0x8954 305#define INACTIVE_QD_PIPES(x) ((x) << 8) 306#define INACTIVE_QD_PIPES_MASK 0x0000FF00 307#define INACTIVE_QD_PIPES_SHIFT 8 308#define INACTIVE_SIMDS(x) ((x) << 16) 309#define INACTIVE_SIMDS_MASK 0xFFFF0000 310#define INACTIVE_SIMDS_SHIFT 16 311 312#define VGT_PRIMITIVE_TYPE 0x8958 313#define VGT_NUM_INSTANCES 0x8974 314#define VGT_TF_RING_SIZE 0x8988 315#define VGT_OFFCHIP_LDS_BASE 0x89b4 316 317#define PA_SC_LINE_STIPPLE_STATE 0x8B10 318#define PA_CL_ENHANCE 0x8A14 319#define CLIP_VTX_REORDER_ENA (1 << 0) 320#define NUM_CLIP_SEQ(x) ((x) << 1) 321#define PA_SC_FIFO_SIZE 0x8BCC 322#define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 323#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 324#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 325#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 326#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 327#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 328 329#define SQ_CONFIG 0x8C00 330#define VC_ENABLE (1 << 0) 331#define EXPORT_SRC_C (1 << 1) 332#define GFX_PRIO(x) ((x) << 2) 333#define CS1_PRIO(x) ((x) << 4) 334#define CS2_PRIO(x) ((x) << 6) 335#define SQ_GPR_RESOURCE_MGMT_1 0x8C04 336#define NUM_PS_GPRS(x) ((x) << 0) 337#define NUM_VS_GPRS(x) ((x) << 16) 338#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 339#define SQ_ESGS_RING_SIZE 0x8c44 340#define SQ_GSVS_RING_SIZE 0x8c4c 341#define SQ_ESTMP_RING_BASE 0x8c50 342#define SQ_ESTMP_RING_SIZE 0x8c54 343#define SQ_GSTMP_RING_BASE 0x8c58 344#define SQ_GSTMP_RING_SIZE 0x8c5c 345#define SQ_VSTMP_RING_BASE 0x8c60 346#define SQ_VSTMP_RING_SIZE 0x8c64 347#define SQ_PSTMP_RING_BASE 0x8c68 348#define SQ_PSTMP_RING_SIZE 0x8c6c 349#define SQ_MS_FIFO_SIZES 0x8CF0 350#define CACHE_FIFO_SIZE(x) ((x) << 0) 351#define FETCH_FIFO_HIWATER(x) ((x) << 8) 352#define DONE_FIFO_HIWATER(x) ((x) << 16) 353#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 354#define SQ_LSTMP_RING_BASE 0x8e10 355#define SQ_LSTMP_RING_SIZE 0x8e14 356#define SQ_HSTMP_RING_BASE 0x8e18 357#define SQ_HSTMP_RING_SIZE 0x8e1c 358#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 359#define DYN_GPR_ENABLE (1 << 8) 360#define SQ_CONST_MEM_BASE 0x8df8 361 362#define SX_EXPORT_BUFFER_SIZES 0x900C 363#define COLOR_BUFFER_SIZE(x) ((x) << 0) 364#define POSITION_BUFFER_SIZE(x) ((x) << 8) 365#define SMX_BUFFER_SIZE(x) ((x) << 16) 366#define SX_DEBUG_1 0x9058 367#define ENABLE_NEW_SMX_ADDRESS (1 << 16) 368 369#define SPI_CONFIG_CNTL 0x9100 370#define GPR_WRITE_PRIORITY(x) ((x) << 0) 371#define SPI_CONFIG_CNTL_1 0x913C 372#define VTX_DONE_DELAY(x) ((x) << 0) 373#define INTERP_ONE_PRIM_PER_ROW (1 << 4) 374#define CRC_SIMD_ID_WADDR_DISABLE (1 << 8) 375 376#define CGTS_TCC_DISABLE 0x9148 377#define CGTS_USER_TCC_DISABLE 0x914C 378#define TCC_DISABLE_MASK 0xFFFF0000 379#define TCC_DISABLE_SHIFT 16 380#define CGTS_SM_CTRL_REG 0x9150 381#define OVERRIDE (1 << 21) 382 383#define TA_CNTL_AUX 0x9508 384#define DISABLE_CUBE_WRAP (1 << 0) 385#define DISABLE_CUBE_ANISO (1 << 1) 386 387#define TCP_CHAN_STEER_LO 0x960c 388#define TCP_CHAN_STEER_HI 0x9610 389 390#define CC_RB_BACKEND_DISABLE 0x98F4 391#define BACKEND_DISABLE(x) ((x) << 16) 392#define GB_ADDR_CONFIG 0x98F8 393#define NUM_PIPES(x) ((x) << 0) 394#define NUM_PIPES_MASK 0x00000007 395#define NUM_PIPES_SHIFT 0 396#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 397#define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 398#define PIPE_INTERLEAVE_SIZE_SHIFT 4 399#define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 400#define NUM_SHADER_ENGINES(x) ((x) << 12) 401#define NUM_SHADER_ENGINES_MASK 0x00003000 402#define NUM_SHADER_ENGINES_SHIFT 12 403#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 404#define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 405#define SHADER_ENGINE_TILE_SIZE_SHIFT 16 406#define NUM_GPUS(x) ((x) << 20) 407#define NUM_GPUS_MASK 0x00700000 408#define NUM_GPUS_SHIFT 20 409#define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 410#define MULTI_GPU_TILE_SIZE_MASK 0x03000000 411#define MULTI_GPU_TILE_SIZE_SHIFT 24 412#define ROW_SIZE(x) ((x) << 28) 413#define ROW_SIZE_MASK 0x30000000 414#define ROW_SIZE_SHIFT 28 415#define NUM_LOWER_PIPES(x) ((x) << 30) 416#define NUM_LOWER_PIPES_MASK 0x40000000 417#define NUM_LOWER_PIPES_SHIFT 30 418#define GB_BACKEND_MAP 0x98FC 419 420#define CB_PERF_CTR0_SEL_0 0x9A20 421#define CB_PERF_CTR0_SEL_1 0x9A24 422#define CB_PERF_CTR1_SEL_0 0x9A28 423#define CB_PERF_CTR1_SEL_1 0x9A2C 424#define CB_PERF_CTR2_SEL_0 0x9A30 425#define CB_PERF_CTR2_SEL_1 0x9A34 426#define CB_PERF_CTR3_SEL_0 0x9A38 427#define CB_PERF_CTR3_SEL_1 0x9A3C 428 429#define GC_USER_RB_BACKEND_DISABLE 0x9B7C 430#define BACKEND_DISABLE_MASK 0x00FF0000 431#define BACKEND_DISABLE_SHIFT 16 432 433#define SMX_DC_CTL0 0xA020 434#define USE_HASH_FUNCTION (1 << 0) 435#define NUMBER_OF_SETS(x) ((x) << 1) 436#define FLUSH_ALL_ON_EVENT (1 << 10) 437#define STALL_ON_EVENT (1 << 11) 438#define SMX_EVENT_CTL 0xA02C 439#define ES_FLUSH_CTL(x) ((x) << 0) 440#define GS_FLUSH_CTL(x) ((x) << 3) 441#define ACK_FLUSH_CTL(x) ((x) << 6) 442#define SYNC_FLUSH_CTL (1 << 8) 443 444#define CP_RB0_BASE 0xC100 445#define CP_RB0_CNTL 0xC104 446#define RB_BUFSZ(x) ((x) << 0) 447#define RB_BLKSZ(x) ((x) << 8) 448#define RB_NO_UPDATE (1 << 27) 449#define RB_RPTR_WR_ENA (1U << 31) 450#define BUF_SWAP_32BIT (2 << 16) 451#define CP_RB0_RPTR_ADDR 0xC10C 452#define CP_RB0_RPTR_ADDR_HI 0xC110 453#define CP_RB0_WPTR 0xC114 454 455#define CP_INT_CNTL 0xC124 456# define CNTX_BUSY_INT_ENABLE (1 << 19) 457# define CNTX_EMPTY_INT_ENABLE (1 << 20) 458# define TIME_STAMP_INT_ENABLE (1 << 26) 459 460#define CP_RB1_BASE 0xC180 461#define CP_RB1_CNTL 0xC184 462#define CP_RB1_RPTR_ADDR 0xC188 463#define CP_RB1_RPTR_ADDR_HI 0xC18C 464#define CP_RB1_WPTR 0xC190 465#define CP_RB2_BASE 0xC194 466#define CP_RB2_CNTL 0xC198 467#define CP_RB2_RPTR_ADDR 0xC19C 468#define CP_RB2_RPTR_ADDR_HI 0xC1A0 469#define CP_RB2_WPTR 0xC1A4 470#define CP_PFP_UCODE_ADDR 0xC150 471#define CP_PFP_UCODE_DATA 0xC154 472#define CP_ME_RAM_RADDR 0xC158 473#define CP_ME_RAM_WADDR 0xC15C 474#define CP_ME_RAM_DATA 0xC160 475#define CP_DEBUG 0xC1FC 476 477#define VGT_EVENT_INITIATOR 0x28a90 478# define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) 479# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 480 481/* 482 * PM4 483 */ 484#define PACKET_TYPE0 0 485#define PACKET_TYPE1 1 486#define PACKET_TYPE2 2 487#define PACKET_TYPE3 3 488 489#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 490#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 491#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 492#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 493#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 494 (((reg) >> 2) & 0xFFFF) | \ 495 ((n) & 0x3FFF) << 16) 496#define CP_PACKET2 0x80000000 497#define PACKET2_PAD_SHIFT 0 498#define PACKET2_PAD_MASK (0x3fffffff << 0) 499 500#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 501 502#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 503 (((op) & 0xFF) << 8) | \ 504 ((n) & 0x3FFF) << 16) 505 506/* Packet 3 types */ 507#define PACKET3_NOP 0x10 508#define PACKET3_SET_BASE 0x11 509#define PACKET3_CLEAR_STATE 0x12 510#define PACKET3_INDEX_BUFFER_SIZE 0x13 511#define PACKET3_DEALLOC_STATE 0x14 512#define PACKET3_DISPATCH_DIRECT 0x15 513#define PACKET3_DISPATCH_INDIRECT 0x16 514#define PACKET3_INDIRECT_BUFFER_END 0x17 515#define PACKET3_MODE_CONTROL 0x18 516#define PACKET3_SET_PREDICATION 0x20 517#define PACKET3_REG_RMW 0x21 518#define PACKET3_COND_EXEC 0x22 519#define PACKET3_PRED_EXEC 0x23 520#define PACKET3_DRAW_INDIRECT 0x24 521#define PACKET3_DRAW_INDEX_INDIRECT 0x25 522#define PACKET3_INDEX_BASE 0x26 523#define PACKET3_DRAW_INDEX_2 0x27 524#define PACKET3_CONTEXT_CONTROL 0x28 525#define PACKET3_DRAW_INDEX_OFFSET 0x29 526#define PACKET3_INDEX_TYPE 0x2A 527#define PACKET3_DRAW_INDEX 0x2B 528#define PACKET3_DRAW_INDEX_AUTO 0x2D 529#define PACKET3_DRAW_INDEX_IMMD 0x2E 530#define PACKET3_NUM_INSTANCES 0x2F 531#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 532#define PACKET3_INDIRECT_BUFFER 0x32 533#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 534#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 535#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 536#define PACKET3_WRITE_DATA 0x37 537#define PACKET3_MEM_SEMAPHORE 0x39 538#define PACKET3_MPEG_INDEX 0x3A 539#define PACKET3_WAIT_REG_MEM 0x3C 540#define PACKET3_MEM_WRITE 0x3D 541#define PACKET3_PFP_SYNC_ME 0x42 542#define PACKET3_SURFACE_SYNC 0x43 543# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 544# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 545# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 546# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 547# define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 548# define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 549# define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 550# define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 551# define PACKET3_DB_DEST_BASE_ENA (1 << 14) 552# define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 553# define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 554# define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 555# define PACKET3_CB11_DEST_BASE_ENA (1 << 18) 556# define PACKET3_FULL_CACHE_ENA (1 << 20) 557# define PACKET3_TC_ACTION_ENA (1 << 23) 558# define PACKET3_CB_ACTION_ENA (1 << 25) 559# define PACKET3_DB_ACTION_ENA (1 << 26) 560# define PACKET3_SH_ACTION_ENA (1 << 27) 561# define PACKET3_SX_ACTION_ENA (1 << 28) 562#define PACKET3_ME_INITIALIZE 0x44 563#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 564#define PACKET3_COND_WRITE 0x45 565#define PACKET3_EVENT_WRITE 0x46 566#define EVENT_TYPE(x) ((x) << 0) 567#define EVENT_INDEX(x) ((x) << 8) 568 /* 0 - any non-TS event 569 * 1 - ZPASS_DONE 570 * 2 - SAMPLE_PIPELINESTAT 571 * 3 - SAMPLE_STREAMOUTSTAT* 572 * 4 - *S_PARTIAL_FLUSH 573 * 5 - TS events 574 */ 575#define PACKET3_EVENT_WRITE_EOP 0x47 576#define DATA_SEL(x) ((x) << 29) 577 /* 0 - discard 578 * 1 - send low 32bit data 579 * 2 - send 64bit data 580 * 3 - send 64bit counter value 581 */ 582#define INT_SEL(x) ((x) << 24) 583 /* 0 - none 584 * 1 - interrupt only (DATA_SEL = 0) 585 * 2 - interrupt when data write is confirmed 586 */ 587#define PACKET3_EVENT_WRITE_EOS 0x48 588#define PACKET3_PREAMBLE_CNTL 0x4A 589# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 590# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 591#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 592#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 593#define PACKET3_ALU_PS_CONST_UPDATE 0x4E 594#define PACKET3_ALU_VS_CONST_UPDATE 0x4F 595#define PACKET3_ONE_REG_WRITE 0x57 596#define PACKET3_SET_CONFIG_REG 0x68 597#define PACKET3_SET_CONFIG_REG_START 0x00008000 598#define PACKET3_SET_CONFIG_REG_END 0x0000ac00 599#define PACKET3_SET_CONTEXT_REG 0x69 600#define PACKET3_SET_CONTEXT_REG_START 0x00028000 601#define PACKET3_SET_CONTEXT_REG_END 0x00029000 602#define PACKET3_SET_ALU_CONST 0x6A 603/* alu const buffers only; no reg file */ 604#define PACKET3_SET_BOOL_CONST 0x6B 605#define PACKET3_SET_BOOL_CONST_START 0x0003a500 606#define PACKET3_SET_BOOL_CONST_END 0x0003a518 607#define PACKET3_SET_LOOP_CONST 0x6C 608#define PACKET3_SET_LOOP_CONST_START 0x0003a200 609#define PACKET3_SET_LOOP_CONST_END 0x0003a500 610#define PACKET3_SET_RESOURCE 0x6D 611#define PACKET3_SET_RESOURCE_START 0x00030000 612#define PACKET3_SET_RESOURCE_END 0x00038000 613#define PACKET3_SET_SAMPLER 0x6E 614#define PACKET3_SET_SAMPLER_START 0x0003c000 615#define PACKET3_SET_SAMPLER_END 0x0003c600 616#define PACKET3_SET_CTL_CONST 0x6F 617#define PACKET3_SET_CTL_CONST_START 0x0003cff0 618#define PACKET3_SET_CTL_CONST_END 0x0003ff0c 619#define PACKET3_SET_RESOURCE_OFFSET 0x70 620#define PACKET3_SET_ALU_CONST_VS 0x71 621#define PACKET3_SET_ALU_CONST_DI 0x72 622#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 623#define PACKET3_SET_RESOURCE_INDIRECT 0x74 624#define PACKET3_SET_APPEND_CNT 0x75 625#define PACKET3_ME_WRITE 0x7A 626 627/* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 628#define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 629#define DMA1_REGISTER_OFFSET 0x800 /* not a register */ 630 631#define DMA_RB_CNTL 0xd000 632# define DMA_RB_ENABLE (1 << 0) 633# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 634# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 635# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 636# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 637# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 638#define DMA_RB_BASE 0xd004 639#define DMA_RB_RPTR 0xd008 640#define DMA_RB_WPTR 0xd00c 641 642#define DMA_RB_RPTR_ADDR_HI 0xd01c 643#define DMA_RB_RPTR_ADDR_LO 0xd020 644 645#define DMA_IB_CNTL 0xd024 646# define DMA_IB_ENABLE (1 << 0) 647# define DMA_IB_SWAP_ENABLE (1 << 4) 648# define CMD_VMID_FORCE (1U << 31) 649#define DMA_IB_RPTR 0xd028 650#define DMA_CNTL 0xd02c 651# define TRAP_ENABLE (1 << 0) 652# define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 653# define SEM_WAIT_INT_ENABLE (1 << 2) 654# define DATA_SWAP_ENABLE (1 << 3) 655# define FENCE_SWAP_ENABLE (1 << 4) 656# define CTXEMPTY_INT_ENABLE (1 << 28) 657#define DMA_STATUS_REG 0xd034 658# define DMA_IDLE (1 << 0) 659#define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044 660#define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048 661#define DMA_TILING_CONFIG 0xd0b8 662#define DMA_MODE 0xd0bc 663 664#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 665 (((t) & 0x1) << 23) | \ 666 (((s) & 0x1) << 22) | \ 667 (((n) & 0xFFFFF) << 0)) 668 669#define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 670 (((vmid) & 0xF) << 20) | \ 671 (((n) & 0xFFFFF) << 0)) 672 673/* async DMA Packet types */ 674#define DMA_PACKET_WRITE 0x2 675#define DMA_PACKET_COPY 0x3 676#define DMA_PACKET_INDIRECT_BUFFER 0x4 677#define DMA_PACKET_SEMAPHORE 0x5 678#define DMA_PACKET_FENCE 0x6 679#define DMA_PACKET_TRAP 0x7 680#define DMA_PACKET_SRBM_WRITE 0x9 681#define DMA_PACKET_CONSTANT_FILL 0xd 682#define DMA_PACKET_NOP 0xf 683 684#endif 685