1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2008 Advanced Micro Devices, Inc. 3254885Sdumbbell * Copyright 2008 Red Hat Inc. 4254885Sdumbbell * Copyright 2009 Jerome Glisse. 5254885Sdumbbell * 6254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 7254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 8254885Sdumbbell * to deal in the Software without restriction, including without limitation 9254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 11254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 12254885Sdumbbell * 13254885Sdumbbell * The above copyright notice and this permission notice shall be included in 14254885Sdumbbell * all copies or substantial portions of the Software. 15254885Sdumbbell * 16254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19254885Sdumbbell * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22254885Sdumbbell * OTHER DEALINGS IN THE SOFTWARE. 23254885Sdumbbell * 24254885Sdumbbell * Authors: Dave Airlie 25254885Sdumbbell * Alex Deucher 26254885Sdumbbell * Jerome Glisse 27254885Sdumbbell */ 28254885Sdumbbell 29254885Sdumbbell#include <sys/cdefs.h> 30254885Sdumbbell__FBSDID("$FreeBSD$"); 31254885Sdumbbell 32254885Sdumbbell#include <dev/drm2/drmP.h> 33254885Sdumbbell#include "radeon.h" 34254885Sdumbbell#include "radeon_asic.h" 35254885Sdumbbell#include "rs400d.h" 36254885Sdumbbell 37254885Sdumbbell/* This files gather functions specifics to : rs400,rs480 */ 38254885Sdumbbellstatic int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 39254885Sdumbbell 40254885Sdumbbellvoid rs400_gart_adjust_size(struct radeon_device *rdev) 41254885Sdumbbell{ 42254885Sdumbbell /* Check gart size */ 43254885Sdumbbell switch (rdev->mc.gtt_size/(1024*1024)) { 44254885Sdumbbell case 32: 45254885Sdumbbell case 64: 46254885Sdumbbell case 128: 47254885Sdumbbell case 256: 48254885Sdumbbell case 512: 49254885Sdumbbell case 1024: 50254885Sdumbbell case 2048: 51254885Sdumbbell break; 52254885Sdumbbell default: 53254885Sdumbbell DRM_ERROR("Unable to use IGP GART size %uM\n", 54254885Sdumbbell (unsigned)(rdev->mc.gtt_size >> 20)); 55254885Sdumbbell DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); 56254885Sdumbbell DRM_ERROR("Forcing to 32M GART size\n"); 57254885Sdumbbell rdev->mc.gtt_size = 32 * 1024 * 1024; 58254885Sdumbbell return; 59254885Sdumbbell } 60254885Sdumbbell} 61254885Sdumbbell 62254885Sdumbbellvoid rs400_gart_tlb_flush(struct radeon_device *rdev) 63254885Sdumbbell{ 64254885Sdumbbell uint32_t tmp; 65254885Sdumbbell unsigned int timeout = rdev->usec_timeout; 66254885Sdumbbell 67254885Sdumbbell WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); 68254885Sdumbbell do { 69254885Sdumbbell tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 70254885Sdumbbell if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) 71254885Sdumbbell break; 72254885Sdumbbell DRM_UDELAY(1); 73254885Sdumbbell timeout--; 74254885Sdumbbell } while (timeout > 0); 75254885Sdumbbell WREG32_MC(RS480_GART_CACHE_CNTRL, 0); 76254885Sdumbbell} 77254885Sdumbbell 78254885Sdumbbellint rs400_gart_init(struct radeon_device *rdev) 79254885Sdumbbell{ 80254885Sdumbbell int r; 81254885Sdumbbell 82254885Sdumbbell if (rdev->gart.ptr) { 83254885Sdumbbell DRM_ERROR("RS400 GART already initialized\n"); 84254885Sdumbbell return 0; 85254885Sdumbbell } 86254885Sdumbbell /* Check gart size */ 87254885Sdumbbell switch(rdev->mc.gtt_size / (1024 * 1024)) { 88254885Sdumbbell case 32: 89254885Sdumbbell case 64: 90254885Sdumbbell case 128: 91254885Sdumbbell case 256: 92254885Sdumbbell case 512: 93254885Sdumbbell case 1024: 94254885Sdumbbell case 2048: 95254885Sdumbbell break; 96254885Sdumbbell default: 97254885Sdumbbell return -EINVAL; 98254885Sdumbbell } 99254885Sdumbbell /* Initialize common gart structure */ 100254885Sdumbbell r = radeon_gart_init(rdev); 101254885Sdumbbell if (r) 102254885Sdumbbell return r; 103254885Sdumbbell if (rs400_debugfs_pcie_gart_info_init(rdev)) 104254885Sdumbbell DRM_ERROR("Failed to register debugfs file for RS400 GART !\n"); 105254885Sdumbbell rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 106254885Sdumbbell return radeon_gart_table_ram_alloc(rdev); 107254885Sdumbbell} 108254885Sdumbbell 109254885Sdumbbellint rs400_gart_enable(struct radeon_device *rdev) 110254885Sdumbbell{ 111254885Sdumbbell uint32_t size_reg; 112254885Sdumbbell uint32_t tmp; 113254885Sdumbbell 114254885Sdumbbell radeon_gart_restore(rdev); 115254885Sdumbbell tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 116254885Sdumbbell tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 117254885Sdumbbell WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 118254885Sdumbbell /* Check gart size */ 119254885Sdumbbell switch(rdev->mc.gtt_size / (1024 * 1024)) { 120254885Sdumbbell case 32: 121254885Sdumbbell size_reg = RS480_VA_SIZE_32MB; 122254885Sdumbbell break; 123254885Sdumbbell case 64: 124254885Sdumbbell size_reg = RS480_VA_SIZE_64MB; 125254885Sdumbbell break; 126254885Sdumbbell case 128: 127254885Sdumbbell size_reg = RS480_VA_SIZE_128MB; 128254885Sdumbbell break; 129254885Sdumbbell case 256: 130254885Sdumbbell size_reg = RS480_VA_SIZE_256MB; 131254885Sdumbbell break; 132254885Sdumbbell case 512: 133254885Sdumbbell size_reg = RS480_VA_SIZE_512MB; 134254885Sdumbbell break; 135254885Sdumbbell case 1024: 136254885Sdumbbell size_reg = RS480_VA_SIZE_1GB; 137254885Sdumbbell break; 138254885Sdumbbell case 2048: 139254885Sdumbbell size_reg = RS480_VA_SIZE_2GB; 140254885Sdumbbell break; 141254885Sdumbbell default: 142254885Sdumbbell return -EINVAL; 143254885Sdumbbell } 144254885Sdumbbell /* It should be fine to program it to max value */ 145254885Sdumbbell if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 146254885Sdumbbell WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); 147254885Sdumbbell WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0); 148254885Sdumbbell } else { 149254885Sdumbbell WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); 150254885Sdumbbell WREG32(RS480_AGP_BASE_2, 0); 151254885Sdumbbell } 152254885Sdumbbell tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); 153254885Sdumbbell tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); 154254885Sdumbbell if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 155254885Sdumbbell WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); 156254885Sdumbbell tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 157254885Sdumbbell WREG32(RADEON_BUS_CNTL, tmp); 158254885Sdumbbell } else { 159254885Sdumbbell WREG32(RADEON_MC_AGP_LOCATION, tmp); 160254885Sdumbbell tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 161254885Sdumbbell WREG32(RADEON_BUS_CNTL, tmp); 162254885Sdumbbell } 163254885Sdumbbell /* Table should be in 32bits address space so ignore bits above. */ 164254885Sdumbbell tmp = (u32)rdev->gart.table_addr & 0xfffff000; 165254885Sdumbbell tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; 166254885Sdumbbell 167254885Sdumbbell WREG32_MC(RS480_GART_BASE, tmp); 168254885Sdumbbell /* TODO: more tweaking here */ 169254885Sdumbbell WREG32_MC(RS480_GART_FEATURE_ID, 170254885Sdumbbell (RS480_TLB_ENABLE | 171254885Sdumbbell RS480_GTW_LAC_EN | RS480_1LEVEL_GART)); 172254885Sdumbbell /* Disable snooping */ 173254885Sdumbbell WREG32_MC(RS480_AGP_MODE_CNTL, 174254885Sdumbbell (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS); 175254885Sdumbbell /* Disable AGP mode */ 176282199Sdumbbell /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0, 177282199Sdumbbell * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */ 178254885Sdumbbell if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 179254885Sdumbbell WREG32_MC(RS480_MC_MISC_CNTL, 180254885Sdumbbell (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN)); 181254885Sdumbbell } else { 182254885Sdumbbell WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); 183254885Sdumbbell } 184254885Sdumbbell /* Enable gart */ 185254885Sdumbbell WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); 186254885Sdumbbell rs400_gart_tlb_flush(rdev); 187254885Sdumbbell DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 188254885Sdumbbell (unsigned)(rdev->mc.gtt_size >> 20), 189254885Sdumbbell (unsigned long long)rdev->gart.table_addr); 190254885Sdumbbell rdev->gart.ready = true; 191254885Sdumbbell return 0; 192254885Sdumbbell} 193254885Sdumbbell 194254885Sdumbbellvoid rs400_gart_disable(struct radeon_device *rdev) 195254885Sdumbbell{ 196254885Sdumbbell uint32_t tmp; 197254885Sdumbbell 198254885Sdumbbell tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 199254885Sdumbbell tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 200254885Sdumbbell WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 201254885Sdumbbell WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0); 202254885Sdumbbell} 203254885Sdumbbell 204254885Sdumbbellvoid rs400_gart_fini(struct radeon_device *rdev) 205254885Sdumbbell{ 206254885Sdumbbell radeon_gart_fini(rdev); 207254885Sdumbbell rs400_gart_disable(rdev); 208254885Sdumbbell radeon_gart_table_ram_free(rdev); 209254885Sdumbbell} 210254885Sdumbbell 211254885Sdumbbell#define RS400_PTE_WRITEABLE (1 << 2) 212254885Sdumbbell#define RS400_PTE_READABLE (1 << 3) 213254885Sdumbbell 214254885Sdumbbellint rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 215254885Sdumbbell{ 216254885Sdumbbell uint32_t entry; 217254885Sdumbbell u32 *gtt = rdev->gart.ptr; 218254885Sdumbbell 219254885Sdumbbell if (i < 0 || i > rdev->gart.num_gpu_pages) { 220254885Sdumbbell return -EINVAL; 221254885Sdumbbell } 222254885Sdumbbell 223282199Sdumbbell entry = (lower_32_bits(addr) & ~PAGE_MASK) | 224254885Sdumbbell ((upper_32_bits(addr) & 0xff) << 4) | 225254885Sdumbbell RS400_PTE_WRITEABLE | RS400_PTE_READABLE; 226254885Sdumbbell entry = cpu_to_le32(entry); 227254885Sdumbbell gtt[i] = entry; 228254885Sdumbbell return 0; 229254885Sdumbbell} 230254885Sdumbbell 231254885Sdumbbellint rs400_mc_wait_for_idle(struct radeon_device *rdev) 232254885Sdumbbell{ 233254885Sdumbbell unsigned i; 234254885Sdumbbell uint32_t tmp; 235254885Sdumbbell 236254885Sdumbbell for (i = 0; i < rdev->usec_timeout; i++) { 237254885Sdumbbell /* read MC_STATUS */ 238254885Sdumbbell tmp = RREG32(RADEON_MC_STATUS); 239254885Sdumbbell if (tmp & RADEON_MC_IDLE) { 240254885Sdumbbell return 0; 241254885Sdumbbell } 242254885Sdumbbell DRM_UDELAY(1); 243254885Sdumbbell } 244254885Sdumbbell return -1; 245254885Sdumbbell} 246254885Sdumbbell 247254885Sdumbbellstatic void rs400_gpu_init(struct radeon_device *rdev) 248254885Sdumbbell{ 249254885Sdumbbell /* FIXME: is this correct ? */ 250254885Sdumbbell r420_pipes_init(rdev); 251254885Sdumbbell if (rs400_mc_wait_for_idle(rdev)) { 252254885Sdumbbell DRM_ERROR("rs400: Failed to wait MC idle while " 253254885Sdumbbell "programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS)); 254254885Sdumbbell } 255254885Sdumbbell} 256254885Sdumbbell 257254885Sdumbbellstatic void rs400_mc_init(struct radeon_device *rdev) 258254885Sdumbbell{ 259254885Sdumbbell u64 base; 260254885Sdumbbell 261254885Sdumbbell rs400_gart_adjust_size(rdev); 262254885Sdumbbell rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev); 263254885Sdumbbell /* DDR for all card after R300 & IGP */ 264254885Sdumbbell rdev->mc.vram_is_ddr = true; 265254885Sdumbbell rdev->mc.vram_width = 128; 266254885Sdumbbell r100_vram_init_sizes(rdev); 267254885Sdumbbell base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 268254885Sdumbbell radeon_vram_location(rdev, &rdev->mc, base); 269254885Sdumbbell rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 270254885Sdumbbell radeon_gtt_location(rdev, &rdev->mc); 271254885Sdumbbell radeon_update_bandwidth_info(rdev); 272254885Sdumbbell} 273254885Sdumbbell 274254885Sdumbbelluint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) 275254885Sdumbbell{ 276254885Sdumbbell uint32_t r; 277254885Sdumbbell 278254885Sdumbbell WREG32(RS480_NB_MC_INDEX, reg & 0xff); 279254885Sdumbbell r = RREG32(RS480_NB_MC_DATA); 280254885Sdumbbell WREG32(RS480_NB_MC_INDEX, 0xff); 281254885Sdumbbell return r; 282254885Sdumbbell} 283254885Sdumbbell 284254885Sdumbbellvoid rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 285254885Sdumbbell{ 286254885Sdumbbell WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); 287254885Sdumbbell WREG32(RS480_NB_MC_DATA, (v)); 288254885Sdumbbell WREG32(RS480_NB_MC_INDEX, 0xff); 289254885Sdumbbell} 290254885Sdumbbell 291254885Sdumbbell#if defined(CONFIG_DEBUG_FS) 292254885Sdumbbellstatic int rs400_debugfs_gart_info(struct seq_file *m, void *data) 293254885Sdumbbell{ 294254885Sdumbbell struct drm_info_node *node = (struct drm_info_node *) m->private; 295254885Sdumbbell struct drm_device *dev = node->minor->dev; 296254885Sdumbbell struct radeon_device *rdev = dev->dev_private; 297254885Sdumbbell uint32_t tmp; 298254885Sdumbbell 299254885Sdumbbell tmp = RREG32(RADEON_HOST_PATH_CNTL); 300254885Sdumbbell seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 301254885Sdumbbell tmp = RREG32(RADEON_BUS_CNTL); 302254885Sdumbbell seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 303254885Sdumbbell tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 304254885Sdumbbell seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp); 305254885Sdumbbell if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 306254885Sdumbbell tmp = RREG32_MC(RS690_MCCFG_AGP_BASE); 307254885Sdumbbell seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp); 308254885Sdumbbell tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2); 309254885Sdumbbell seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); 310254885Sdumbbell tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); 311254885Sdumbbell seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); 312254885Sdumbbell tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION); 313254885Sdumbbell seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); 314254885Sdumbbell tmp = RREG32(RS690_HDP_FB_LOCATION); 315254885Sdumbbell seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); 316254885Sdumbbell } else { 317254885Sdumbbell tmp = RREG32(RADEON_AGP_BASE); 318254885Sdumbbell seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 319254885Sdumbbell tmp = RREG32(RS480_AGP_BASE_2); 320254885Sdumbbell seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp); 321254885Sdumbbell tmp = RREG32(RADEON_MC_AGP_LOCATION); 322254885Sdumbbell seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 323254885Sdumbbell } 324254885Sdumbbell tmp = RREG32_MC(RS480_GART_BASE); 325254885Sdumbbell seq_printf(m, "GART_BASE 0x%08x\n", tmp); 326254885Sdumbbell tmp = RREG32_MC(RS480_GART_FEATURE_ID); 327254885Sdumbbell seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp); 328254885Sdumbbell tmp = RREG32_MC(RS480_AGP_MODE_CNTL); 329254885Sdumbbell seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp); 330254885Sdumbbell tmp = RREG32_MC(RS480_MC_MISC_CNTL); 331254885Sdumbbell seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp); 332254885Sdumbbell tmp = RREG32_MC(0x5F); 333254885Sdumbbell seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp); 334254885Sdumbbell tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE); 335254885Sdumbbell seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp); 336254885Sdumbbell tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 337254885Sdumbbell seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp); 338254885Sdumbbell tmp = RREG32_MC(0x3B); 339254885Sdumbbell seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp); 340254885Sdumbbell tmp = RREG32_MC(0x3C); 341254885Sdumbbell seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp); 342254885Sdumbbell tmp = RREG32_MC(0x30); 343254885Sdumbbell seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp); 344254885Sdumbbell tmp = RREG32_MC(0x31); 345254885Sdumbbell seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp); 346254885Sdumbbell tmp = RREG32_MC(0x32); 347254885Sdumbbell seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp); 348254885Sdumbbell tmp = RREG32_MC(0x33); 349254885Sdumbbell seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp); 350254885Sdumbbell tmp = RREG32_MC(0x34); 351254885Sdumbbell seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp); 352254885Sdumbbell tmp = RREG32_MC(0x35); 353254885Sdumbbell seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp); 354254885Sdumbbell tmp = RREG32_MC(0x36); 355254885Sdumbbell seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp); 356254885Sdumbbell tmp = RREG32_MC(0x37); 357254885Sdumbbell seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp); 358254885Sdumbbell return 0; 359254885Sdumbbell} 360254885Sdumbbell 361254885Sdumbbellstatic struct drm_info_list rs400_gart_info_list[] = { 362254885Sdumbbell {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL}, 363254885Sdumbbell}; 364254885Sdumbbell#endif 365254885Sdumbbell 366254885Sdumbbellstatic int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 367254885Sdumbbell{ 368254885Sdumbbell#if defined(CONFIG_DEBUG_FS) 369254885Sdumbbell return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1); 370254885Sdumbbell#else 371254885Sdumbbell return 0; 372254885Sdumbbell#endif 373254885Sdumbbell} 374254885Sdumbbell 375254885Sdumbbellstatic void rs400_mc_program(struct radeon_device *rdev) 376254885Sdumbbell{ 377254885Sdumbbell struct r100_mc_save save; 378254885Sdumbbell 379254885Sdumbbell /* Stops all mc clients */ 380254885Sdumbbell r100_mc_stop(rdev, &save); 381254885Sdumbbell 382254885Sdumbbell /* Wait for mc idle */ 383254885Sdumbbell if (rs400_mc_wait_for_idle(rdev)) 384254885Sdumbbell dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n"); 385254885Sdumbbell WREG32(R_000148_MC_FB_LOCATION, 386254885Sdumbbell S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 387254885Sdumbbell S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 388254885Sdumbbell 389254885Sdumbbell r100_mc_resume(rdev, &save); 390254885Sdumbbell} 391254885Sdumbbell 392254885Sdumbbellstatic int rs400_startup(struct radeon_device *rdev) 393254885Sdumbbell{ 394254885Sdumbbell int r; 395254885Sdumbbell 396254885Sdumbbell r100_set_common_regs(rdev); 397254885Sdumbbell 398254885Sdumbbell rs400_mc_program(rdev); 399254885Sdumbbell /* Resume clock */ 400254885Sdumbbell r300_clock_startup(rdev); 401254885Sdumbbell /* Initialize GPU configuration (# pipes, ...) */ 402254885Sdumbbell rs400_gpu_init(rdev); 403254885Sdumbbell r100_enable_bm(rdev); 404254885Sdumbbell /* Initialize GART (initialize after TTM so we can allocate 405254885Sdumbbell * memory through TTM but finalize after TTM) */ 406254885Sdumbbell r = rs400_gart_enable(rdev); 407254885Sdumbbell if (r) 408254885Sdumbbell return r; 409254885Sdumbbell 410254885Sdumbbell /* allocate wb buffer */ 411254885Sdumbbell r = radeon_wb_init(rdev); 412254885Sdumbbell if (r) 413254885Sdumbbell return r; 414254885Sdumbbell 415254885Sdumbbell r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 416254885Sdumbbell if (r) { 417254885Sdumbbell dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 418254885Sdumbbell return r; 419254885Sdumbbell } 420254885Sdumbbell 421254885Sdumbbell /* Enable IRQ */ 422254885Sdumbbell r100_irq_set(rdev); 423254885Sdumbbell rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 424254885Sdumbbell /* 1M ring buffer */ 425254885Sdumbbell r = r100_cp_init(rdev, 1024 * 1024); 426254885Sdumbbell if (r) { 427254885Sdumbbell dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 428254885Sdumbbell return r; 429254885Sdumbbell } 430254885Sdumbbell 431254885Sdumbbell r = radeon_ib_pool_init(rdev); 432254885Sdumbbell if (r) { 433254885Sdumbbell dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 434254885Sdumbbell return r; 435254885Sdumbbell } 436254885Sdumbbell 437254885Sdumbbell return 0; 438254885Sdumbbell} 439254885Sdumbbell 440254885Sdumbbellint rs400_resume(struct radeon_device *rdev) 441254885Sdumbbell{ 442254885Sdumbbell int r; 443254885Sdumbbell 444254885Sdumbbell /* Make sur GART are not working */ 445254885Sdumbbell rs400_gart_disable(rdev); 446254885Sdumbbell /* Resume clock before doing reset */ 447254885Sdumbbell r300_clock_startup(rdev); 448254885Sdumbbell /* setup MC before calling post tables */ 449254885Sdumbbell rs400_mc_program(rdev); 450254885Sdumbbell /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 451254885Sdumbbell if (radeon_asic_reset(rdev)) { 452254885Sdumbbell dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 453254885Sdumbbell RREG32(R_000E40_RBBM_STATUS), 454254885Sdumbbell RREG32(R_0007C0_CP_STAT)); 455254885Sdumbbell } 456254885Sdumbbell /* post */ 457254885Sdumbbell radeon_combios_asic_init(rdev->ddev); 458254885Sdumbbell /* Resume clock after posting */ 459254885Sdumbbell r300_clock_startup(rdev); 460254885Sdumbbell /* Initialize surface registers */ 461254885Sdumbbell radeon_surface_init(rdev); 462254885Sdumbbell 463254885Sdumbbell rdev->accel_working = true; 464254885Sdumbbell r = rs400_startup(rdev); 465254885Sdumbbell if (r) { 466254885Sdumbbell rdev->accel_working = false; 467254885Sdumbbell } 468254885Sdumbbell return r; 469254885Sdumbbell} 470254885Sdumbbell 471254885Sdumbbellint rs400_suspend(struct radeon_device *rdev) 472254885Sdumbbell{ 473254885Sdumbbell r100_cp_disable(rdev); 474254885Sdumbbell radeon_wb_disable(rdev); 475254885Sdumbbell r100_irq_disable(rdev); 476254885Sdumbbell rs400_gart_disable(rdev); 477254885Sdumbbell return 0; 478254885Sdumbbell} 479254885Sdumbbell 480254885Sdumbbellvoid rs400_fini(struct radeon_device *rdev) 481254885Sdumbbell{ 482254885Sdumbbell r100_cp_fini(rdev); 483254885Sdumbbell radeon_wb_fini(rdev); 484254885Sdumbbell radeon_ib_pool_fini(rdev); 485254885Sdumbbell radeon_gem_fini(rdev); 486254885Sdumbbell rs400_gart_fini(rdev); 487254885Sdumbbell radeon_irq_kms_fini(rdev); 488254885Sdumbbell radeon_fence_driver_fini(rdev); 489254885Sdumbbell radeon_bo_fini(rdev); 490254885Sdumbbell radeon_atombios_fini(rdev); 491254885Sdumbbell free(rdev->bios, DRM_MEM_DRIVER); 492254885Sdumbbell rdev->bios = NULL; 493254885Sdumbbell} 494254885Sdumbbell 495254885Sdumbbellint rs400_init(struct radeon_device *rdev) 496254885Sdumbbell{ 497254885Sdumbbell int r; 498254885Sdumbbell 499254885Sdumbbell /* Disable VGA */ 500254885Sdumbbell r100_vga_render_disable(rdev); 501254885Sdumbbell /* Initialize scratch registers */ 502254885Sdumbbell radeon_scratch_init(rdev); 503254885Sdumbbell /* Initialize surface registers */ 504254885Sdumbbell radeon_surface_init(rdev); 505254885Sdumbbell /* TODO: disable VGA need to use VGA request */ 506254885Sdumbbell /* restore some register to sane defaults */ 507254885Sdumbbell r100_restore_sanity(rdev); 508254885Sdumbbell /* BIOS*/ 509254885Sdumbbell if (!radeon_get_bios(rdev)) { 510254885Sdumbbell if (ASIC_IS_AVIVO(rdev)) 511254885Sdumbbell return -EINVAL; 512254885Sdumbbell } 513254885Sdumbbell if (rdev->is_atom_bios) { 514254885Sdumbbell dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 515254885Sdumbbell return -EINVAL; 516254885Sdumbbell } else { 517254885Sdumbbell r = radeon_combios_init(rdev); 518254885Sdumbbell if (r) 519254885Sdumbbell return r; 520254885Sdumbbell } 521254885Sdumbbell /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 522254885Sdumbbell if (radeon_asic_reset(rdev)) { 523254885Sdumbbell dev_warn(rdev->dev, 524254885Sdumbbell "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 525254885Sdumbbell RREG32(R_000E40_RBBM_STATUS), 526254885Sdumbbell RREG32(R_0007C0_CP_STAT)); 527254885Sdumbbell } 528254885Sdumbbell /* check if cards are posted or not */ 529254885Sdumbbell if (radeon_boot_test_post_card(rdev) == false) 530254885Sdumbbell return -EINVAL; 531254885Sdumbbell 532254885Sdumbbell /* Initialize clocks */ 533254885Sdumbbell radeon_get_clock_info(rdev->ddev); 534254885Sdumbbell /* initialize memory controller */ 535254885Sdumbbell rs400_mc_init(rdev); 536254885Sdumbbell /* Fence driver */ 537254885Sdumbbell r = radeon_fence_driver_init(rdev); 538254885Sdumbbell if (r) 539254885Sdumbbell return r; 540254885Sdumbbell r = radeon_irq_kms_init(rdev); 541254885Sdumbbell if (r) 542254885Sdumbbell return r; 543254885Sdumbbell /* Memory manager */ 544254885Sdumbbell r = radeon_bo_init(rdev); 545254885Sdumbbell if (r) 546254885Sdumbbell return r; 547254885Sdumbbell r = rs400_gart_init(rdev); 548254885Sdumbbell if (r) 549254885Sdumbbell return r; 550254885Sdumbbell r300_set_reg_safe(rdev); 551254885Sdumbbell 552254885Sdumbbell rdev->accel_working = true; 553254885Sdumbbell r = rs400_startup(rdev); 554254885Sdumbbell if (r) { 555254885Sdumbbell /* Somethings want wront with the accel init stop accel */ 556254885Sdumbbell dev_err(rdev->dev, "Disabling GPU acceleration\n"); 557254885Sdumbbell r100_cp_fini(rdev); 558254885Sdumbbell radeon_wb_fini(rdev); 559254885Sdumbbell radeon_ib_pool_fini(rdev); 560254885Sdumbbell rs400_gart_fini(rdev); 561254885Sdumbbell radeon_irq_kms_fini(rdev); 562254885Sdumbbell rdev->accel_working = false; 563254885Sdumbbell } 564254885Sdumbbell return 0; 565254885Sdumbbell} 566