/freebsd-10-stable/contrib/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, argument 30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); 45 MachineInstr *DefMI = LastMI; local 61 DefMI = &*I; 65 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && 67 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
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H A D | MLxExpansionPass.cpp | 94 MachineInstr *DefMI = MRI->getVRegDef(Reg); local 96 if (DefMI->getParent() != MBB) 98 if (DefMI->isCopyLike()) { 99 Reg = DefMI->getOperand(1).getReg(); 101 DefMI = MRI->getVRegDef(Reg); 104 } else if (DefMI->isInsertSubreg()) { 105 Reg = DefMI->getOperand(2).getReg(); 107 DefMI = MRI->getVRegDef(Reg); 113 return DefMI; 148 MachineInstr *DefMI local [all...] |
H A D | ARMBaseInstrInfo.h | 215 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 223 const MachineInstr *DefMI, unsigned DefIdx, 278 const MachineInstr *DefMI, unsigned DefIdx, 281 const MachineInstr *DefMI, unsigned DefIdx) const;
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H A D | ARMBaseInstrInfo.cpp | 1730 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this); local 1731 bool Invert = !DefMI; 1732 if (!DefMI) 1733 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this); 1734 if (!DefMI) 1744 // Create a new predicated version of DefMI. 1747 DefMI->getDesc(), DestReg); 1749 // Copy all the DefMI operands, excluding its (null) predicate. 1750 const MCInstrDesc &DefDesc = DefMI->getDesc(); 1753 NewMI.addOperand(DefMI 2462 FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const argument 3289 adjustDefLatency(const ARMSubtarget &Subtarget, const MachineInstr *DefMI, const MCInstrDesc *DefMCID, unsigned DefAlign) argument 3470 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument 3863 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument 3885 hasLowDefLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx) const argument [all...] |
/freebsd-10-stable/contrib/llvm/lib/CodeGen/ |
H A D | TargetSchedule.cpp | 156 const MachineInstr *DefMI, unsigned DefOperIdx, 160 return TII->defaultDefLatency(&SchedModel, DefMI); 165 OperLatency = TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, 169 unsigned DefClass = DefMI->getDesc().getSchedClass(); 176 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI); 184 TII->defaultDefLatency(&SchedModel, DefMI)); 188 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); 189 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); 212 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit() 213 && !DefMI 155 computeOperandLatency( const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const argument 218 << *DefMI; local 255 computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *DepMI) const argument [all...] |
H A D | LiveRangeEdit.cpp | 51 const MachineInstr *DefMI, 53 assert(DefMI && "Missing instruction"); 55 if (!TII.isTriviallyReMaterializable(DefMI, aa)) 67 MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def); local 68 if (!DefMI) 70 checkRematerializable(VNI, DefMI, aa); 167 MachineInstr *DefMI = 0, *UseMI = 0; local 175 if (DefMI && DefMI != MI) 179 DefMI 50 checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI, AliasAnalysis *aa) argument [all...] |
H A D | TargetInstrInfo.cpp | 665 const MachineInstr *DefMI) const { 666 if (DefMI->isTransient()) 668 if (DefMI->mayLoad()) 670 if (isHighLatencyDef(DefMI->getOpcode())) 692 const MachineInstr *DefMI, 697 unsigned DefClass = DefMI->getDesc().getSchedClass(); 702 /// Both DefMI and UseMI must be valid. By default, call directly to the 706 const MachineInstr *DefMI, unsigned DefIdx, 708 unsigned DefClass = DefMI->getDesc().getSchedClass(); 717 const MachineInstr *DefMI) cons 691 hasLowDefLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx) const argument 705 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument 742 computeOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument [all...] |
H A D | RegisterCoalescer.cpp | 591 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def); 592 if (!DefMI) 594 if (!DefMI->isCommutable()) 596 // If DefMI is a two-address instruction then commuting it will change the 598 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); 601 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) 604 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2)) 613 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); 639 << *DefMI); 643 MachineBasicBlock *MBB = DefMI 1422 computeWriteLanes(const MachineInstr *DefMI, bool &Redef) argument 1471 const MachineInstr *DefMI = 0; local [all...] |
H A D | MachineTraceMetrics.cpp | 617 const MachineInstr *DefMI; 621 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp) 622 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} 630 DefMI = &*DefI; 770 const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg); 772 const TraceBlockInfo &DefTBI = BlockInfo[DefMI->getParent()->getNumber()]; 775 unsigned Len = LIR.Height + Cycles[DefMI].Depth; 847 BlockInfo[Dep.DefMI->getParent()->getNumber()]; 852 unsigned DepCycle = Cycles.lookup(Dep.DefMI) [all...] |
H A D | InlineSpiller.cpp | 112 MachineInstr *DefMI; member in struct:__anon2266::InlineSpiller::SibValueInfo 123 SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {} 126 bool hasDef() const { return DefByOrigPHI || DefMI; } 332 if (SVI.DefMI) 333 OS << " def: " << *SVI.DefMI; 396 DepSV.DefMI = SV.DefMI; 484 return SVI->second.DefMI; 602 SVI->second.DefMI = MI; 623 return SVI->second.DefMI; 646 MachineInstr *DefMI = 0; local 721 MachineInstr *DefMI = LIS.getInstructionFromIndex(SVI.SpillVNI->def); local [all...] |
H A D | MachineCSE.cpp | 128 MachineInstr *DefMI = MRI->getVRegDef(Reg); local 129 if (!DefMI->isCopy()) 131 unsigned SrcReg = DefMI->getOperand(1).getReg(); 134 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg()) 138 DEBUG(dbgs() << "Coalescing: " << *DefMI); 142 DefMI->eraseFromParent();
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H A D | PHIElimination.cpp | 154 MachineInstr *DefMI = *I; local 155 unsigned DefReg = DefMI->getOperand(0).getReg(); 158 LIS->RemoveMachineInstrFromMaps(DefMI); 159 DefMI->eraseFromParent(); 392 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) 393 if (DefMI->isImplicitDef()) 394 ImpDefs.insert(DefMI);
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H A D | EarlyIfConversion.cpp | 244 MachineInstr *DefMI = MRI->getVRegDef(Reg); local 245 if (!DefMI || DefMI->getParent() != Head) 247 if (InsertAfter.insert(DefMI)) 248 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI); 249 if (DefMI->isTerminator()) {
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H A D | MachineSink.cpp | 140 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); 141 if (DefMI->isCopyLike()) 143 DEBUG(dbgs() << "Coalescing: " << *DefMI); 330 MachineInstr *DefMI = MRI->getVRegDef(Reg); local 331 if (DefMI->getParent() == MI->getParent())
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H A D | PeepholeOptimizer.cpp | 636 MachineInstr *DefMI = 0; local 638 FoldAsLoadDefReg, DefMI); 640 // Update LocalMIs since we replaced MI with FoldMI and deleted DefMI. 644 LocalMIs.erase(DefMI); 647 DefMI->eraseFromParent();
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H A D | TwoAddressInstructionPass.cpp | 407 MachineInstr *DefMI = &MI; local 413 if (!isPlainlyKilled(DefMI, Reg, LIS)) 422 DefMI = &*Begin; 427 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 919 MachineInstr *DefMI = &*DI; local 920 if (DefMI->getParent() != MBB || DefMI->isCopy() || DefMI->isCopyLike()) 922 if (DefMI == MI) 924 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(DefMI); [all...] |
H A D | TailDuplication.cpp | 236 MachineInstr *DefMI = MRI->getVRegDef(VReg); local 238 if (DefMI) { 239 DefBB = DefMI->getParent();
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/freebsd-10-stable/contrib/llvm/include/llvm/CodeGen/ |
H A D | TargetSchedule.h | 145 unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, 166 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
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H A D | LiveRangeEdit.h | 169 /// values if DefMI may be rematerializable. 170 bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI,
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H A D | MachineTraceMetrics.h | 307 void addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
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/freebsd-10-stable/contrib/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 776 /// defined by the load we are trying to fold. DefMI returns the machine 782 MachineInstr *&DefMI) const { 789 /// then the caller may assume that DefMI has been erased from its parent 792 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, argument 825 const MachineInstr *DefMI, unsigned DefIdx, 832 const MachineInstr *DefMI, unsigned DefIdx, 850 const MachineInstr *DefMI) const; 853 const MachineInstr *DefMI) const; 867 const MachineInstr *DefMI, unsigned DefIdx, 876 const MachineInstr *DefMI, unsigne 865 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument [all...] |
/freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.h | 155 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
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H A D | PPCInstrInfo.cpp | 817 bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, argument 821 unsigned DefOpc = DefMI->getOpcode(); 824 if (!DefMI->getOperand(1).isImm()) 826 if (DefMI->getOperand(1).getImm() != 0) 880 DefMI->eraseFromParent();
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/freebsd-10-stable/contrib/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.h | 389 const MachineInstr *DefMI, unsigned DefIdx, 411 /// defined by the load we are trying to fold. DefMI returns the machine 417 MachineInstr *&DefMI) const;
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/freebsd-10-stable/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 495 MachineInstr *DefMI = MRI->getVRegDef(VReg); 497 if (DefMI && 498 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
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