1234353Sdim//===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file contains the PowerPC implementation of the TargetInstrInfo class. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14234353Sdim#ifndef POWERPC_INSTRUCTIONINFO_H 15234353Sdim#define POWERPC_INSTRUCTIONINFO_H 16193323Sed 17193323Sed#include "PPC.h" 18234353Sdim#include "PPCRegisterInfo.h" 19193323Sed#include "llvm/Target/TargetInstrInfo.h" 20193323Sed 21224145Sdim#define GET_INSTRINFO_HEADER 22224145Sdim#include "PPCGenInstrInfo.inc" 23224145Sdim 24193323Sednamespace llvm { 25193323Sed 26193323Sed/// PPCII - This namespace holds all of the PowerPC target-specific 27193323Sed/// per-instruction flags. These must match the corresponding definitions in 28193323Sed/// PPC.td and PPCInstrFormats.td. 29193323Sednamespace PPCII { 30193323Sedenum { 31193323Sed // PPC970 Instruction Flags. These flags describe the characteristics of the 32193323Sed // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 33193323Sed // raw machine instructions. 34193323Sed 35193323Sed /// PPC970_First - This instruction starts a new dispatch group, so it will 36193323Sed /// always be the first one in the group. 37193323Sed PPC970_First = 0x1, 38218893Sdim 39193323Sed /// PPC970_Single - This instruction starts a new dispatch group and 40193323Sed /// terminates it, so it will be the sole instruction in the group. 41193323Sed PPC970_Single = 0x2, 42193323Sed 43193323Sed /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 44193323Sed /// two dispatch pipes to be available to issue. 45193323Sed PPC970_Cracked = 0x4, 46218893Sdim 47193323Sed /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 48193323Sed /// an instruction is issued to. 49193323Sed PPC970_Shift = 3, 50193323Sed PPC970_Mask = 0x07 << PPC970_Shift 51193323Sed}; 52193323Sedenum PPC970_Unit { 53193323Sed /// These are the various PPC970 execution unit pipelines. Each instruction 54193323Sed /// is one of these. 55193323Sed PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 56193323Sed PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 57193323Sed PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 58193323Sed PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 59193323Sed PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 60193323Sed PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 61193323Sed PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 62193323Sed PPC970_BRU = 7 << PPC970_Shift // Branch Unit 63193323Sed}; 64218893Sdim} // end namespace PPCII 65218893Sdim 66218893Sdim 67224145Sdimclass PPCInstrInfo : public PPCGenInstrInfo { 68193323Sed PPCTargetMachine &TM; 69193323Sed const PPCRegisterInfo RI; 70193323Sed 71193323Sed bool StoreRegToStackSlot(MachineFunction &MF, 72193323Sed unsigned SrcReg, bool isKill, int FrameIdx, 73193323Sed const TargetRegisterClass *RC, 74249423Sdim SmallVectorImpl<MachineInstr*> &NewMIs, 75249423Sdim bool &NonRI, bool &SpillsVRS) const; 76234353Sdim bool LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, 77193323Sed unsigned DestReg, int FrameIdx, 78193323Sed const TargetRegisterClass *RC, 79249423Sdim SmallVectorImpl<MachineInstr*> &NewMIs, 80249423Sdim bool &NonRI, bool &SpillsVRS) const; 81263508Sdim virtual void anchor(); 82193323Sedpublic: 83193323Sed explicit PPCInstrInfo(PPCTargetMachine &TM); 84193323Sed 85193323Sed /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 86193323Sed /// such, whenever a client has an instance of instruction info, it should 87193323Sed /// always be able to get register info as well (through this method). 88193323Sed /// 89193323Sed virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; } 90193323Sed 91218893Sdim ScheduleHazardRecognizer * 92218893Sdim CreateTargetHazardRecognizer(const TargetMachine *TM, 93218893Sdim const ScheduleDAG *DAG) const; 94234353Sdim ScheduleHazardRecognizer * 95234353Sdim CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 96234353Sdim const ScheduleDAG *DAG) const; 97218893Sdim 98239462Sdim bool isCoalescableExtInstr(const MachineInstr &MI, 99239462Sdim unsigned &SrcReg, unsigned &DstReg, 100239462Sdim unsigned &SubIdx) const; 101193323Sed unsigned isLoadFromStackSlot(const MachineInstr *MI, 102193323Sed int &FrameIndex) const; 103193323Sed unsigned isStoreToStackSlot(const MachineInstr *MI, 104193323Sed int &FrameIndex) const; 105193323Sed 106193323Sed // commuteInstruction - We can commute rlwimi instructions, but only if the 107193323Sed // rotate amt is zero. We also have to munge the immediates a bit. 108193323Sed virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 109218893Sdim 110218893Sdim virtual void insertNoop(MachineBasicBlock &MBB, 111193323Sed MachineBasicBlock::iterator MI) const; 112193323Sed 113193323Sed 114193323Sed // Branch analysis. 115193323Sed virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 116193323Sed MachineBasicBlock *&FBB, 117193323Sed SmallVectorImpl<MachineOperand> &Cond, 118193323Sed bool AllowModify) const; 119193323Sed virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 120193323Sed virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 121193323Sed MachineBasicBlock *FBB, 122210299Sed const SmallVectorImpl<MachineOperand> &Cond, 123210299Sed DebugLoc DL) const; 124251662Sdim 125251662Sdim // Select analysis. 126251662Sdim virtual bool canInsertSelect(const MachineBasicBlock&, 127251662Sdim const SmallVectorImpl<MachineOperand> &Cond, 128251662Sdim unsigned, unsigned, int&, int&, int&) const; 129251662Sdim virtual void insertSelect(MachineBasicBlock &MBB, 130251662Sdim MachineBasicBlock::iterator MI, DebugLoc DL, 131251662Sdim unsigned DstReg, 132251662Sdim const SmallVectorImpl<MachineOperand> &Cond, 133251662Sdim unsigned TrueReg, unsigned FalseReg) const; 134251662Sdim 135210299Sed virtual void copyPhysReg(MachineBasicBlock &MBB, 136210299Sed MachineBasicBlock::iterator I, DebugLoc DL, 137210299Sed unsigned DestReg, unsigned SrcReg, 138210299Sed bool KillSrc) const; 139218893Sdim 140193323Sed virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 141193323Sed MachineBasicBlock::iterator MBBI, 142193323Sed unsigned SrcReg, bool isKill, int FrameIndex, 143208599Srdivacky const TargetRegisterClass *RC, 144208599Srdivacky const TargetRegisterInfo *TRI) const; 145193323Sed 146193323Sed virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 147193323Sed MachineBasicBlock::iterator MBBI, 148193323Sed unsigned DestReg, int FrameIndex, 149208599Srdivacky const TargetRegisterClass *RC, 150208599Srdivacky const TargetRegisterInfo *TRI) const; 151218893Sdim 152193323Sed virtual 153193323Sed bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 154218893Sdim 155251662Sdim virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 156251662Sdim unsigned Reg, MachineRegisterInfo *MRI) const; 157251662Sdim 158251662Sdim // If conversion by predication (only supported by some branch instructions). 159251662Sdim // All of the profitability checks always return true; it is always 160251662Sdim // profitable to use the predicated branches. 161251662Sdim virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, 162251662Sdim unsigned NumCycles, unsigned ExtraPredCycles, 163251662Sdim const BranchProbability &Probability) const { 164251662Sdim return true; 165251662Sdim } 166251662Sdim 167251662Sdim virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 168251662Sdim unsigned NumT, unsigned ExtraT, 169251662Sdim MachineBasicBlock &FMBB, 170251662Sdim unsigned NumF, unsigned ExtraF, 171251662Sdim const BranchProbability &Probability) const; 172251662Sdim 173251662Sdim virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, 174251662Sdim unsigned NumCycles, 175251662Sdim const BranchProbability 176251662Sdim &Probability) const { 177251662Sdim return true; 178251662Sdim } 179251662Sdim 180251662Sdim virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 181251662Sdim MachineBasicBlock &FMBB) const { 182251662Sdim return false; 183251662Sdim } 184251662Sdim 185251662Sdim // Predication support. 186251662Sdim bool isPredicated(const MachineInstr *MI) const; 187251662Sdim 188251662Sdim virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 189251662Sdim 190251662Sdim virtual 191251662Sdim bool PredicateInstruction(MachineInstr *MI, 192251662Sdim const SmallVectorImpl<MachineOperand> &Pred) const; 193251662Sdim 194251662Sdim virtual 195251662Sdim bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 196251662Sdim const SmallVectorImpl<MachineOperand> &Pred2) const; 197251662Sdim 198251662Sdim virtual bool DefinesPredicate(MachineInstr *MI, 199251662Sdim std::vector<MachineOperand> &Pred) const; 200251662Sdim 201251662Sdim virtual bool isPredicable(MachineInstr *MI) const; 202251662Sdim 203251662Sdim // Comparison optimization. 204251662Sdim 205251662Sdim 206251662Sdim virtual bool analyzeCompare(const MachineInstr *MI, 207251662Sdim unsigned &SrcReg, unsigned &SrcReg2, 208251662Sdim int &Mask, int &Value) const; 209251662Sdim 210251662Sdim virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, 211251662Sdim unsigned SrcReg, unsigned SrcReg2, 212251662Sdim int Mask, int Value, 213251662Sdim const MachineRegisterInfo *MRI) const; 214251662Sdim 215193323Sed /// GetInstSize - Return the number of bytes of code the specified 216193323Sed /// instruction may be. This returns the maximum number of bytes. 217193323Sed /// 218193323Sed virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 219193323Sed}; 220193323Sed 221193323Sed} 222193323Sed 223193323Sed#endif 224