1234353Sdim//===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file contains the PowerPC implementation of the TargetInstrInfo class. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed#include "PPCInstrInfo.h" 15249423Sdim#include "MCTargetDesc/PPCPredicates.h" 16224145Sdim#include "PPC.h" 17249423Sdim#include "PPCHazardRecognizers.h" 18193323Sed#include "PPCInstrBuilder.h" 19193323Sed#include "PPCMachineFunctionInfo.h" 20193323Sed#include "PPCTargetMachine.h" 21251662Sdim#include "llvm/ADT/Statistic.h" 22249423Sdim#include "llvm/ADT/STLExtras.h" 23212904Sdim#include "llvm/CodeGen/MachineFrameInfo.h" 24251662Sdim#include "llvm/CodeGen/MachineFunctionPass.h" 25193323Sed#include "llvm/CodeGen/MachineInstrBuilder.h" 26212904Sdim#include "llvm/CodeGen/MachineMemOperand.h" 27204642Srdivacky#include "llvm/CodeGen/MachineRegisterInfo.h" 28212904Sdim#include "llvm/CodeGen/PseudoSourceValue.h" 29224145Sdim#include "llvm/MC/MCAsmInfo.h" 30193323Sed#include "llvm/Support/CommandLine.h" 31198090Srdivacky#include "llvm/Support/ErrorHandling.h" 32226633Sdim#include "llvm/Support/TargetRegistry.h" 33198090Srdivacky#include "llvm/Support/raw_ostream.h" 34193323Sed 35251662Sdim#define GET_INSTRMAP_INFO 36263508Sdim#define GET_INSTRINFO_CTOR_DTOR 37224145Sdim#include "PPCGenInstrInfo.inc" 38224145Sdim 39207618Srdivackyusing namespace llvm; 40207618Srdivacky 41239462Sdimstatic cl:: 42239462Sdimopt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, 43239462Sdim cl::desc("Disable analysis for CTR loops")); 44239462Sdim 45251662Sdimstatic cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt", 46251662Sdimcl::desc("Disable compare instruction optimization"), cl::Hidden); 47251662Sdim 48263508Sdim// Pin the vtable to this file. 49263508Sdimvoid PPCInstrInfo::anchor() {} 50263508Sdim 51193323SedPPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) 52224145Sdim : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 53263508Sdim TM(tm), RI(*TM.getSubtargetImpl()) {} 54193323Sed 55218893Sdim/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for 56218893Sdim/// this target when scheduling the DAG. 57218893SdimScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer( 58218893Sdim const TargetMachine *TM, 59218893Sdim const ScheduleDAG *DAG) const { 60234353Sdim unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective(); 61243830Sdim if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 || 62243830Sdim Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) { 63234353Sdim const InstrItineraryData *II = TM->getInstrItineraryData(); 64234353Sdim return new PPCScoreboardHazardRecognizer(II, DAG); 65234353Sdim } 66234353Sdim 67249423Sdim return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG); 68218893Sdim} 69218893Sdim 70234353Sdim/// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer 71234353Sdim/// to use for this target when scheduling the DAG. 72234353SdimScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer( 73234353Sdim const InstrItineraryData *II, 74234353Sdim const ScheduleDAG *DAG) const { 75234353Sdim unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective(); 76234353Sdim 77234353Sdim // Most subtargets use a PPC970 recognizer. 78243830Sdim if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 && 79243830Sdim Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) { 80263508Sdim assert(TM.getInstrInfo() && "No InstrInfo?"); 81234353Sdim 82263508Sdim return new PPCHazardRecognizer970(TM); 83234353Sdim } 84234353Sdim 85234353Sdim return new PPCScoreboardHazardRecognizer(II, DAG); 86234353Sdim} 87239462Sdim 88239462Sdim// Detect 32 -> 64-bit extensions where we may reuse the low sub-register. 89239462Sdimbool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 90239462Sdim unsigned &SrcReg, unsigned &DstReg, 91239462Sdim unsigned &SubIdx) const { 92239462Sdim switch (MI.getOpcode()) { 93239462Sdim default: return false; 94239462Sdim case PPC::EXTSW: 95239462Sdim case PPC::EXTSW_32_64: 96239462Sdim SrcReg = MI.getOperand(1).getReg(); 97239462Sdim DstReg = MI.getOperand(0).getReg(); 98239462Sdim SubIdx = PPC::sub_32; 99239462Sdim return true; 100239462Sdim } 101239462Sdim} 102239462Sdim 103218893Sdimunsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 104193323Sed int &FrameIndex) const { 105249423Sdim // Note: This list must be kept consistent with LoadRegFromStackSlot. 106193323Sed switch (MI->getOpcode()) { 107193323Sed default: break; 108193323Sed case PPC::LD: 109193323Sed case PPC::LWZ: 110193323Sed case PPC::LFS: 111193323Sed case PPC::LFD: 112249423Sdim case PPC::RESTORE_CR: 113249423Sdim case PPC::LVX: 114249423Sdim case PPC::RESTORE_VRSAVE: 115249423Sdim // Check for the operands added by addFrameReference (the immediate is the 116249423Sdim // offset which defaults to 0). 117193323Sed if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 118193323Sed MI->getOperand(2).isFI()) { 119193323Sed FrameIndex = MI->getOperand(2).getIndex(); 120193323Sed return MI->getOperand(0).getReg(); 121193323Sed } 122193323Sed break; 123193323Sed } 124193323Sed return 0; 125193323Sed} 126193323Sed 127218893Sdimunsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 128193323Sed int &FrameIndex) const { 129249423Sdim // Note: This list must be kept consistent with StoreRegToStackSlot. 130193323Sed switch (MI->getOpcode()) { 131193323Sed default: break; 132193323Sed case PPC::STD: 133193323Sed case PPC::STW: 134193323Sed case PPC::STFS: 135193323Sed case PPC::STFD: 136249423Sdim case PPC::SPILL_CR: 137249423Sdim case PPC::STVX: 138249423Sdim case PPC::SPILL_VRSAVE: 139249423Sdim // Check for the operands added by addFrameReference (the immediate is the 140249423Sdim // offset which defaults to 0). 141193323Sed if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 142193323Sed MI->getOperand(2).isFI()) { 143193323Sed FrameIndex = MI->getOperand(2).getIndex(); 144193323Sed return MI->getOperand(0).getReg(); 145193323Sed } 146193323Sed break; 147193323Sed } 148193323Sed return 0; 149193323Sed} 150193323Sed 151193323Sed// commuteInstruction - We can commute rlwimi instructions, but only if the 152193323Sed// rotate amt is zero. We also have to munge the immediates a bit. 153193323SedMachineInstr * 154193323SedPPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 155193323Sed MachineFunction &MF = *MI->getParent()->getParent(); 156193323Sed 157193323Sed // Normal instructions can be commuted the obvious way. 158251662Sdim if (MI->getOpcode() != PPC::RLWIMI && 159251662Sdim MI->getOpcode() != PPC::RLWIMIo) 160249423Sdim return TargetInstrInfo::commuteInstruction(MI, NewMI); 161218893Sdim 162193323Sed // Cannot commute if it has a non-zero rotate count. 163193323Sed if (MI->getOperand(3).getImm() != 0) 164193323Sed return 0; 165218893Sdim 166193323Sed // If we have a zero rotate count, we have: 167193323Sed // M = mask(MB,ME) 168193323Sed // Op0 = (Op1 & ~M) | (Op2 & M) 169193323Sed // Change this to: 170193323Sed // M = mask((ME+1)&31, (MB-1)&31) 171193323Sed // Op0 = (Op2 & ~M) | (Op1 & M) 172193323Sed 173193323Sed // Swap op1/op2 174193323Sed unsigned Reg0 = MI->getOperand(0).getReg(); 175193323Sed unsigned Reg1 = MI->getOperand(1).getReg(); 176193323Sed unsigned Reg2 = MI->getOperand(2).getReg(); 177193323Sed bool Reg1IsKill = MI->getOperand(1).isKill(); 178193323Sed bool Reg2IsKill = MI->getOperand(2).isKill(); 179193323Sed bool ChangeReg0 = false; 180193323Sed // If machine instrs are no longer in two-address forms, update 181193323Sed // destination register as well. 182193323Sed if (Reg0 == Reg1) { 183193323Sed // Must be two address instruction! 184224145Sdim assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) && 185193323Sed "Expecting a two-address instruction!"); 186193323Sed Reg2IsKill = false; 187193323Sed ChangeReg0 = true; 188193323Sed } 189193323Sed 190193323Sed // Masks. 191193323Sed unsigned MB = MI->getOperand(4).getImm(); 192193323Sed unsigned ME = MI->getOperand(5).getImm(); 193193323Sed 194193323Sed if (NewMI) { 195193323Sed // Create a new instruction. 196193323Sed unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); 197193323Sed bool Reg0IsDead = MI->getOperand(0).isDead(); 198193323Sed return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) 199193323Sed .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) 200193323Sed .addReg(Reg2, getKillRegState(Reg2IsKill)) 201193323Sed .addReg(Reg1, getKillRegState(Reg1IsKill)) 202193323Sed .addImm((ME+1) & 31) 203193323Sed .addImm((MB-1) & 31); 204193323Sed } 205193323Sed 206193323Sed if (ChangeReg0) 207193323Sed MI->getOperand(0).setReg(Reg2); 208193323Sed MI->getOperand(2).setReg(Reg1); 209193323Sed MI->getOperand(1).setReg(Reg2); 210193323Sed MI->getOperand(2).setIsKill(Reg1IsKill); 211193323Sed MI->getOperand(1).setIsKill(Reg2IsKill); 212218893Sdim 213193323Sed // Swap the mask around. 214193323Sed MI->getOperand(4).setImm((ME+1) & 31); 215193323Sed MI->getOperand(5).setImm((MB-1) & 31); 216193323Sed return MI; 217193323Sed} 218193323Sed 219218893Sdimvoid PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, 220193323Sed MachineBasicBlock::iterator MI) const { 221206124Srdivacky DebugLoc DL; 222193323Sed BuildMI(MBB, MI, DL, get(PPC::NOP)); 223193323Sed} 224193323Sed 225193323Sed 226193323Sed// Branch analysis. 227239462Sdim// Note: If the condition register is set to CTR or CTR8 then this is a 228239462Sdim// BDNZ (imm == 1) or BDZ (imm == 0) branch. 229193323Sedbool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 230193323Sed MachineBasicBlock *&FBB, 231193323Sed SmallVectorImpl<MachineOperand> &Cond, 232193323Sed bool AllowModify) const { 233239462Sdim bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); 234239462Sdim 235193323Sed // If the block has no terminators, it just falls into the block after it. 236193323Sed MachineBasicBlock::iterator I = MBB.end(); 237206083Srdivacky if (I == MBB.begin()) 238193323Sed return false; 239206083Srdivacky --I; 240206083Srdivacky while (I->isDebugValue()) { 241206083Srdivacky if (I == MBB.begin()) 242206083Srdivacky return false; 243206083Srdivacky --I; 244206083Srdivacky } 245206083Srdivacky if (!isUnpredicatedTerminator(I)) 246206083Srdivacky return false; 247193323Sed 248193323Sed // Get the last instruction in the block. 249193323Sed MachineInstr *LastInst = I; 250218893Sdim 251193323Sed // If there is only one terminator instruction, process it. 252193323Sed if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 253193323Sed if (LastInst->getOpcode() == PPC::B) { 254193323Sed if (!LastInst->getOperand(0).isMBB()) 255193323Sed return true; 256193323Sed TBB = LastInst->getOperand(0).getMBB(); 257193323Sed return false; 258193323Sed } else if (LastInst->getOpcode() == PPC::BCC) { 259193323Sed if (!LastInst->getOperand(2).isMBB()) 260193323Sed return true; 261193323Sed // Block ends with fall-through condbranch. 262193323Sed TBB = LastInst->getOperand(2).getMBB(); 263193323Sed Cond.push_back(LastInst->getOperand(0)); 264193323Sed Cond.push_back(LastInst->getOperand(1)); 265193323Sed return false; 266239462Sdim } else if (LastInst->getOpcode() == PPC::BDNZ8 || 267239462Sdim LastInst->getOpcode() == PPC::BDNZ) { 268239462Sdim if (!LastInst->getOperand(0).isMBB()) 269239462Sdim return true; 270239462Sdim if (DisableCTRLoopAnal) 271239462Sdim return true; 272239462Sdim TBB = LastInst->getOperand(0).getMBB(); 273239462Sdim Cond.push_back(MachineOperand::CreateImm(1)); 274239462Sdim Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 275239462Sdim true)); 276239462Sdim return false; 277239462Sdim } else if (LastInst->getOpcode() == PPC::BDZ8 || 278239462Sdim LastInst->getOpcode() == PPC::BDZ) { 279239462Sdim if (!LastInst->getOperand(0).isMBB()) 280239462Sdim return true; 281239462Sdim if (DisableCTRLoopAnal) 282239462Sdim return true; 283239462Sdim TBB = LastInst->getOperand(0).getMBB(); 284239462Sdim Cond.push_back(MachineOperand::CreateImm(0)); 285239462Sdim Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 286239462Sdim true)); 287239462Sdim return false; 288193323Sed } 289239462Sdim 290193323Sed // Otherwise, don't know what this is. 291193323Sed return true; 292193323Sed } 293218893Sdim 294193323Sed // Get the instruction before it if it's a terminator. 295193323Sed MachineInstr *SecondLastInst = I; 296193323Sed 297193323Sed // If there are three terminators, we don't know what sort of block this is. 298193323Sed if (SecondLastInst && I != MBB.begin() && 299193323Sed isUnpredicatedTerminator(--I)) 300193323Sed return true; 301218893Sdim 302193323Sed // If the block ends with PPC::B and PPC:BCC, handle it. 303218893Sdim if (SecondLastInst->getOpcode() == PPC::BCC && 304193323Sed LastInst->getOpcode() == PPC::B) { 305193323Sed if (!SecondLastInst->getOperand(2).isMBB() || 306193323Sed !LastInst->getOperand(0).isMBB()) 307193323Sed return true; 308193323Sed TBB = SecondLastInst->getOperand(2).getMBB(); 309193323Sed Cond.push_back(SecondLastInst->getOperand(0)); 310193323Sed Cond.push_back(SecondLastInst->getOperand(1)); 311193323Sed FBB = LastInst->getOperand(0).getMBB(); 312193323Sed return false; 313239462Sdim } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 || 314239462Sdim SecondLastInst->getOpcode() == PPC::BDNZ) && 315239462Sdim LastInst->getOpcode() == PPC::B) { 316239462Sdim if (!SecondLastInst->getOperand(0).isMBB() || 317239462Sdim !LastInst->getOperand(0).isMBB()) 318239462Sdim return true; 319239462Sdim if (DisableCTRLoopAnal) 320239462Sdim return true; 321239462Sdim TBB = SecondLastInst->getOperand(0).getMBB(); 322239462Sdim Cond.push_back(MachineOperand::CreateImm(1)); 323239462Sdim Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 324239462Sdim true)); 325239462Sdim FBB = LastInst->getOperand(0).getMBB(); 326239462Sdim return false; 327239462Sdim } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 || 328239462Sdim SecondLastInst->getOpcode() == PPC::BDZ) && 329239462Sdim LastInst->getOpcode() == PPC::B) { 330239462Sdim if (!SecondLastInst->getOperand(0).isMBB() || 331239462Sdim !LastInst->getOperand(0).isMBB()) 332239462Sdim return true; 333239462Sdim if (DisableCTRLoopAnal) 334239462Sdim return true; 335239462Sdim TBB = SecondLastInst->getOperand(0).getMBB(); 336239462Sdim Cond.push_back(MachineOperand::CreateImm(0)); 337239462Sdim Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 338239462Sdim true)); 339239462Sdim FBB = LastInst->getOperand(0).getMBB(); 340239462Sdim return false; 341193323Sed } 342218893Sdim 343193323Sed // If the block ends with two PPC:Bs, handle it. The second one is not 344193323Sed // executed, so remove it. 345218893Sdim if (SecondLastInst->getOpcode() == PPC::B && 346193323Sed LastInst->getOpcode() == PPC::B) { 347193323Sed if (!SecondLastInst->getOperand(0).isMBB()) 348193323Sed return true; 349193323Sed TBB = SecondLastInst->getOperand(0).getMBB(); 350193323Sed I = LastInst; 351193323Sed if (AllowModify) 352193323Sed I->eraseFromParent(); 353193323Sed return false; 354193323Sed } 355193323Sed 356193323Sed // Otherwise, can't handle this. 357193323Sed return true; 358193323Sed} 359193323Sed 360193323Sedunsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 361193323Sed MachineBasicBlock::iterator I = MBB.end(); 362193323Sed if (I == MBB.begin()) return 0; 363193323Sed --I; 364206083Srdivacky while (I->isDebugValue()) { 365206083Srdivacky if (I == MBB.begin()) 366206083Srdivacky return 0; 367206083Srdivacky --I; 368206083Srdivacky } 369239462Sdim if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC && 370239462Sdim I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ && 371239462Sdim I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ) 372193323Sed return 0; 373218893Sdim 374193323Sed // Remove the branch. 375193323Sed I->eraseFromParent(); 376218893Sdim 377193323Sed I = MBB.end(); 378193323Sed 379193323Sed if (I == MBB.begin()) return 1; 380193323Sed --I; 381239462Sdim if (I->getOpcode() != PPC::BCC && 382239462Sdim I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ && 383239462Sdim I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ) 384193323Sed return 1; 385218893Sdim 386193323Sed // Remove the branch. 387193323Sed I->eraseFromParent(); 388193323Sed return 2; 389193323Sed} 390193323Sed 391193323Sedunsigned 392193323SedPPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 393193323Sed MachineBasicBlock *FBB, 394210299Sed const SmallVectorImpl<MachineOperand> &Cond, 395210299Sed DebugLoc DL) const { 396193323Sed // Shouldn't be a fall through. 397193323Sed assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 398218893Sdim assert((Cond.size() == 2 || Cond.size() == 0) && 399193323Sed "PPC branch conditions have two components!"); 400218893Sdim 401239462Sdim bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); 402239462Sdim 403193323Sed // One-way branch. 404193323Sed if (FBB == 0) { 405193323Sed if (Cond.empty()) // Unconditional branch 406210299Sed BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); 407239462Sdim else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) 408239462Sdim BuildMI(&MBB, DL, get(Cond[0].getImm() ? 409239462Sdim (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : 410239462Sdim (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); 411193323Sed else // Conditional branch 412210299Sed BuildMI(&MBB, DL, get(PPC::BCC)) 413193323Sed .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 414193323Sed return 1; 415193323Sed } 416218893Sdim 417193323Sed // Two-way Conditional Branch. 418239462Sdim if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) 419239462Sdim BuildMI(&MBB, DL, get(Cond[0].getImm() ? 420239462Sdim (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : 421239462Sdim (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); 422239462Sdim else 423239462Sdim BuildMI(&MBB, DL, get(PPC::BCC)) 424239462Sdim .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 425210299Sed BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); 426193323Sed return 2; 427193323Sed} 428193323Sed 429251662Sdim// Select analysis. 430251662Sdimbool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB, 431251662Sdim const SmallVectorImpl<MachineOperand> &Cond, 432251662Sdim unsigned TrueReg, unsigned FalseReg, 433251662Sdim int &CondCycles, int &TrueCycles, int &FalseCycles) const { 434251662Sdim if (!TM.getSubtargetImpl()->hasISEL()) 435251662Sdim return false; 436251662Sdim 437251662Sdim if (Cond.size() != 2) 438251662Sdim return false; 439251662Sdim 440251662Sdim // If this is really a bdnz-like condition, then it cannot be turned into a 441251662Sdim // select. 442251662Sdim if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) 443251662Sdim return false; 444251662Sdim 445251662Sdim // Check register classes. 446251662Sdim const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 447251662Sdim const TargetRegisterClass *RC = 448251662Sdim RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 449251662Sdim if (!RC) 450251662Sdim return false; 451251662Sdim 452251662Sdim // isel is for regular integer GPRs only. 453251662Sdim if (!PPC::GPRCRegClass.hasSubClassEq(RC) && 454263508Sdim !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && 455263508Sdim !PPC::G8RCRegClass.hasSubClassEq(RC) && 456263508Sdim !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) 457251662Sdim return false; 458251662Sdim 459251662Sdim // FIXME: These numbers are for the A2, how well they work for other cores is 460251662Sdim // an open question. On the A2, the isel instruction has a 2-cycle latency 461251662Sdim // but single-cycle throughput. These numbers are used in combination with 462251662Sdim // the MispredictPenalty setting from the active SchedMachineModel. 463251662Sdim CondCycles = 1; 464251662Sdim TrueCycles = 1; 465251662Sdim FalseCycles = 1; 466251662Sdim 467251662Sdim return true; 468251662Sdim} 469251662Sdim 470251662Sdimvoid PPCInstrInfo::insertSelect(MachineBasicBlock &MBB, 471251662Sdim MachineBasicBlock::iterator MI, DebugLoc dl, 472251662Sdim unsigned DestReg, 473251662Sdim const SmallVectorImpl<MachineOperand> &Cond, 474251662Sdim unsigned TrueReg, unsigned FalseReg) const { 475251662Sdim assert(Cond.size() == 2 && 476251662Sdim "PPC branch conditions have two components!"); 477251662Sdim 478251662Sdim assert(TM.getSubtargetImpl()->hasISEL() && 479251662Sdim "Cannot insert select on target without ISEL support"); 480251662Sdim 481251662Sdim // Get the register classes. 482251662Sdim MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 483251662Sdim const TargetRegisterClass *RC = 484251662Sdim RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 485251662Sdim assert(RC && "TrueReg and FalseReg must have overlapping register classes"); 486263508Sdim 487263508Sdim bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) || 488263508Sdim PPC::G8RC_NOX0RegClass.hasSubClassEq(RC); 489263508Sdim assert((Is64Bit || 490263508Sdim PPC::GPRCRegClass.hasSubClassEq(RC) || 491263508Sdim PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && 492251662Sdim "isel is for regular integer GPRs only"); 493251662Sdim 494263508Sdim unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL; 495251662Sdim unsigned SelectPred = Cond[0].getImm(); 496251662Sdim 497251662Sdim unsigned SubIdx; 498251662Sdim bool SwapOps; 499251662Sdim switch (SelectPred) { 500251662Sdim default: llvm_unreachable("invalid predicate for isel"); 501251662Sdim case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break; 502251662Sdim case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break; 503251662Sdim case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break; 504251662Sdim case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break; 505251662Sdim case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break; 506251662Sdim case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break; 507251662Sdim case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break; 508251662Sdim case PPC::PRED_NU: SubIdx = PPC::sub_un; SwapOps = true; break; 509251662Sdim } 510251662Sdim 511251662Sdim unsigned FirstReg = SwapOps ? FalseReg : TrueReg, 512251662Sdim SecondReg = SwapOps ? TrueReg : FalseReg; 513251662Sdim 514251662Sdim // The first input register of isel cannot be r0. If it is a member 515251662Sdim // of a register class that can be r0, then copy it first (the 516251662Sdim // register allocator should eliminate the copy). 517251662Sdim if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || 518251662Sdim MRI.getRegClass(FirstReg)->contains(PPC::X0)) { 519251662Sdim const TargetRegisterClass *FirstRC = 520251662Sdim MRI.getRegClass(FirstReg)->contains(PPC::X0) ? 521251662Sdim &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass; 522251662Sdim unsigned OldFirstReg = FirstReg; 523251662Sdim FirstReg = MRI.createVirtualRegister(FirstRC); 524251662Sdim BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg) 525251662Sdim .addReg(OldFirstReg); 526251662Sdim } 527251662Sdim 528251662Sdim BuildMI(MBB, MI, dl, get(OpCode), DestReg) 529251662Sdim .addReg(FirstReg).addReg(SecondReg) 530251662Sdim .addReg(Cond[1].getReg(), 0, SubIdx); 531251662Sdim} 532251662Sdim 533210299Sedvoid PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 534210299Sed MachineBasicBlock::iterator I, DebugLoc DL, 535210299Sed unsigned DestReg, unsigned SrcReg, 536210299Sed bool KillSrc) const { 537210299Sed unsigned Opc; 538210299Sed if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) 539210299Sed Opc = PPC::OR; 540210299Sed else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) 541210299Sed Opc = PPC::OR8; 542210299Sed else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) 543210299Sed Opc = PPC::FMR; 544210299Sed else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) 545210299Sed Opc = PPC::MCRF; 546210299Sed else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) 547210299Sed Opc = PPC::VOR; 548210299Sed else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) 549210299Sed Opc = PPC::CROR; 550210299Sed else 551210299Sed llvm_unreachable("Impossible reg-to-reg copy"); 552193323Sed 553224145Sdim const MCInstrDesc &MCID = get(Opc); 554224145Sdim if (MCID.getNumOperands() == 3) 555224145Sdim BuildMI(MBB, I, DL, MCID, DestReg) 556210299Sed .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); 557210299Sed else 558224145Sdim BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); 559193323Sed} 560193323Sed 561234353Sdim// This function returns true if a CR spill is necessary and false otherwise. 562193323Sedbool 563193323SedPPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, 564193323Sed unsigned SrcReg, bool isKill, 565193323Sed int FrameIdx, 566193323Sed const TargetRegisterClass *RC, 567249423Sdim SmallVectorImpl<MachineInstr*> &NewMIs, 568249423Sdim bool &NonRI, bool &SpillsVRS) const{ 569249423Sdim // Note: If additional store instructions are added here, 570249423Sdim // update isStoreToStackSlot. 571249423Sdim 572206124Srdivacky DebugLoc DL; 573266715Sdim if (PPC::GPRCRegClass.hasSubClassEq(RC) || 574266715Sdim PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { 575249423Sdim NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 576249423Sdim .addReg(SrcReg, 577249423Sdim getKillRegState(isKill)), 578249423Sdim FrameIdx)); 579266715Sdim } else if (PPC::G8RCRegClass.hasSubClassEq(RC) || 580266715Sdim PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) { 581249423Sdim NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 582249423Sdim .addReg(SrcReg, 583249423Sdim getKillRegState(isKill)), 584249423Sdim FrameIdx)); 585239462Sdim } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { 586193323Sed NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) 587193323Sed .addReg(SrcReg, 588193323Sed getKillRegState(isKill)), 589193323Sed FrameIdx)); 590239462Sdim } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { 591193323Sed NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) 592193323Sed .addReg(SrcReg, 593193323Sed getKillRegState(isKill)), 594193323Sed FrameIdx)); 595239462Sdim } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { 596249423Sdim NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) 597249423Sdim .addReg(SrcReg, 598249423Sdim getKillRegState(isKill)), 599249423Sdim FrameIdx)); 600249423Sdim return true; 601239462Sdim } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { 602193323Sed // FIXME: We use CRi here because there is no mtcrf on a bit. Since the 603193323Sed // backend currently only uses CR1EQ as an individual bit, this should 604193323Sed // not cause any bug. If we need other uses of CR bits, the following 605193323Sed // code may be invalid. 606193323Sed unsigned Reg = 0; 607195340Sed if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || 608195340Sed SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) 609193323Sed Reg = PPC::CR0; 610195340Sed else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || 611195340Sed SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) 612193323Sed Reg = PPC::CR1; 613195340Sed else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || 614195340Sed SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) 615193323Sed Reg = PPC::CR2; 616195340Sed else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || 617195340Sed SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) 618193323Sed Reg = PPC::CR3; 619195340Sed else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || 620195340Sed SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) 621193323Sed Reg = PPC::CR4; 622195340Sed else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT || 623195340Sed SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) 624193323Sed Reg = PPC::CR5; 625195340Sed else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT || 626195340Sed SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) 627193323Sed Reg = PPC::CR6; 628195340Sed else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT || 629195340Sed SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN) 630193323Sed Reg = PPC::CR7; 631193323Sed 632218893Sdim return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx, 633249423Sdim &PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS); 634193323Sed 635239462Sdim } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { 636249423Sdim NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX)) 637249423Sdim .addReg(SrcReg, 638249423Sdim getKillRegState(isKill)), 639249423Sdim FrameIdx)); 640249423Sdim NonRI = true; 641249423Sdim } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) { 642249423Sdim assert(TM.getSubtargetImpl()->isDarwin() && 643249423Sdim "VRSAVE only needs spill/restore on Darwin"); 644249423Sdim NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE)) 645249423Sdim .addReg(SrcReg, 646249423Sdim getKillRegState(isKill)), 647249423Sdim FrameIdx)); 648249423Sdim SpillsVRS = true; 649193323Sed } else { 650198090Srdivacky llvm_unreachable("Unknown regclass!"); 651193323Sed } 652193323Sed 653193323Sed return false; 654193323Sed} 655193323Sed 656193323Sedvoid 657193323SedPPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 658193323Sed MachineBasicBlock::iterator MI, 659193323Sed unsigned SrcReg, bool isKill, int FrameIdx, 660208599Srdivacky const TargetRegisterClass *RC, 661208599Srdivacky const TargetRegisterInfo *TRI) const { 662193323Sed MachineFunction &MF = *MBB.getParent(); 663193323Sed SmallVector<MachineInstr*, 4> NewMIs; 664193323Sed 665249423Sdim PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 666249423Sdim FuncInfo->setHasSpills(); 667249423Sdim 668249423Sdim bool NonRI = false, SpillsVRS = false; 669249423Sdim if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs, 670249423Sdim NonRI, SpillsVRS)) 671193323Sed FuncInfo->setSpillsCR(); 672193323Sed 673249423Sdim if (SpillsVRS) 674249423Sdim FuncInfo->setSpillsVRSAVE(); 675249423Sdim 676249423Sdim if (NonRI) 677249423Sdim FuncInfo->setHasNonRISpills(); 678249423Sdim 679193323Sed for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 680193323Sed MBB.insert(MI, NewMIs[i]); 681212904Sdim 682212904Sdim const MachineFrameInfo &MFI = *MF.getFrameInfo(); 683212904Sdim MachineMemOperand *MMO = 684234353Sdim MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx), 685218893Sdim MachineMemOperand::MOStore, 686212904Sdim MFI.getObjectSize(FrameIdx), 687212904Sdim MFI.getObjectAlignment(FrameIdx)); 688212904Sdim NewMIs.back()->addMemOperand(MF, MMO); 689193323Sed} 690193323Sed 691234353Sdimbool 692193323SedPPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, 693193323Sed unsigned DestReg, int FrameIdx, 694193323Sed const TargetRegisterClass *RC, 695249423Sdim SmallVectorImpl<MachineInstr*> &NewMIs, 696249423Sdim bool &NonRI, bool &SpillsVRS) const{ 697249423Sdim // Note: If additional load instructions are added here, 698249423Sdim // update isLoadFromStackSlot. 699249423Sdim 700266715Sdim if (PPC::GPRCRegClass.hasSubClassEq(RC) || 701266715Sdim PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { 702249423Sdim NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 703249423Sdim DestReg), FrameIdx)); 704266715Sdim } else if (PPC::G8RCRegClass.hasSubClassEq(RC) || 705266715Sdim PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) { 706249423Sdim NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg), 707249423Sdim FrameIdx)); 708239462Sdim } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { 709193323Sed NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg), 710193323Sed FrameIdx)); 711239462Sdim } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { 712193323Sed NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg), 713193323Sed FrameIdx)); 714239462Sdim } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { 715249423Sdim NewMIs.push_back(addFrameReference(BuildMI(MF, DL, 716249423Sdim get(PPC::RESTORE_CR), DestReg), 717249423Sdim FrameIdx)); 718249423Sdim return true; 719239462Sdim } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { 720218893Sdim 721193323Sed unsigned Reg = 0; 722195340Sed if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT || 723195340Sed DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN) 724193323Sed Reg = PPC::CR0; 725195340Sed else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT || 726195340Sed DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN) 727193323Sed Reg = PPC::CR1; 728195340Sed else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT || 729195340Sed DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN) 730193323Sed Reg = PPC::CR2; 731195340Sed else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT || 732195340Sed DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN) 733193323Sed Reg = PPC::CR3; 734195340Sed else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT || 735195340Sed DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN) 736193323Sed Reg = PPC::CR4; 737195340Sed else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT || 738195340Sed DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN) 739193323Sed Reg = PPC::CR5; 740195340Sed else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT || 741195340Sed DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN) 742193323Sed Reg = PPC::CR6; 743195340Sed else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT || 744195340Sed DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN) 745193323Sed Reg = PPC::CR7; 746193323Sed 747218893Sdim return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx, 748249423Sdim &PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS); 749193323Sed 750239462Sdim } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { 751249423Sdim NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg), 752249423Sdim FrameIdx)); 753249423Sdim NonRI = true; 754249423Sdim } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) { 755249423Sdim assert(TM.getSubtargetImpl()->isDarwin() && 756249423Sdim "VRSAVE only needs spill/restore on Darwin"); 757249423Sdim NewMIs.push_back(addFrameReference(BuildMI(MF, DL, 758249423Sdim get(PPC::RESTORE_VRSAVE), 759249423Sdim DestReg), 760249423Sdim FrameIdx)); 761249423Sdim SpillsVRS = true; 762193323Sed } else { 763198090Srdivacky llvm_unreachable("Unknown regclass!"); 764193323Sed } 765234353Sdim 766234353Sdim return false; 767193323Sed} 768193323Sed 769193323Sedvoid 770193323SedPPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 771193323Sed MachineBasicBlock::iterator MI, 772193323Sed unsigned DestReg, int FrameIdx, 773208599Srdivacky const TargetRegisterClass *RC, 774208599Srdivacky const TargetRegisterInfo *TRI) const { 775193323Sed MachineFunction &MF = *MBB.getParent(); 776193323Sed SmallVector<MachineInstr*, 4> NewMIs; 777206124Srdivacky DebugLoc DL; 778193323Sed if (MI != MBB.end()) DL = MI->getDebugLoc(); 779249423Sdim 780249423Sdim PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 781249423Sdim FuncInfo->setHasSpills(); 782249423Sdim 783249423Sdim bool NonRI = false, SpillsVRS = false; 784249423Sdim if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs, 785249423Sdim NonRI, SpillsVRS)) 786234353Sdim FuncInfo->setSpillsCR(); 787249423Sdim 788249423Sdim if (SpillsVRS) 789249423Sdim FuncInfo->setSpillsVRSAVE(); 790249423Sdim 791249423Sdim if (NonRI) 792249423Sdim FuncInfo->setHasNonRISpills(); 793249423Sdim 794193323Sed for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 795193323Sed MBB.insert(MI, NewMIs[i]); 796212904Sdim 797212904Sdim const MachineFrameInfo &MFI = *MF.getFrameInfo(); 798212904Sdim MachineMemOperand *MMO = 799234353Sdim MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx), 800218893Sdim MachineMemOperand::MOLoad, 801212904Sdim MFI.getObjectSize(FrameIdx), 802212904Sdim MFI.getObjectAlignment(FrameIdx)); 803212904Sdim NewMIs.back()->addMemOperand(MF, MMO); 804193323Sed} 805193323Sed 806193323Sedbool PPCInstrInfo:: 807193323SedReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 808193323Sed assert(Cond.size() == 2 && "Invalid PPC branch opcode!"); 809239462Sdim if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR) 810239462Sdim Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0); 811239462Sdim else 812239462Sdim // Leave the CR# the same, but invert the condition. 813239462Sdim Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); 814193323Sed return false; 815193323Sed} 816193323Sed 817251662Sdimbool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 818251662Sdim unsigned Reg, MachineRegisterInfo *MRI) const { 819251662Sdim // For some instructions, it is legal to fold ZERO into the RA register field. 820251662Sdim // A zero immediate should always be loaded with a single li. 821251662Sdim unsigned DefOpc = DefMI->getOpcode(); 822251662Sdim if (DefOpc != PPC::LI && DefOpc != PPC::LI8) 823251662Sdim return false; 824251662Sdim if (!DefMI->getOperand(1).isImm()) 825251662Sdim return false; 826251662Sdim if (DefMI->getOperand(1).getImm() != 0) 827251662Sdim return false; 828251662Sdim 829251662Sdim // Note that we cannot here invert the arguments of an isel in order to fold 830251662Sdim // a ZERO into what is presented as the second argument. All we have here 831251662Sdim // is the condition bit, and that might come from a CR-logical bit operation. 832251662Sdim 833251662Sdim const MCInstrDesc &UseMCID = UseMI->getDesc(); 834251662Sdim 835251662Sdim // Only fold into real machine instructions. 836251662Sdim if (UseMCID.isPseudo()) 837251662Sdim return false; 838251662Sdim 839251662Sdim unsigned UseIdx; 840251662Sdim for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx) 841251662Sdim if (UseMI->getOperand(UseIdx).isReg() && 842251662Sdim UseMI->getOperand(UseIdx).getReg() == Reg) 843251662Sdim break; 844251662Sdim 845251662Sdim assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI"); 846251662Sdim assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg"); 847251662Sdim 848251662Sdim const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx]; 849251662Sdim 850251662Sdim // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0 851251662Sdim // register (which might also be specified as a pointer class kind). 852251662Sdim if (UseInfo->isLookupPtrRegClass()) { 853251662Sdim if (UseInfo->RegClass /* Kind */ != 1) 854251662Sdim return false; 855251662Sdim } else { 856251662Sdim if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID && 857251662Sdim UseInfo->RegClass != PPC::G8RC_NOX0RegClassID) 858251662Sdim return false; 859251662Sdim } 860251662Sdim 861251662Sdim // Make sure this is not tied to an output register (or otherwise 862251662Sdim // constrained). This is true for ST?UX registers, for example, which 863251662Sdim // are tied to their output registers. 864251662Sdim if (UseInfo->Constraints != 0) 865251662Sdim return false; 866251662Sdim 867251662Sdim unsigned ZeroReg; 868251662Sdim if (UseInfo->isLookupPtrRegClass()) { 869251662Sdim bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); 870251662Sdim ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; 871251662Sdim } else { 872251662Sdim ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? 873251662Sdim PPC::ZERO8 : PPC::ZERO; 874251662Sdim } 875251662Sdim 876251662Sdim bool DeleteDef = MRI->hasOneNonDBGUse(Reg); 877251662Sdim UseMI->getOperand(UseIdx).setReg(ZeroReg); 878251662Sdim 879251662Sdim if (DeleteDef) 880251662Sdim DefMI->eraseFromParent(); 881251662Sdim 882251662Sdim return true; 883251662Sdim} 884251662Sdim 885251662Sdimstatic bool MBBDefinesCTR(MachineBasicBlock &MBB) { 886251662Sdim for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end(); 887251662Sdim I != IE; ++I) 888251662Sdim if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8)) 889251662Sdim return true; 890251662Sdim return false; 891251662Sdim} 892251662Sdim 893251662Sdim// We should make sure that, if we're going to predicate both sides of a 894251662Sdim// condition (a diamond), that both sides don't define the counter register. We 895251662Sdim// can predicate counter-decrement-based branches, but while that predicates 896251662Sdim// the branching, it does not predicate the counter decrement. If we tried to 897251662Sdim// merge the triangle into one predicated block, we'd decrement the counter 898251662Sdim// twice. 899251662Sdimbool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB, 900251662Sdim unsigned NumT, unsigned ExtraT, 901251662Sdim MachineBasicBlock &FMBB, 902251662Sdim unsigned NumF, unsigned ExtraF, 903251662Sdim const BranchProbability &Probability) const { 904251662Sdim return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB)); 905251662Sdim} 906251662Sdim 907251662Sdim 908251662Sdimbool PPCInstrInfo::isPredicated(const MachineInstr *MI) const { 909251662Sdim // The predicated branches are identified by their type, not really by the 910251662Sdim // explicit presence of a predicate. Furthermore, some of them can be 911251662Sdim // predicated more than once. Because if conversion won't try to predicate 912251662Sdim // any instruction which already claims to be predicated (by returning true 913251662Sdim // here), always return false. In doing so, we let isPredicable() be the 914251662Sdim // final word on whether not the instruction can be (further) predicated. 915251662Sdim 916251662Sdim return false; 917251662Sdim} 918251662Sdim 919251662Sdimbool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 920251662Sdim if (!MI->isTerminator()) 921251662Sdim return false; 922251662Sdim 923251662Sdim // Conditional branch is a special case. 924251662Sdim if (MI->isBranch() && !MI->isBarrier()) 925251662Sdim return true; 926251662Sdim 927251662Sdim return !isPredicated(MI); 928251662Sdim} 929251662Sdim 930251662Sdimbool PPCInstrInfo::PredicateInstruction( 931251662Sdim MachineInstr *MI, 932251662Sdim const SmallVectorImpl<MachineOperand> &Pred) const { 933251662Sdim unsigned OpC = MI->getOpcode(); 934251662Sdim if (OpC == PPC::BLR) { 935251662Sdim if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { 936251662Sdim bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); 937251662Sdim MI->setDesc(get(Pred[0].getImm() ? 938251662Sdim (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) : 939251662Sdim (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR))); 940251662Sdim } else { 941251662Sdim MI->setDesc(get(PPC::BCLR)); 942251662Sdim MachineInstrBuilder(*MI->getParent()->getParent(), MI) 943251662Sdim .addImm(Pred[0].getImm()) 944251662Sdim .addReg(Pred[1].getReg()); 945251662Sdim } 946251662Sdim 947251662Sdim return true; 948251662Sdim } else if (OpC == PPC::B) { 949251662Sdim if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { 950251662Sdim bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); 951251662Sdim MI->setDesc(get(Pred[0].getImm() ? 952251662Sdim (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : 953251662Sdim (isPPC64 ? PPC::BDZ8 : PPC::BDZ))); 954251662Sdim } else { 955251662Sdim MachineBasicBlock *MBB = MI->getOperand(0).getMBB(); 956251662Sdim MI->RemoveOperand(0); 957251662Sdim 958251662Sdim MI->setDesc(get(PPC::BCC)); 959251662Sdim MachineInstrBuilder(*MI->getParent()->getParent(), MI) 960251662Sdim .addImm(Pred[0].getImm()) 961251662Sdim .addReg(Pred[1].getReg()) 962251662Sdim .addMBB(MBB); 963251662Sdim } 964251662Sdim 965251662Sdim return true; 966251662Sdim } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || 967251662Sdim OpC == PPC::BCTRL || OpC == PPC::BCTRL8) { 968251662Sdim if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) 969251662Sdim llvm_unreachable("Cannot predicate bctr[l] on the ctr register"); 970251662Sdim 971251662Sdim bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8; 972251662Sdim bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); 973251662Sdim MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) : 974251662Sdim (setLR ? PPC::BCCTRL : PPC::BCCTR))); 975251662Sdim MachineInstrBuilder(*MI->getParent()->getParent(), MI) 976251662Sdim .addImm(Pred[0].getImm()) 977251662Sdim .addReg(Pred[1].getReg()); 978251662Sdim return true; 979251662Sdim } 980251662Sdim 981251662Sdim return false; 982251662Sdim} 983251662Sdim 984251662Sdimbool PPCInstrInfo::SubsumesPredicate( 985251662Sdim const SmallVectorImpl<MachineOperand> &Pred1, 986251662Sdim const SmallVectorImpl<MachineOperand> &Pred2) const { 987251662Sdim assert(Pred1.size() == 2 && "Invalid PPC first predicate"); 988251662Sdim assert(Pred2.size() == 2 && "Invalid PPC second predicate"); 989251662Sdim 990251662Sdim if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR) 991251662Sdim return false; 992251662Sdim if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR) 993251662Sdim return false; 994251662Sdim 995263508Sdim // P1 can only subsume P2 if they test the same condition register. 996263508Sdim if (Pred1[1].getReg() != Pred2[1].getReg()) 997263508Sdim return false; 998263508Sdim 999251662Sdim PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm(); 1000251662Sdim PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm(); 1001251662Sdim 1002251662Sdim if (P1 == P2) 1003251662Sdim return true; 1004251662Sdim 1005251662Sdim // Does P1 subsume P2, e.g. GE subsumes GT. 1006251662Sdim if (P1 == PPC::PRED_LE && 1007251662Sdim (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ)) 1008251662Sdim return true; 1009251662Sdim if (P1 == PPC::PRED_GE && 1010251662Sdim (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ)) 1011251662Sdim return true; 1012251662Sdim 1013251662Sdim return false; 1014251662Sdim} 1015251662Sdim 1016251662Sdimbool PPCInstrInfo::DefinesPredicate(MachineInstr *MI, 1017251662Sdim std::vector<MachineOperand> &Pred) const { 1018251662Sdim // Note: At the present time, the contents of Pred from this function is 1019251662Sdim // unused by IfConversion. This implementation follows ARM by pushing the 1020251662Sdim // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of 1021251662Sdim // predicate, instructions defining CTR or CTR8 are also included as 1022251662Sdim // predicate-defining instructions. 1023251662Sdim 1024251662Sdim const TargetRegisterClass *RCs[] = 1025251662Sdim { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass, 1026251662Sdim &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass }; 1027251662Sdim 1028251662Sdim bool Found = false; 1029251662Sdim for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1030251662Sdim const MachineOperand &MO = MI->getOperand(i); 1031251662Sdim for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) { 1032251662Sdim const TargetRegisterClass *RC = RCs[c]; 1033251662Sdim if (MO.isReg()) { 1034251662Sdim if (MO.isDef() && RC->contains(MO.getReg())) { 1035251662Sdim Pred.push_back(MO); 1036251662Sdim Found = true; 1037251662Sdim } 1038251662Sdim } else if (MO.isRegMask()) { 1039251662Sdim for (TargetRegisterClass::iterator I = RC->begin(), 1040251662Sdim IE = RC->end(); I != IE; ++I) 1041251662Sdim if (MO.clobbersPhysReg(*I)) { 1042251662Sdim Pred.push_back(MO); 1043251662Sdim Found = true; 1044251662Sdim } 1045251662Sdim } 1046251662Sdim } 1047251662Sdim } 1048251662Sdim 1049251662Sdim return Found; 1050251662Sdim} 1051251662Sdim 1052251662Sdimbool PPCInstrInfo::isPredicable(MachineInstr *MI) const { 1053251662Sdim unsigned OpC = MI->getOpcode(); 1054251662Sdim switch (OpC) { 1055251662Sdim default: 1056251662Sdim return false; 1057251662Sdim case PPC::B: 1058251662Sdim case PPC::BLR: 1059251662Sdim case PPC::BCTR: 1060251662Sdim case PPC::BCTR8: 1061251662Sdim case PPC::BCTRL: 1062251662Sdim case PPC::BCTRL8: 1063251662Sdim return true; 1064251662Sdim } 1065251662Sdim} 1066251662Sdim 1067251662Sdimbool PPCInstrInfo::analyzeCompare(const MachineInstr *MI, 1068251662Sdim unsigned &SrcReg, unsigned &SrcReg2, 1069251662Sdim int &Mask, int &Value) const { 1070251662Sdim unsigned Opc = MI->getOpcode(); 1071251662Sdim 1072251662Sdim switch (Opc) { 1073251662Sdim default: return false; 1074251662Sdim case PPC::CMPWI: 1075251662Sdim case PPC::CMPLWI: 1076251662Sdim case PPC::CMPDI: 1077251662Sdim case PPC::CMPLDI: 1078251662Sdim SrcReg = MI->getOperand(1).getReg(); 1079251662Sdim SrcReg2 = 0; 1080251662Sdim Value = MI->getOperand(2).getImm(); 1081251662Sdim Mask = 0xFFFF; 1082251662Sdim return true; 1083251662Sdim case PPC::CMPW: 1084251662Sdim case PPC::CMPLW: 1085251662Sdim case PPC::CMPD: 1086251662Sdim case PPC::CMPLD: 1087251662Sdim case PPC::FCMPUS: 1088251662Sdim case PPC::FCMPUD: 1089251662Sdim SrcReg = MI->getOperand(1).getReg(); 1090251662Sdim SrcReg2 = MI->getOperand(2).getReg(); 1091251662Sdim return true; 1092251662Sdim } 1093251662Sdim} 1094251662Sdim 1095251662Sdimbool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr, 1096251662Sdim unsigned SrcReg, unsigned SrcReg2, 1097251662Sdim int Mask, int Value, 1098251662Sdim const MachineRegisterInfo *MRI) const { 1099251662Sdim if (DisableCmpOpt) 1100251662Sdim return false; 1101251662Sdim 1102251662Sdim int OpC = CmpInstr->getOpcode(); 1103251662Sdim unsigned CRReg = CmpInstr->getOperand(0).getReg(); 1104251662Sdim 1105251662Sdim // FP record forms set CR1 based on the execption status bits, not a 1106251662Sdim // comparison with zero. 1107251662Sdim if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD) 1108251662Sdim return false; 1109251662Sdim 1110251662Sdim // The record forms set the condition register based on a signed comparison 1111251662Sdim // with zero (so says the ISA manual). This is not as straightforward as it 1112251662Sdim // seems, however, because this is always a 64-bit comparison on PPC64, even 1113251662Sdim // for instructions that are 32-bit in nature (like slw for example). 1114251662Sdim // So, on PPC32, for unsigned comparisons, we can use the record forms only 1115251662Sdim // for equality checks (as those don't depend on the sign). On PPC64, 1116251662Sdim // we are restricted to equality for unsigned 64-bit comparisons and for 1117251662Sdim // signed 32-bit comparisons the applicability is more restricted. 1118251662Sdim bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); 1119251662Sdim bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW; 1120251662Sdim bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW; 1121251662Sdim bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD; 1122251662Sdim 1123251662Sdim // Get the unique definition of SrcReg. 1124251662Sdim MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); 1125251662Sdim if (!MI) return false; 1126251662Sdim int MIOpC = MI->getOpcode(); 1127251662Sdim 1128251662Sdim bool equalityOnly = false; 1129251662Sdim bool noSub = false; 1130251662Sdim if (isPPC64) { 1131251662Sdim if (is32BitSignedCompare) { 1132251662Sdim // We can perform this optimization only if MI is sign-extending. 1133251662Sdim if (MIOpC == PPC::SRAW || MIOpC == PPC::SRAWo || 1134251662Sdim MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo || 1135251662Sdim MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo || 1136251662Sdim MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo || 1137251662Sdim MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) { 1138251662Sdim noSub = true; 1139251662Sdim } else 1140251662Sdim return false; 1141251662Sdim } else if (is32BitUnsignedCompare) { 1142251662Sdim // We can perform this optimization, equality only, if MI is 1143251662Sdim // zero-extending. 1144251662Sdim if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo || 1145251662Sdim MIOpC == PPC::SLW || MIOpC == PPC::SLWo || 1146251662Sdim MIOpC == PPC::SRW || MIOpC == PPC::SRWo) { 1147251662Sdim noSub = true; 1148251662Sdim equalityOnly = true; 1149251662Sdim } else 1150251662Sdim return false; 1151251662Sdim } else 1152251662Sdim equalityOnly = is64BitUnsignedCompare; 1153251662Sdim } else 1154251662Sdim equalityOnly = is32BitUnsignedCompare; 1155251662Sdim 1156251662Sdim if (equalityOnly) { 1157251662Sdim // We need to check the uses of the condition register in order to reject 1158251662Sdim // non-equality comparisons. 1159251662Sdim for (MachineRegisterInfo::use_iterator I = MRI->use_begin(CRReg), 1160251662Sdim IE = MRI->use_end(); I != IE; ++I) { 1161251662Sdim MachineInstr *UseMI = &*I; 1162251662Sdim if (UseMI->getOpcode() == PPC::BCC) { 1163251662Sdim unsigned Pred = UseMI->getOperand(0).getImm(); 1164263508Sdim if (Pred != PPC::PRED_EQ && Pred != PPC::PRED_NE) 1165263508Sdim return false; 1166251662Sdim } else if (UseMI->getOpcode() == PPC::ISEL || 1167251662Sdim UseMI->getOpcode() == PPC::ISEL8) { 1168251662Sdim unsigned SubIdx = UseMI->getOperand(3).getSubReg(); 1169263508Sdim if (SubIdx != PPC::sub_eq) 1170263508Sdim return false; 1171251662Sdim } else 1172251662Sdim return false; 1173251662Sdim } 1174251662Sdim } 1175251662Sdim 1176263508Sdim MachineBasicBlock::iterator I = CmpInstr; 1177251662Sdim 1178251662Sdim // Scan forward to find the first use of the compare. 1179251662Sdim for (MachineBasicBlock::iterator EL = CmpInstr->getParent()->end(); 1180251662Sdim I != EL; ++I) { 1181251662Sdim bool FoundUse = false; 1182251662Sdim for (MachineRegisterInfo::use_iterator J = MRI->use_begin(CRReg), 1183251662Sdim JE = MRI->use_end(); J != JE; ++J) 1184251662Sdim if (&*J == &*I) { 1185251662Sdim FoundUse = true; 1186251662Sdim break; 1187251662Sdim } 1188251662Sdim 1189251662Sdim if (FoundUse) 1190251662Sdim break; 1191251662Sdim } 1192251662Sdim 1193251662Sdim // There are two possible candidates which can be changed to set CR[01]. 1194251662Sdim // One is MI, the other is a SUB instruction. 1195251662Sdim // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1). 1196251662Sdim MachineInstr *Sub = NULL; 1197251662Sdim if (SrcReg2 != 0) 1198251662Sdim // MI is not a candidate for CMPrr. 1199251662Sdim MI = NULL; 1200251662Sdim // FIXME: Conservatively refuse to convert an instruction which isn't in the 1201251662Sdim // same BB as the comparison. This is to allow the check below to avoid calls 1202251662Sdim // (and other explicit clobbers); instead we should really check for these 1203251662Sdim // more explicitly (in at least a few predecessors). 1204251662Sdim else if (MI->getParent() != CmpInstr->getParent() || Value != 0) { 1205251662Sdim // PPC does not have a record-form SUBri. 1206251662Sdim return false; 1207251662Sdim } 1208251662Sdim 1209251662Sdim // Search for Sub. 1210251662Sdim const TargetRegisterInfo *TRI = &getRegisterInfo(); 1211251662Sdim --I; 1212263508Sdim 1213263508Sdim // Get ready to iterate backward from CmpInstr. 1214263508Sdim MachineBasicBlock::iterator E = MI, 1215263508Sdim B = CmpInstr->getParent()->begin(); 1216263508Sdim 1217251662Sdim for (; I != E && !noSub; --I) { 1218251662Sdim const MachineInstr &Instr = *I; 1219251662Sdim unsigned IOpC = Instr.getOpcode(); 1220251662Sdim 1221251662Sdim if (&*I != CmpInstr && ( 1222251662Sdim Instr.modifiesRegister(PPC::CR0, TRI) || 1223251662Sdim Instr.readsRegister(PPC::CR0, TRI))) 1224251662Sdim // This instruction modifies or uses the record condition register after 1225251662Sdim // the one we want to change. While we could do this transformation, it 1226251662Sdim // would likely not be profitable. This transformation removes one 1227251662Sdim // instruction, and so even forcing RA to generate one move probably 1228251662Sdim // makes it unprofitable. 1229251662Sdim return false; 1230251662Sdim 1231251662Sdim // Check whether CmpInstr can be made redundant by the current instruction. 1232251662Sdim if ((OpC == PPC::CMPW || OpC == PPC::CMPLW || 1233251662Sdim OpC == PPC::CMPD || OpC == PPC::CMPLD) && 1234251662Sdim (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) && 1235251662Sdim ((Instr.getOperand(1).getReg() == SrcReg && 1236251662Sdim Instr.getOperand(2).getReg() == SrcReg2) || 1237251662Sdim (Instr.getOperand(1).getReg() == SrcReg2 && 1238251662Sdim Instr.getOperand(2).getReg() == SrcReg))) { 1239251662Sdim Sub = &*I; 1240251662Sdim break; 1241251662Sdim } 1242251662Sdim 1243251662Sdim if (I == B) 1244251662Sdim // The 'and' is below the comparison instruction. 1245251662Sdim return false; 1246251662Sdim } 1247251662Sdim 1248251662Sdim // Return false if no candidates exist. 1249251662Sdim if (!MI && !Sub) 1250251662Sdim return false; 1251251662Sdim 1252251662Sdim // The single candidate is called MI. 1253251662Sdim if (!MI) MI = Sub; 1254251662Sdim 1255251662Sdim int NewOpC = -1; 1256251662Sdim MIOpC = MI->getOpcode(); 1257251662Sdim if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8) 1258251662Sdim NewOpC = MIOpC; 1259251662Sdim else { 1260251662Sdim NewOpC = PPC::getRecordFormOpcode(MIOpC); 1261251662Sdim if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1) 1262251662Sdim NewOpC = MIOpC; 1263251662Sdim } 1264251662Sdim 1265251662Sdim // FIXME: On the non-embedded POWER architectures, only some of the record 1266251662Sdim // forms are fast, and we should use only the fast ones. 1267251662Sdim 1268251662Sdim // The defining instruction has a record form (or is already a record 1269251662Sdim // form). It is possible, however, that we'll need to reverse the condition 1270251662Sdim // code of the users. 1271251662Sdim if (NewOpC == -1) 1272251662Sdim return false; 1273251662Sdim 1274251662Sdim SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate; 1275251662Sdim SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate; 1276251662Sdim 1277251662Sdim // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP 1278251662Sdim // needs to be updated to be based on SUB. Push the condition code 1279251662Sdim // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the 1280251662Sdim // condition code of these operands will be modified. 1281251662Sdim bool ShouldSwap = false; 1282251662Sdim if (Sub) { 1283251662Sdim ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 1284251662Sdim Sub->getOperand(2).getReg() == SrcReg; 1285251662Sdim 1286251662Sdim // The operands to subf are the opposite of sub, so only in the fixed-point 1287251662Sdim // case, invert the order. 1288251662Sdim ShouldSwap = !ShouldSwap; 1289251662Sdim } 1290251662Sdim 1291251662Sdim if (ShouldSwap) 1292251662Sdim for (MachineRegisterInfo::use_iterator I = MRI->use_begin(CRReg), 1293251662Sdim IE = MRI->use_end(); I != IE; ++I) { 1294251662Sdim MachineInstr *UseMI = &*I; 1295251662Sdim if (UseMI->getOpcode() == PPC::BCC) { 1296251662Sdim PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm(); 1297251662Sdim assert((!equalityOnly || 1298251662Sdim Pred == PPC::PRED_EQ || Pred == PPC::PRED_NE) && 1299251662Sdim "Invalid predicate for equality-only optimization"); 1300251662Sdim PredsToUpdate.push_back(std::make_pair(&((*I).getOperand(0)), 1301251662Sdim PPC::getSwappedPredicate(Pred))); 1302251662Sdim } else if (UseMI->getOpcode() == PPC::ISEL || 1303251662Sdim UseMI->getOpcode() == PPC::ISEL8) { 1304251662Sdim unsigned NewSubReg = UseMI->getOperand(3).getSubReg(); 1305251662Sdim assert((!equalityOnly || NewSubReg == PPC::sub_eq) && 1306251662Sdim "Invalid CR bit for equality-only optimization"); 1307251662Sdim 1308251662Sdim if (NewSubReg == PPC::sub_lt) 1309251662Sdim NewSubReg = PPC::sub_gt; 1310251662Sdim else if (NewSubReg == PPC::sub_gt) 1311251662Sdim NewSubReg = PPC::sub_lt; 1312251662Sdim 1313251662Sdim SubRegsToUpdate.push_back(std::make_pair(&((*I).getOperand(3)), 1314251662Sdim NewSubReg)); 1315251662Sdim } else // We need to abort on a user we don't understand. 1316251662Sdim return false; 1317251662Sdim } 1318251662Sdim 1319251662Sdim // Create a new virtual register to hold the value of the CR set by the 1320251662Sdim // record-form instruction. If the instruction was not previously in 1321251662Sdim // record form, then set the kill flag on the CR. 1322251662Sdim CmpInstr->eraseFromParent(); 1323251662Sdim 1324251662Sdim MachineBasicBlock::iterator MII = MI; 1325251662Sdim BuildMI(*MI->getParent(), llvm::next(MII), MI->getDebugLoc(), 1326251662Sdim get(TargetOpcode::COPY), CRReg) 1327251662Sdim .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0); 1328251662Sdim 1329251662Sdim if (MIOpC != NewOpC) { 1330251662Sdim // We need to be careful here: we're replacing one instruction with 1331251662Sdim // another, and we need to make sure that we get all of the right 1332251662Sdim // implicit uses and defs. On the other hand, the caller may be holding 1333251662Sdim // an iterator to this instruction, and so we can't delete it (this is 1334251662Sdim // specifically the case if this is the instruction directly after the 1335251662Sdim // compare). 1336251662Sdim 1337251662Sdim const MCInstrDesc &NewDesc = get(NewOpC); 1338251662Sdim MI->setDesc(NewDesc); 1339251662Sdim 1340251662Sdim if (NewDesc.ImplicitDefs) 1341251662Sdim for (const uint16_t *ImpDefs = NewDesc.getImplicitDefs(); 1342251662Sdim *ImpDefs; ++ImpDefs) 1343251662Sdim if (!MI->definesRegister(*ImpDefs)) 1344251662Sdim MI->addOperand(*MI->getParent()->getParent(), 1345251662Sdim MachineOperand::CreateReg(*ImpDefs, true, true)); 1346251662Sdim if (NewDesc.ImplicitUses) 1347251662Sdim for (const uint16_t *ImpUses = NewDesc.getImplicitUses(); 1348251662Sdim *ImpUses; ++ImpUses) 1349251662Sdim if (!MI->readsRegister(*ImpUses)) 1350251662Sdim MI->addOperand(*MI->getParent()->getParent(), 1351251662Sdim MachineOperand::CreateReg(*ImpUses, false, true)); 1352251662Sdim } 1353251662Sdim 1354251662Sdim // Modify the condition code of operands in OperandsToUpdate. 1355251662Sdim // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to 1356251662Sdim // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 1357251662Sdim for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++) 1358251662Sdim PredsToUpdate[i].first->setImm(PredsToUpdate[i].second); 1359251662Sdim 1360251662Sdim for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++) 1361251662Sdim SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second); 1362251662Sdim 1363251662Sdim return true; 1364251662Sdim} 1365251662Sdim 1366193323Sed/// GetInstSize - Return the number of bytes of code the specified 1367193323Sed/// instruction may be. This returns the maximum number of bytes. 1368193323Sed/// 1369193323Sedunsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 1370193323Sed switch (MI->getOpcode()) { 1371193323Sed case PPC::INLINEASM: { // Inline Asm: Variable size. 1372193323Sed const MachineFunction *MF = MI->getParent()->getParent(); 1373193323Sed const char *AsmStr = MI->getOperand(0).getSymbolName(); 1374198090Srdivacky return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); 1375193323Sed } 1376212904Sdim case PPC::PROLOG_LABEL: 1377193323Sed case PPC::EH_LABEL: 1378193323Sed case PPC::GC_LABEL: 1379207618Srdivacky case PPC::DBG_VALUE: 1380193323Sed return 0; 1381249423Sdim case PPC::BL8_NOP: 1382249423Sdim case PPC::BLA8_NOP: 1383234353Sdim return 8; 1384193323Sed default: 1385193323Sed return 4; // PowerPC instructions are all 4 bytes 1386193323Sed } 1387193323Sed} 1388251662Sdim 1389251662Sdim#undef DEBUG_TYPE 1390251662Sdim#define DEBUG_TYPE "ppc-early-ret" 1391251662SdimSTATISTIC(NumBCLR, "Number of early conditional returns"); 1392251662SdimSTATISTIC(NumBLR, "Number of early returns"); 1393251662Sdim 1394251662Sdimnamespace llvm { 1395251662Sdim void initializePPCEarlyReturnPass(PassRegistry&); 1396251662Sdim} 1397251662Sdim 1398251662Sdimnamespace { 1399251662Sdim // PPCEarlyReturn pass - For simple functions without epilogue code, move 1400251662Sdim // returns up, and create conditional returns, to avoid unnecessary 1401251662Sdim // branch-to-blr sequences. 1402251662Sdim struct PPCEarlyReturn : public MachineFunctionPass { 1403251662Sdim static char ID; 1404251662Sdim PPCEarlyReturn() : MachineFunctionPass(ID) { 1405251662Sdim initializePPCEarlyReturnPass(*PassRegistry::getPassRegistry()); 1406251662Sdim } 1407251662Sdim 1408251662Sdim const PPCTargetMachine *TM; 1409251662Sdim const PPCInstrInfo *TII; 1410251662Sdim 1411251662Sdimprotected: 1412251662Sdim bool processBlock(MachineBasicBlock &ReturnMBB) { 1413251662Sdim bool Changed = false; 1414251662Sdim 1415251662Sdim MachineBasicBlock::iterator I = ReturnMBB.begin(); 1416251662Sdim I = ReturnMBB.SkipPHIsAndLabels(I); 1417251662Sdim 1418251662Sdim // The block must be essentially empty except for the blr. 1419251662Sdim if (I == ReturnMBB.end() || I->getOpcode() != PPC::BLR || 1420251662Sdim I != ReturnMBB.getLastNonDebugInstr()) 1421251662Sdim return Changed; 1422251662Sdim 1423251662Sdim SmallVector<MachineBasicBlock*, 8> PredToRemove; 1424251662Sdim for (MachineBasicBlock::pred_iterator PI = ReturnMBB.pred_begin(), 1425251662Sdim PIE = ReturnMBB.pred_end(); PI != PIE; ++PI) { 1426251662Sdim bool OtherReference = false, BlockChanged = false; 1427251662Sdim for (MachineBasicBlock::iterator J = (*PI)->getLastNonDebugInstr();;) { 1428251662Sdim if (J->getOpcode() == PPC::B) { 1429251662Sdim if (J->getOperand(0).getMBB() == &ReturnMBB) { 1430251662Sdim // This is an unconditional branch to the return. Replace the 1431251662Sdim // branch with a blr. 1432251662Sdim BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BLR)); 1433251662Sdim MachineBasicBlock::iterator K = J--; 1434251662Sdim K->eraseFromParent(); 1435251662Sdim BlockChanged = true; 1436251662Sdim ++NumBLR; 1437251662Sdim continue; 1438251662Sdim } 1439251662Sdim } else if (J->getOpcode() == PPC::BCC) { 1440251662Sdim if (J->getOperand(2).getMBB() == &ReturnMBB) { 1441251662Sdim // This is a conditional branch to the return. Replace the branch 1442251662Sdim // with a bclr. 1443251662Sdim BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BCLR)) 1444251662Sdim .addImm(J->getOperand(0).getImm()) 1445251662Sdim .addReg(J->getOperand(1).getReg()); 1446251662Sdim MachineBasicBlock::iterator K = J--; 1447251662Sdim K->eraseFromParent(); 1448251662Sdim BlockChanged = true; 1449251662Sdim ++NumBCLR; 1450251662Sdim continue; 1451251662Sdim } 1452251662Sdim } else if (J->isBranch()) { 1453251662Sdim if (J->isIndirectBranch()) { 1454251662Sdim if (ReturnMBB.hasAddressTaken()) 1455251662Sdim OtherReference = true; 1456251662Sdim } else 1457251662Sdim for (unsigned i = 0; i < J->getNumOperands(); ++i) 1458251662Sdim if (J->getOperand(i).isMBB() && 1459251662Sdim J->getOperand(i).getMBB() == &ReturnMBB) 1460251662Sdim OtherReference = true; 1461251662Sdim } else if (!J->isTerminator() && !J->isDebugValue()) 1462251662Sdim break; 1463251662Sdim 1464251662Sdim if (J == (*PI)->begin()) 1465251662Sdim break; 1466251662Sdim 1467251662Sdim --J; 1468251662Sdim } 1469251662Sdim 1470251662Sdim if ((*PI)->canFallThrough() && (*PI)->isLayoutSuccessor(&ReturnMBB)) 1471251662Sdim OtherReference = true; 1472251662Sdim 1473251662Sdim // Predecessors are stored in a vector and can't be removed here. 1474251662Sdim if (!OtherReference && BlockChanged) { 1475251662Sdim PredToRemove.push_back(*PI); 1476251662Sdim } 1477251662Sdim 1478251662Sdim if (BlockChanged) 1479251662Sdim Changed = true; 1480251662Sdim } 1481251662Sdim 1482251662Sdim for (unsigned i = 0, ie = PredToRemove.size(); i != ie; ++i) 1483251662Sdim PredToRemove[i]->removeSuccessor(&ReturnMBB); 1484251662Sdim 1485251662Sdim if (Changed && !ReturnMBB.hasAddressTaken()) { 1486251662Sdim // We now might be able to merge this blr-only block into its 1487251662Sdim // by-layout predecessor. 1488251662Sdim if (ReturnMBB.pred_size() == 1 && 1489251662Sdim (*ReturnMBB.pred_begin())->isLayoutSuccessor(&ReturnMBB)) { 1490251662Sdim // Move the blr into the preceding block. 1491251662Sdim MachineBasicBlock &PrevMBB = **ReturnMBB.pred_begin(); 1492251662Sdim PrevMBB.splice(PrevMBB.end(), &ReturnMBB, I); 1493251662Sdim PrevMBB.removeSuccessor(&ReturnMBB); 1494251662Sdim } 1495251662Sdim 1496251662Sdim if (ReturnMBB.pred_empty()) 1497251662Sdim ReturnMBB.eraseFromParent(); 1498251662Sdim } 1499251662Sdim 1500251662Sdim return Changed; 1501251662Sdim } 1502251662Sdim 1503251662Sdimpublic: 1504251662Sdim virtual bool runOnMachineFunction(MachineFunction &MF) { 1505251662Sdim TM = static_cast<const PPCTargetMachine *>(&MF.getTarget()); 1506251662Sdim TII = TM->getInstrInfo(); 1507251662Sdim 1508251662Sdim bool Changed = false; 1509251662Sdim 1510251662Sdim // If the function does not have at least two blocks, then there is 1511251662Sdim // nothing to do. 1512251662Sdim if (MF.size() < 2) 1513251662Sdim return Changed; 1514251662Sdim 1515251662Sdim for (MachineFunction::iterator I = MF.begin(); I != MF.end();) { 1516251662Sdim MachineBasicBlock &B = *I++; 1517251662Sdim if (processBlock(B)) 1518251662Sdim Changed = true; 1519251662Sdim } 1520251662Sdim 1521251662Sdim return Changed; 1522251662Sdim } 1523251662Sdim 1524251662Sdim virtual void getAnalysisUsage(AnalysisUsage &AU) const { 1525251662Sdim MachineFunctionPass::getAnalysisUsage(AU); 1526251662Sdim } 1527251662Sdim }; 1528251662Sdim} 1529251662Sdim 1530251662SdimINITIALIZE_PASS(PPCEarlyReturn, DEBUG_TYPE, 1531251662Sdim "PowerPC Early-Return Creation", false, false) 1532251662Sdim 1533251662Sdimchar PPCEarlyReturn::ID = 0; 1534251662SdimFunctionPass* 1535251662Sdimllvm::createPPCEarlyReturnPass() { return new PPCEarlyReturn(); } 1536251662Sdim 1537