1198090Srdivacky//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 2198090Srdivacky// 3198090Srdivacky// The LLVM Compiler Infrastructure 4198090Srdivacky// 5198090Srdivacky// This file is distributed under the University of Illinois Open Source 6198090Srdivacky// License. See LICENSE.TXT for details. 7198090Srdivacky// 8198090Srdivacky//===----------------------------------------------------------------------===// 9198090Srdivacky// 10198090Srdivacky// This implements the Emit routines for the SelectionDAG class, which creates 11198090Srdivacky// MachineInstrs based on the decisions of the SelectionDAG instruction 12198090Srdivacky// selection. 13198090Srdivacky// 14198090Srdivacky//===----------------------------------------------------------------------===// 15198090Srdivacky 16198090Srdivacky#define DEBUG_TYPE "instr-emitter" 17198090Srdivacky#include "InstrEmitter.h" 18205218Srdivacky#include "SDNodeDbgValue.h" 19249423Sdim#include "llvm/ADT/Statistic.h" 20198090Srdivacky#include "llvm/CodeGen/MachineConstantPool.h" 21198090Srdivacky#include "llvm/CodeGen/MachineFunction.h" 22198090Srdivacky#include "llvm/CodeGen/MachineInstrBuilder.h" 23198090Srdivacky#include "llvm/CodeGen/MachineRegisterInfo.h" 24263508Sdim#include "llvm/CodeGen/StackMaps.h" 25249423Sdim#include "llvm/IR/DataLayout.h" 26198090Srdivacky#include "llvm/Support/Debug.h" 27198090Srdivacky#include "llvm/Support/ErrorHandling.h" 28198090Srdivacky#include "llvm/Support/MathExtras.h" 29249423Sdim#include "llvm/Target/TargetInstrInfo.h" 30249423Sdim#include "llvm/Target/TargetLowering.h" 31249423Sdim#include "llvm/Target/TargetMachine.h" 32198090Srdivackyusing namespace llvm; 33198090Srdivacky 34226633Sdim/// MinRCSize - Smallest register class we allow when constraining virtual 35226633Sdim/// registers. If satisfying all register class constraints would require 36226633Sdim/// using a smaller register class, emit a COPY to a new virtual register 37226633Sdim/// instead. 38226633Sdimconst unsigned MinRCSize = 4; 39226633Sdim 40198090Srdivacky/// CountResults - The results of target nodes have register or immediate 41218893Sdim/// operands first, then an optional chain, and optional glue operands (which do 42198090Srdivacky/// not go into the resulting MachineInstr). 43198090Srdivackyunsigned InstrEmitter::CountResults(SDNode *Node) { 44198090Srdivacky unsigned N = Node->getNumValues(); 45218893Sdim while (N && Node->getValueType(N - 1) == MVT::Glue) 46198090Srdivacky --N; 47198090Srdivacky if (N && Node->getValueType(N - 1) == MVT::Other) 48198090Srdivacky --N; // Skip over chain result. 49198090Srdivacky return N; 50198090Srdivacky} 51198090Srdivacky 52239462Sdim/// countOperands - The inputs to target nodes have any actual inputs first, 53218893Sdim/// followed by an optional chain operand, then an optional glue operand. 54198090Srdivacky/// Compute the number of actual operands that will go into the resulting 55198090Srdivacky/// MachineInstr. 56239462Sdim/// 57239462Sdim/// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding 58239462Sdim/// the chain and glue. These operands may be implicit on the machine instr. 59243830Sdimstatic unsigned countOperands(SDNode *Node, unsigned NumExpUses, 60243830Sdim unsigned &NumImpUses) { 61198090Srdivacky unsigned N = Node->getNumOperands(); 62218893Sdim while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue) 63198090Srdivacky --N; 64198090Srdivacky if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 65198090Srdivacky --N; // Ignore chain if it exists. 66239462Sdim 67239462Sdim // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses. 68243830Sdim NumImpUses = N - NumExpUses; 69243830Sdim for (unsigned I = N; I > NumExpUses; --I) { 70239462Sdim if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1))) 71239462Sdim continue; 72239462Sdim if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1))) 73239462Sdim if (TargetRegisterInfo::isPhysicalRegister(RN->getReg())) 74239462Sdim continue; 75239462Sdim NumImpUses = N - I; 76239462Sdim break; 77239462Sdim } 78239462Sdim 79198090Srdivacky return N; 80198090Srdivacky} 81198090Srdivacky 82198090Srdivacky/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 83198090Srdivacky/// implicit physical register output. 84198090Srdivackyvoid InstrEmitter:: 85198090SrdivackyEmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 86198090Srdivacky unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 87198090Srdivacky unsigned VRBase = 0; 88198090Srdivacky if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 89198090Srdivacky // Just use the input register directly! 90198090Srdivacky SDValue Op(Node, ResNo); 91198090Srdivacky if (IsClone) 92198090Srdivacky VRBaseMap.erase(Op); 93198090Srdivacky bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 94218893Sdim (void)isNew; // Silence compiler warning. 95198090Srdivacky assert(isNew && "Node emitted out of order - early"); 96198090Srdivacky return; 97198090Srdivacky } 98198090Srdivacky 99198090Srdivacky // If the node is only used by a CopyToReg and the dest reg is a vreg, use 100198090Srdivacky // the CopyToReg'd destination register instead of creating a new vreg. 101198090Srdivacky bool MatchReg = true; 102198090Srdivacky const TargetRegisterClass *UseRC = NULL; 103249423Sdim MVT VT = Node->getSimpleValueType(ResNo); 104224145Sdim 105224145Sdim // Stick to the preferred register classes for legal types. 106224145Sdim if (TLI->isTypeLegal(VT)) 107224145Sdim UseRC = TLI->getRegClassFor(VT); 108224145Sdim 109198090Srdivacky if (!IsClone && !IsCloned) 110198090Srdivacky for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 111198090Srdivacky UI != E; ++UI) { 112198090Srdivacky SDNode *User = *UI; 113198090Srdivacky bool Match = true; 114226633Sdim if (User->getOpcode() == ISD::CopyToReg && 115198090Srdivacky User->getOperand(2).getNode() == Node && 116198090Srdivacky User->getOperand(2).getResNo() == ResNo) { 117198090Srdivacky unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 118198090Srdivacky if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 119198090Srdivacky VRBase = DestReg; 120198090Srdivacky Match = false; 121198090Srdivacky } else if (DestReg != SrcReg) 122198090Srdivacky Match = false; 123198090Srdivacky } else { 124198090Srdivacky for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 125198090Srdivacky SDValue Op = User->getOperand(i); 126198090Srdivacky if (Op.getNode() != Node || Op.getResNo() != ResNo) 127198090Srdivacky continue; 128249423Sdim MVT VT = Node->getSimpleValueType(Op.getResNo()); 129218893Sdim if (VT == MVT::Other || VT == MVT::Glue) 130198090Srdivacky continue; 131198090Srdivacky Match = false; 132198090Srdivacky if (User->isMachineOpcode()) { 133224145Sdim const MCInstrDesc &II = TII->get(User->getMachineOpcode()); 134198090Srdivacky const TargetRegisterClass *RC = 0; 135239462Sdim if (i+II.getNumDefs() < II.getNumOperands()) { 136239462Sdim RC = TRI->getAllocatableClass( 137239462Sdim TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); 138239462Sdim } 139198090Srdivacky if (!UseRC) 140198090Srdivacky UseRC = RC; 141198090Srdivacky else if (RC) { 142226633Sdim const TargetRegisterClass *ComRC = 143226633Sdim TRI->getCommonSubClass(UseRC, RC); 144198090Srdivacky // If multiple uses expect disjoint register classes, we emit 145198090Srdivacky // copies in AddRegisterOperand. 146198090Srdivacky if (ComRC) 147198090Srdivacky UseRC = ComRC; 148198090Srdivacky } 149198090Srdivacky } 150198090Srdivacky } 151198090Srdivacky } 152198090Srdivacky MatchReg &= Match; 153198090Srdivacky if (VRBase) 154198090Srdivacky break; 155198090Srdivacky } 156198090Srdivacky 157198090Srdivacky const TargetRegisterClass *SrcRC = 0, *DstRC = 0; 158210299Sed SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); 159224145Sdim 160198090Srdivacky // Figure out the register class to create for the destreg. 161198090Srdivacky if (VRBase) { 162198090Srdivacky DstRC = MRI->getRegClass(VRBase); 163198090Srdivacky } else if (UseRC) { 164198090Srdivacky assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 165198090Srdivacky DstRC = UseRC; 166198090Srdivacky } else { 167198090Srdivacky DstRC = TLI->getRegClassFor(VT); 168198090Srdivacky } 169226633Sdim 170198090Srdivacky // If all uses are reading from the src physical register and copying the 171198090Srdivacky // register is either impossible or very expensive, then don't create a copy. 172198090Srdivacky if (MatchReg && SrcRC->getCopyCost() < 0) { 173198090Srdivacky VRBase = SrcReg; 174198090Srdivacky } else { 175198090Srdivacky // Create the reg, emit the copy. 176198090Srdivacky VRBase = MRI->createVirtualRegister(DstRC); 177210299Sed BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 178210299Sed VRBase).addReg(SrcReg); 179198090Srdivacky } 180198090Srdivacky 181198090Srdivacky SDValue Op(Node, ResNo); 182198090Srdivacky if (IsClone) 183198090Srdivacky VRBaseMap.erase(Op); 184198090Srdivacky bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 185218893Sdim (void)isNew; // Silence compiler warning. 186198090Srdivacky assert(isNew && "Node emitted out of order - early"); 187198090Srdivacky} 188198090Srdivacky 189198090Srdivacky/// getDstOfCopyToRegUse - If the only use of the specified result number of 190198090Srdivacky/// node is a CopyToReg, return its destination register. Return 0 otherwise. 191198090Srdivackyunsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 192198090Srdivacky unsigned ResNo) const { 193198090Srdivacky if (!Node->hasOneUse()) 194198090Srdivacky return 0; 195198090Srdivacky 196198090Srdivacky SDNode *User = *Node->use_begin(); 197226633Sdim if (User->getOpcode() == ISD::CopyToReg && 198198090Srdivacky User->getOperand(2).getNode() == Node && 199198090Srdivacky User->getOperand(2).getResNo() == ResNo) { 200198090Srdivacky unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 201198090Srdivacky if (TargetRegisterInfo::isVirtualRegister(Reg)) 202198090Srdivacky return Reg; 203198090Srdivacky } 204198090Srdivacky return 0; 205198090Srdivacky} 206198090Srdivacky 207249423Sdimvoid InstrEmitter::CreateVirtualRegisters(SDNode *Node, 208249423Sdim MachineInstrBuilder &MIB, 209224145Sdim const MCInstrDesc &II, 210198090Srdivacky bool IsClone, bool IsCloned, 211198090Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap) { 212203954Srdivacky assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 213198090Srdivacky "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 214198090Srdivacky 215263508Sdim unsigned NumResults = CountResults(Node); 216198090Srdivacky for (unsigned i = 0; i < II.getNumDefs(); ++i) { 217198090Srdivacky // If the specific node value is only used by a CopyToReg and the dest reg 218198090Srdivacky // is a vreg in the same register class, use the CopyToReg'd destination 219198090Srdivacky // register instead of creating a new vreg. 220198090Srdivacky unsigned VRBase = 0; 221239462Sdim const TargetRegisterClass *RC = 222239462Sdim TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); 223263763Sdim // Always let the value type influence the used register class. The 224263763Sdim // constraints on the instruction may be too lax to represent the value 225263763Sdim // type correctly. For example, a 64-bit float (X86::FR64) can't live in 226263763Sdim // the 32-bit float super-class (X86::FR32). 227263763Sdim if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) { 228263763Sdim const TargetRegisterClass *VTRC = 229263763Sdim TLI->getRegClassFor(Node->getSimpleValueType(i)); 230263763Sdim if (RC) 231263763Sdim VTRC = TRI->getCommonSubClass(RC, VTRC); 232263763Sdim if (VTRC) 233263763Sdim RC = VTRC; 234263763Sdim } 235263763Sdim 236198090Srdivacky if (II.OpInfo[i].isOptionalDef()) { 237198090Srdivacky // Optional def must be a physical register. 238198090Srdivacky unsigned NumResults = CountResults(Node); 239198090Srdivacky VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 240198090Srdivacky assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 241249423Sdim MIB.addReg(VRBase, RegState::Define); 242198090Srdivacky } 243198090Srdivacky 244198090Srdivacky if (!VRBase && !IsClone && !IsCloned) 245198090Srdivacky for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 246198090Srdivacky UI != E; ++UI) { 247198090Srdivacky SDNode *User = *UI; 248226633Sdim if (User->getOpcode() == ISD::CopyToReg && 249198090Srdivacky User->getOperand(2).getNode() == Node && 250198090Srdivacky User->getOperand(2).getResNo() == i) { 251198090Srdivacky unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 252198090Srdivacky if (TargetRegisterInfo::isVirtualRegister(Reg)) { 253198090Srdivacky const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 254198090Srdivacky if (RegRC == RC) { 255198090Srdivacky VRBase = Reg; 256249423Sdim MIB.addReg(VRBase, RegState::Define); 257198090Srdivacky break; 258198090Srdivacky } 259198090Srdivacky } 260198090Srdivacky } 261198090Srdivacky } 262198090Srdivacky 263198090Srdivacky // Create the result registers for this node and add the result regs to 264198090Srdivacky // the machine instruction. 265198090Srdivacky if (VRBase == 0) { 266198090Srdivacky assert(RC && "Isn't a register operand!"); 267198090Srdivacky VRBase = MRI->createVirtualRegister(RC); 268249423Sdim MIB.addReg(VRBase, RegState::Define); 269198090Srdivacky } 270198090Srdivacky 271198090Srdivacky SDValue Op(Node, i); 272198090Srdivacky if (IsClone) 273198090Srdivacky VRBaseMap.erase(Op); 274198090Srdivacky bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 275218893Sdim (void)isNew; // Silence compiler warning. 276198090Srdivacky assert(isNew && "Node emitted out of order - early"); 277198090Srdivacky } 278198090Srdivacky} 279198090Srdivacky 280198090Srdivacky/// getVR - Return the virtual register corresponding to the specified result 281198090Srdivacky/// of the specified node. 282198090Srdivackyunsigned InstrEmitter::getVR(SDValue Op, 283198090Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap) { 284198090Srdivacky if (Op.isMachineOpcode() && 285203954Srdivacky Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 286198090Srdivacky // Add an IMPLICIT_DEF instruction before every use. 287198090Srdivacky unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 288224145Sdim // IMPLICIT_DEF can produce any type of result so its MCInstrDesc 289198090Srdivacky // does not include operand register class info. 290198090Srdivacky if (!VReg) { 291249423Sdim const TargetRegisterClass *RC = 292249423Sdim TLI->getRegClassFor(Op.getSimpleValueType()); 293198090Srdivacky VReg = MRI->createVirtualRegister(RC); 294198090Srdivacky } 295210299Sed BuildMI(*MBB, InsertPos, Op.getDebugLoc(), 296203954Srdivacky TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 297198090Srdivacky return VReg; 298198090Srdivacky } 299198090Srdivacky 300198090Srdivacky DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 301198090Srdivacky assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 302198090Srdivacky return I->second; 303198090Srdivacky} 304198090Srdivacky 305198090Srdivacky 306198090Srdivacky/// AddRegisterOperand - Add the specified register as an operand to the 307198090Srdivacky/// specified machine instr. Insert register copies if the register is 308198090Srdivacky/// not in the required register class. 309198090Srdivackyvoid 310249423SdimInstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, 311249423Sdim SDValue Op, 312198090Srdivacky unsigned IIOpNum, 313224145Sdim const MCInstrDesc *II, 314206083Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap, 315208599Srdivacky bool IsDebug, bool IsClone, bool IsCloned) { 316198090Srdivacky assert(Op.getValueType() != MVT::Other && 317218893Sdim Op.getValueType() != MVT::Glue && 318218893Sdim "Chain and glue operands should occur at end of operand list!"); 319198090Srdivacky // Get/emit the operand. 320198090Srdivacky unsigned VReg = getVR(Op, VRBaseMap); 321198090Srdivacky assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 322198090Srdivacky 323249423Sdim const MCInstrDesc &MCID = MIB->getDesc(); 324224145Sdim bool isOptDef = IIOpNum < MCID.getNumOperands() && 325224145Sdim MCID.OpInfo[IIOpNum].isOptionalDef(); 326198090Srdivacky 327198090Srdivacky // If the instruction requires a register in a different class, create 328226633Sdim // a new virtual register and copy the value into it, but first attempt to 329226633Sdim // shrink VReg's register class within reason. For example, if VReg == GR32 330226633Sdim // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP. 331198090Srdivacky if (II) { 332198090Srdivacky const TargetRegisterClass *DstRC = 0; 333198090Srdivacky if (IIOpNum < II->getNumOperands()) 334239462Sdim DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); 335226633Sdim if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { 336198090Srdivacky unsigned NewVReg = MRI->createVirtualRegister(DstRC); 337210299Sed BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), 338210299Sed TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); 339198090Srdivacky VReg = NewVReg; 340198090Srdivacky } 341198090Srdivacky } 342198090Srdivacky 343207618Srdivacky // If this value has only one use, that use is a kill. This is a 344208599Srdivacky // conservative approximation. InstrEmitter does trivial coalescing 345208599Srdivacky // with CopyFromReg nodes, so don't emit kill flags for them. 346208599Srdivacky // Avoid kill flags on Schedule cloned nodes, since there will be 347208599Srdivacky // multiple uses. 348208599Srdivacky // Tied operands are never killed, so we need to check that. And that 349208599Srdivacky // means we need to determine the index of the operand. 350208599Srdivacky bool isKill = Op.hasOneUse() && 351208599Srdivacky Op.getNode()->getOpcode() != ISD::CopyFromReg && 352208599Srdivacky !IsDebug && 353208599Srdivacky !(IsClone || IsCloned); 354208599Srdivacky if (isKill) { 355249423Sdim unsigned Idx = MIB->getNumOperands(); 356208599Srdivacky while (Idx > 0 && 357249423Sdim MIB->getOperand(Idx-1).isReg() && 358249423Sdim MIB->getOperand(Idx-1).isImplicit()) 359208599Srdivacky --Idx; 360249423Sdim bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1; 361208599Srdivacky if (isTied) 362208599Srdivacky isKill = false; 363208599Srdivacky } 364207618Srdivacky 365249423Sdim MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | 366249423Sdim getDebugRegState(IsDebug)); 367198090Srdivacky} 368198090Srdivacky 369198090Srdivacky/// AddOperand - Add the specified operand to the specified machine instr. II 370198090Srdivacky/// specifies the instruction information for the node, and IIOpNum is the 371239462Sdim/// operand number (in the II) that we are adding. 372249423Sdimvoid InstrEmitter::AddOperand(MachineInstrBuilder &MIB, 373249423Sdim SDValue Op, 374198090Srdivacky unsigned IIOpNum, 375224145Sdim const MCInstrDesc *II, 376206083Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap, 377208599Srdivacky bool IsDebug, bool IsClone, bool IsCloned) { 378198090Srdivacky if (Op.isMachineOpcode()) { 379249423Sdim AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap, 380208599Srdivacky IsDebug, IsClone, IsCloned); 381198090Srdivacky } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 382249423Sdim MIB.addImm(C->getSExtValue()); 383198090Srdivacky } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 384249423Sdim MIB.addFPImm(F->getConstantFPValue()); 385198090Srdivacky } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 386239462Sdim // Turn additional physreg operands into implicit uses on non-variadic 387239462Sdim // instructions. This is used by call and return instructions passing 388239462Sdim // arguments in registers. 389239462Sdim bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic()); 390249423Sdim MIB.addReg(R->getReg(), getImplRegState(Imp)); 391234353Sdim } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) { 392249423Sdim MIB.addRegMask(RM->getRegMask()); 393198090Srdivacky } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 394249423Sdim MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(), 395249423Sdim TGA->getTargetFlags()); 396198090Srdivacky } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 397249423Sdim MIB.addMBB(BBNode->getBasicBlock()); 398198090Srdivacky } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 399249423Sdim MIB.addFrameIndex(FI->getIndex()); 400198090Srdivacky } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 401249423Sdim MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags()); 402198090Srdivacky } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 403198090Srdivacky int Offset = CP->getOffset(); 404198090Srdivacky unsigned Align = CP->getAlignment(); 405226633Sdim Type *Type = CP->getType(); 406198090Srdivacky // MachineConstantPool wants an explicit alignment. 407198090Srdivacky if (Align == 0) { 408243830Sdim Align = TM->getDataLayout()->getPrefTypeAlignment(Type); 409198090Srdivacky if (Align == 0) { 410198090Srdivacky // Alignment of vector types. FIXME! 411243830Sdim Align = TM->getDataLayout()->getTypeAllocSize(Type); 412198090Srdivacky } 413198090Srdivacky } 414226633Sdim 415198090Srdivacky unsigned Idx; 416198090Srdivacky MachineConstantPool *MCP = MF->getConstantPool(); 417198090Srdivacky if (CP->isMachineConstantPoolEntry()) 418198090Srdivacky Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 419198090Srdivacky else 420198090Srdivacky Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 421249423Sdim MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags()); 422198090Srdivacky } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 423249423Sdim MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags()); 424198892Srdivacky } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 425249423Sdim MIB.addBlockAddress(BA->getBlockAddress(), 426249423Sdim BA->getOffset(), 427249423Sdim BA->getTargetFlags()); 428239462Sdim } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) { 429249423Sdim MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags()); 430198090Srdivacky } else { 431198090Srdivacky assert(Op.getValueType() != MVT::Other && 432218893Sdim Op.getValueType() != MVT::Glue && 433218893Sdim "Chain and glue operands should occur at end of operand list!"); 434249423Sdim AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap, 435208599Srdivacky IsDebug, IsClone, IsCloned); 436198090Srdivacky } 437198090Srdivacky} 438198090Srdivacky 439226633Sdimunsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, 440249423Sdim MVT VT, DebugLoc DL) { 441226633Sdim const TargetRegisterClass *VRC = MRI->getRegClass(VReg); 442226633Sdim const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); 443226633Sdim 444226633Sdim // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg 445226633Sdim // within reason. 446226633Sdim if (RC && RC != VRC) 447226633Sdim RC = MRI->constrainRegClass(VReg, RC, MinRCSize); 448226633Sdim 449226633Sdim // VReg has been adjusted. It can be used with SubIdx operands now. 450226633Sdim if (RC) 451226633Sdim return VReg; 452226633Sdim 453226633Sdim // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual 454226633Sdim // register instead. 455226633Sdim RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); 456226633Sdim assert(RC && "No legal register class for VT supports that SubIdx"); 457226633Sdim unsigned NewReg = MRI->createVirtualRegister(RC); 458226633Sdim BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg) 459226633Sdim .addReg(VReg); 460226633Sdim return NewReg; 461198090Srdivacky} 462198090Srdivacky 463198090Srdivacky/// EmitSubregNode - Generate machine code for subreg nodes. 464198090Srdivacky/// 465226633Sdimvoid InstrEmitter::EmitSubregNode(SDNode *Node, 466208599Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap, 467208599Srdivacky bool IsClone, bool IsCloned) { 468198090Srdivacky unsigned VRBase = 0; 469198090Srdivacky unsigned Opc = Node->getMachineOpcode(); 470226633Sdim 471198090Srdivacky // If the node is only used by a CopyToReg and the dest reg is a vreg, use 472198090Srdivacky // the CopyToReg'd destination register instead of creating a new vreg. 473198090Srdivacky for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 474198090Srdivacky UI != E; ++UI) { 475198090Srdivacky SDNode *User = *UI; 476226633Sdim if (User->getOpcode() == ISD::CopyToReg && 477198090Srdivacky User->getOperand(2).getNode() == Node) { 478198090Srdivacky unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 479198090Srdivacky if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 480198090Srdivacky VRBase = DestReg; 481198090Srdivacky break; 482198090Srdivacky } 483198090Srdivacky } 484198090Srdivacky } 485226633Sdim 486203954Srdivacky if (Opc == TargetOpcode::EXTRACT_SUBREG) { 487226633Sdim // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no 488226633Sdim // constraints on the %dst register, COPY can target all legal register 489226633Sdim // classes. 490198090Srdivacky unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 491249423Sdim const TargetRegisterClass *TRC = 492249423Sdim TLI->getRegClassFor(Node->getSimpleValueType(0)); 493198090Srdivacky 494198090Srdivacky unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 495218893Sdim MachineInstr *DefMI = MRI->getVRegDef(VReg); 496218893Sdim unsigned SrcReg, DstReg, DefSubIdx; 497218893Sdim if (DefMI && 498218893Sdim TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) && 499239462Sdim SubIdx == DefSubIdx && 500239462Sdim TRC == MRI->getRegClass(SrcReg)) { 501218893Sdim // Optimize these: 502218893Sdim // r1025 = s/zext r1024, 4 503218893Sdim // r1026 = extract_subreg r1025, 4 504218893Sdim // to a copy 505218893Sdim // r1026 = copy r1024 506218893Sdim VRBase = MRI->createVirtualRegister(TRC); 507218893Sdim BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 508218893Sdim TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg); 509239462Sdim MRI->clearKillFlags(SrcReg); 510218893Sdim } else { 511226633Sdim // VReg may not support a SubIdx sub-register, and we may need to 512226633Sdim // constrain its register class or issue a COPY to a compatible register 513226633Sdim // class. 514226633Sdim VReg = ConstrainForSubReg(VReg, SubIdx, 515249423Sdim Node->getOperand(0).getSimpleValueType(), 516226633Sdim Node->getDebugLoc()); 517198090Srdivacky 518226633Sdim // Create the destreg if it is missing. 519226633Sdim if (VRBase == 0) 520226633Sdim VRBase = MRI->createVirtualRegister(TRC); 521198090Srdivacky 522218893Sdim // Create the extract_subreg machine instruction. 523226633Sdim BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 524226633Sdim TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); 525218893Sdim } 526203954Srdivacky } else if (Opc == TargetOpcode::INSERT_SUBREG || 527203954Srdivacky Opc == TargetOpcode::SUBREG_TO_REG) { 528198090Srdivacky SDValue N0 = Node->getOperand(0); 529198090Srdivacky SDValue N1 = Node->getOperand(1); 530198090Srdivacky SDValue N2 = Node->getOperand(2); 531198090Srdivacky unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 532198090Srdivacky 533226633Sdim // Figure out the register class to create for the destreg. It should be 534226633Sdim // the largest legal register class supporting SubIdx sub-registers. 535226633Sdim // RegisterCoalescer will constrain it further if it decides to eliminate 536226633Sdim // the INSERT_SUBREG instruction. 537226633Sdim // 538226633Sdim // %dst = INSERT_SUBREG %src, %sub, SubIdx 539226633Sdim // 540226633Sdim // is lowered by TwoAddressInstructionPass to: 541226633Sdim // 542226633Sdim // %dst = COPY %src 543226633Sdim // %dst:SubIdx = COPY %sub 544226633Sdim // 545226633Sdim // There is no constraint on the %src register class. 546226633Sdim // 547249423Sdim const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0)); 548226633Sdim SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); 549226633Sdim assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG"); 550226633Sdim 551226633Sdim if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) 552198090Srdivacky VRBase = MRI->createVirtualRegister(SRC); 553198090Srdivacky 554198090Srdivacky // Create the insert_subreg or subreg_to_reg machine instruction. 555249423Sdim MachineInstrBuilder MIB = 556249423Sdim BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase); 557226633Sdim 558198090Srdivacky // If creating a subreg_to_reg, then the first input operand 559198090Srdivacky // is an implicit value immediate, otherwise it's a register 560203954Srdivacky if (Opc == TargetOpcode::SUBREG_TO_REG) { 561198090Srdivacky const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 562249423Sdim MIB.addImm(SD->getZExtValue()); 563198090Srdivacky } else 564249423Sdim AddOperand(MIB, N0, 0, 0, VRBaseMap, /*IsDebug=*/false, 565208599Srdivacky IsClone, IsCloned); 566198090Srdivacky // Add the subregster being inserted 567249423Sdim AddOperand(MIB, N1, 0, 0, VRBaseMap, /*IsDebug=*/false, 568208599Srdivacky IsClone, IsCloned); 569249423Sdim MIB.addImm(SubIdx); 570249423Sdim MBB->insert(InsertPos, MIB); 571198090Srdivacky } else 572198090Srdivacky llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 573226633Sdim 574198090Srdivacky SDValue Op(Node, 0); 575198090Srdivacky bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 576218893Sdim (void)isNew; // Silence compiler warning. 577198090Srdivacky assert(isNew && "Node emitted out of order - early"); 578198090Srdivacky} 579198090Srdivacky 580198090Srdivacky/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 581198090Srdivacky/// COPY_TO_REGCLASS is just a normal copy, except that the destination 582198090Srdivacky/// register is constrained to be in a particular register class. 583198090Srdivacky/// 584198090Srdivackyvoid 585198090SrdivackyInstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 586198090Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap) { 587198090Srdivacky unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 588198090Srdivacky 589210299Sed // Create the new VReg in the destination class and emit a copy. 590198090Srdivacky unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 591239462Sdim const TargetRegisterClass *DstRC = 592239462Sdim TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx)); 593198090Srdivacky unsigned NewVReg = MRI->createVirtualRegister(DstRC); 594210299Sed BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 595210299Sed NewVReg).addReg(VReg); 596198090Srdivacky 597198090Srdivacky SDValue Op(Node, 0); 598198090Srdivacky bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 599218893Sdim (void)isNew; // Silence compiler warning. 600198090Srdivacky assert(isNew && "Node emitted out of order - early"); 601198090Srdivacky} 602198090Srdivacky 603207618Srdivacky/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 604207618Srdivacky/// 605207618Srdivackyvoid InstrEmitter::EmitRegSequence(SDNode *Node, 606208599Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap, 607208599Srdivacky bool IsClone, bool IsCloned) { 608224145Sdim unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue(); 609224145Sdim const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); 610239462Sdim unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC)); 611249423Sdim const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); 612249423Sdim MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg); 613207618Srdivacky unsigned NumOps = Node->getNumOperands(); 614224145Sdim assert((NumOps & 1) == 1 && 615224145Sdim "REG_SEQUENCE must have an odd number of operands!"); 616224145Sdim for (unsigned i = 1; i != NumOps; ++i) { 617207618Srdivacky SDValue Op = Node->getOperand(i); 618224145Sdim if ((i & 1) == 0) { 619234353Sdim RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1)); 620234353Sdim // Skip physical registers as they don't have a vreg to get and we'll 621234353Sdim // insert copies for them in TwoAddressInstructionPass anyway. 622234353Sdim if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 623234353Sdim unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); 624234353Sdim unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap); 625234353Sdim const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 626234353Sdim const TargetRegisterClass *SRC = 627208599Srdivacky TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); 628234353Sdim if (SRC && SRC != RC) { 629234353Sdim MRI->setRegClass(NewVReg, SRC); 630234353Sdim RC = SRC; 631234353Sdim } 632208599Srdivacky } 633207618Srdivacky } 634249423Sdim AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false, 635208599Srdivacky IsClone, IsCloned); 636207618Srdivacky } 637207618Srdivacky 638249423Sdim MBB->insert(InsertPos, MIB); 639207618Srdivacky SDValue Op(Node, 0); 640207618Srdivacky bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 641218893Sdim (void)isNew; // Silence compiler warning. 642207618Srdivacky assert(isNew && "Node emitted out of order - early"); 643207618Srdivacky} 644207618Srdivacky 645206083Srdivacky/// EmitDbgValue - Generate machine instruction for a dbg_value node. 646206083Srdivacky/// 647207618SrdivackyMachineInstr * 648207618SrdivackyInstrEmitter::EmitDbgValue(SDDbgValue *SD, 649207618Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap) { 650206083Srdivacky uint64_t Offset = SD->getOffset(); 651206083Srdivacky MDNode* MDPtr = SD->getMDPtr(); 652206083Srdivacky DebugLoc DL = SD->getDebugLoc(); 653204792Srdivacky 654207618Srdivacky if (SD->getKind() == SDDbgValue::FRAMEIX) { 655207618Srdivacky // Stack address; this needs to be lowered in target-dependent fashion. 656207618Srdivacky // EmitTargetCodeForFrameDebugValue is responsible for allocation. 657263508Sdim return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE)) 658263508Sdim .addFrameIndex(SD->getFrameIx()).addImm(Offset).addMetadata(MDPtr); 659207618Srdivacky } 660207618Srdivacky // Otherwise, we're going to create an instruction here. 661224145Sdim const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); 662206083Srdivacky MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 663206083Srdivacky if (SD->getKind() == SDDbgValue::SDNODE) { 664207618Srdivacky SDNode *Node = SD->getSDNode(); 665207618Srdivacky SDValue Op = SDValue(Node, SD->getResNo()); 666207618Srdivacky // It's possible we replaced this SDNode with other(s) and therefore 667207618Srdivacky // didn't generate code for it. It's better to catch these cases where 668207618Srdivacky // they happen and transfer the debug info, but trying to guarantee that 669207618Srdivacky // in all cases would be very fragile; this is a safeguard for any 670207618Srdivacky // that were missed. 671207618Srdivacky DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 672207618Srdivacky if (I==VRBaseMap.end()) 673207618Srdivacky MIB.addReg(0U); // undef 674207618Srdivacky else 675249423Sdim AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, 676208599Srdivacky /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false); 677206083Srdivacky } else if (SD->getKind() == SDDbgValue::CONST) { 678207618Srdivacky const Value *V = SD->getConst(); 679207618Srdivacky if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 680224145Sdim if (CI->getBitWidth() > 64) 681224145Sdim MIB.addCImm(CI); 682208599Srdivacky else 683208599Srdivacky MIB.addImm(CI->getSExtValue()); 684207618Srdivacky } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 685206083Srdivacky MIB.addFPImm(CF); 686205218Srdivacky } else { 687205218Srdivacky // Could be an Undef. In any case insert an Undef so we can see what we 688205218Srdivacky // dropped. 689206083Srdivacky MIB.addReg(0U); 690205218Srdivacky } 691204792Srdivacky } else { 692204792Srdivacky // Insert an Undef so we can see what we dropped. 693206083Srdivacky MIB.addReg(0U); 694204792Srdivacky } 695206083Srdivacky 696263508Sdim if (Offset != 0) // Indirect addressing. 697263508Sdim MIB.addImm(Offset); 698263508Sdim else 699263508Sdim MIB.addReg(0U, RegState::Debug); 700263508Sdim 701263508Sdim MIB.addMetadata(MDPtr); 702263508Sdim 703206083Srdivacky return &*MIB; 704204792Srdivacky} 705204792Srdivacky 706206083Srdivacky/// EmitMachineNode - Generate machine code for a target-specific node and 707206083Srdivacky/// needed dependencies. 708198090Srdivacky/// 709206083Srdivackyvoid InstrEmitter:: 710206083SrdivackyEmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 711207618Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap) { 712206083Srdivacky unsigned Opc = Node->getMachineOpcode(); 713226633Sdim 714206083Srdivacky // Handle subreg insert/extract specially 715226633Sdim if (Opc == TargetOpcode::EXTRACT_SUBREG || 716206083Srdivacky Opc == TargetOpcode::INSERT_SUBREG || 717206083Srdivacky Opc == TargetOpcode::SUBREG_TO_REG) { 718208599Srdivacky EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned); 719206083Srdivacky return; 720206083Srdivacky } 721198090Srdivacky 722206083Srdivacky // Handle COPY_TO_REGCLASS specially. 723206083Srdivacky if (Opc == TargetOpcode::COPY_TO_REGCLASS) { 724206083Srdivacky EmitCopyToRegClassNode(Node, VRBaseMap); 725206083Srdivacky return; 726206083Srdivacky } 727198090Srdivacky 728207618Srdivacky // Handle REG_SEQUENCE specially. 729207618Srdivacky if (Opc == TargetOpcode::REG_SEQUENCE) { 730208599Srdivacky EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned); 731207618Srdivacky return; 732207618Srdivacky } 733207618Srdivacky 734206083Srdivacky if (Opc == TargetOpcode::IMPLICIT_DEF) 735206083Srdivacky // We want a unique VR for each IMPLICIT_DEF use. 736206083Srdivacky return; 737226633Sdim 738224145Sdim const MCInstrDesc &II = TII->get(Opc); 739206083Srdivacky unsigned NumResults = CountResults(Node); 740263508Sdim unsigned NumDefs = II.getNumDefs(); 741263508Sdim const uint16_t *ScratchRegs = NULL; 742263508Sdim 743263508Sdim // Handle PATCHPOINT specially and then use the generic code. 744263508Sdim if (Opc == TargetOpcode::PATCHPOINT) { 745263508Sdim unsigned CC = Node->getConstantOperandVal(PatchPointOpers::CCPos); 746263508Sdim NumDefs = NumResults; 747263508Sdim ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC); 748263508Sdim } 749263508Sdim 750239462Sdim unsigned NumImpUses = 0; 751243830Sdim unsigned NodeOperands = 752263508Sdim countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses); 753263508Sdim bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=0; 754198090Srdivacky#ifndef NDEBUG 755206083Srdivacky unsigned NumMIOperands = NodeOperands + NumResults; 756206083Srdivacky if (II.isVariadic()) 757206083Srdivacky assert(NumMIOperands >= II.getNumOperands() && 758206083Srdivacky "Too few operands for a variadic node!"); 759206083Srdivacky else 760206083Srdivacky assert(NumMIOperands >= II.getNumOperands() && 761239462Sdim NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + 762239462Sdim NumImpUses && 763206083Srdivacky "#operands for dag node doesn't match .td file!"); 764198090Srdivacky#endif 765198090Srdivacky 766206083Srdivacky // Create the new machine instruction. 767249423Sdim MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II); 768210299Sed 769206083Srdivacky // Add result register values for things that are defined by this 770206083Srdivacky // instruction. 771206083Srdivacky if (NumResults) 772249423Sdim CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap); 773226633Sdim 774206083Srdivacky // Emit all of the actual operands of this instruction, adding them to the 775206083Srdivacky // instruction as appropriate. 776263508Sdim bool HasOptPRefs = NumDefs > NumResults; 777206083Srdivacky assert((!HasOptPRefs || !HasPhysRegOuts) && 778206083Srdivacky "Unable to cope with optional defs and phys regs defs!"); 779263508Sdim unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0; 780206083Srdivacky for (unsigned i = NumSkip; i != NodeOperands; ++i) 781263508Sdim AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II, 782208599Srdivacky VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned); 783198090Srdivacky 784263508Sdim // Add scratch registers as implicit def and early clobber 785263508Sdim if (ScratchRegs) 786263508Sdim for (unsigned i = 0; ScratchRegs[i]; ++i) 787263508Sdim MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine | 788263508Sdim RegState::EarlyClobber); 789263508Sdim 790206083Srdivacky // Transfer all of the memory reference descriptions of this instruction. 791249423Sdim MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 792206083Srdivacky cast<MachineSDNode>(Node)->memoperands_end()); 793198090Srdivacky 794210299Sed // Insert the instruction into position in the block. This needs to 795210299Sed // happen before any custom inserter hook is called so that the 796210299Sed // hook knows where in the block to insert the replacement code. 797249423Sdim MBB->insert(InsertPos, MIB); 798210299Sed 799234353Sdim // The MachineInstr may also define physregs instead of virtregs. These 800234353Sdim // physreg values can reach other instructions in different ways: 801234353Sdim // 802234353Sdim // 1. When there is a use of a Node value beyond the explicitly defined 803234353Sdim // virtual registers, we emit a CopyFromReg for one of the implicitly 804234353Sdim // defined physregs. This only happens when HasPhysRegOuts is true. 805234353Sdim // 806234353Sdim // 2. A CopyFromReg reading a physreg may be glued to this instruction. 807234353Sdim // 808234353Sdim // 3. A glued instruction may implicitly use a physreg. 809234353Sdim // 810234353Sdim // 4. A glued instruction may use a RegisterSDNode operand. 811234353Sdim // 812234353Sdim // Collect all the used physreg defs, and make sure that any unused physreg 813234353Sdim // defs are marked as dead. 814234353Sdim SmallVector<unsigned, 8> UsedRegs; 815234353Sdim 816218893Sdim // Additional results must be physical register defs. 817206083Srdivacky if (HasPhysRegOuts) { 818263508Sdim for (unsigned i = NumDefs; i < NumResults; ++i) { 819263508Sdim unsigned Reg = II.getImplicitDefs()[i - NumDefs]; 820234353Sdim if (!Node->hasAnyUseOfValue(i)) 821234353Sdim continue; 822234353Sdim // This implicitly defined physreg has a use. 823234353Sdim UsedRegs.push_back(Reg); 824234353Sdim EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 825198090Srdivacky } 826198090Srdivacky } 827226633Sdim 828234353Sdim // Scan the glue chain for any used physregs. 829234353Sdim if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) { 830234353Sdim for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) { 831234353Sdim if (F->getOpcode() == ISD::CopyFromReg) { 832234353Sdim UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg()); 833234353Sdim continue; 834234353Sdim } else if (F->getOpcode() == ISD::CopyToReg) { 835234353Sdim // Skip CopyToReg nodes that are internal to the glue chain. 836234353Sdim continue; 837234353Sdim } 838234353Sdim // Collect declared implicit uses. 839234353Sdim const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); 840234353Sdim UsedRegs.append(MCID.getImplicitUses(), 841234353Sdim MCID.getImplicitUses() + MCID.getNumImplicitUses()); 842234353Sdim // In addition to declared implicit uses, we must also check for 843234353Sdim // direct RegisterSDNode operands. 844234353Sdim for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i) 845234353Sdim if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) { 846234353Sdim unsigned Reg = R->getReg(); 847234353Sdim if (TargetRegisterInfo::isPhysicalRegister(Reg)) 848234353Sdim UsedRegs.push_back(Reg); 849234353Sdim } 850206083Srdivacky } 851234353Sdim } 852226633Sdim 853234353Sdim // Finally mark unused registers as dead. 854234353Sdim if (!UsedRegs.empty() || II.getImplicitDefs()) 855249423Sdim MIB->setPhysRegsDeadExcept(UsedRegs, *TRI); 856234353Sdim 857226633Sdim // Run post-isel target hook to adjust this instruction if needed. 858226633Sdim#ifdef NDEBUG 859226633Sdim if (II.hasPostISelHook()) 860226633Sdim#endif 861249423Sdim TLI->AdjustInstrPostInstrSelection(MIB, Node); 862206083Srdivacky} 863198090Srdivacky 864206083Srdivacky/// EmitSpecialNode - Generate machine code for a target-independent node and 865206083Srdivacky/// needed dependencies. 866206083Srdivackyvoid InstrEmitter:: 867206083SrdivackyEmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 868206083Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap) { 869198090Srdivacky switch (Node->getOpcode()) { 870198090Srdivacky default: 871198090Srdivacky#ifndef NDEBUG 872198090Srdivacky Node->dump(); 873198090Srdivacky#endif 874198090Srdivacky llvm_unreachable("This target-independent node should have been selected!"); 875198090Srdivacky case ISD::EntryToken: 876198090Srdivacky llvm_unreachable("EntryToken should have been excluded from the schedule!"); 877198090Srdivacky case ISD::MERGE_VALUES: 878198090Srdivacky case ISD::TokenFactor: // fall thru 879198090Srdivacky break; 880198090Srdivacky case ISD::CopyToReg: { 881198090Srdivacky unsigned SrcReg; 882198090Srdivacky SDValue SrcVal = Node->getOperand(2); 883198090Srdivacky if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 884198090Srdivacky SrcReg = R->getReg(); 885198090Srdivacky else 886198090Srdivacky SrcReg = getVR(SrcVal, VRBaseMap); 887226633Sdim 888198090Srdivacky unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 889198090Srdivacky if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 890198090Srdivacky break; 891198090Srdivacky 892210299Sed BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 893210299Sed DestReg).addReg(SrcReg); 894198090Srdivacky break; 895198090Srdivacky } 896198090Srdivacky case ISD::CopyFromReg: { 897198090Srdivacky unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 898198090Srdivacky EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 899198090Srdivacky break; 900198090Srdivacky } 901205218Srdivacky case ISD::EH_LABEL: { 902205218Srdivacky MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel(); 903205218Srdivacky BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 904205218Srdivacky TII->get(TargetOpcode::EH_LABEL)).addSym(S); 905205218Srdivacky break; 906205218Srdivacky } 907226633Sdim 908243830Sdim case ISD::LIFETIME_START: 909243830Sdim case ISD::LIFETIME_END: { 910243830Sdim unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ? 911243830Sdim TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END; 912243830Sdim 913243830Sdim FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1)); 914243830Sdim BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp)) 915243830Sdim .addFrameIndex(FI->getIndex()); 916243830Sdim break; 917243830Sdim } 918243830Sdim 919198090Srdivacky case ISD::INLINEASM: { 920198090Srdivacky unsigned NumOps = Node->getNumOperands(); 921218893Sdim if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) 922218893Sdim --NumOps; // Ignore the glue operand. 923226633Sdim 924198090Srdivacky // Create the inline asm machine instruction. 925249423Sdim MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), 926249423Sdim TII->get(TargetOpcode::INLINEASM)); 927198090Srdivacky 928198090Srdivacky // Add the asm string as an external symbol operand. 929207618Srdivacky SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString); 930207618Srdivacky const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol(); 931249423Sdim MIB.addExternalSymbol(AsmStr); 932226633Sdim 933243830Sdim // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore 934243830Sdim // bits. 935218893Sdim int64_t ExtraInfo = 936218893Sdim cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))-> 937210299Sed getZExtValue(); 938249423Sdim MIB.addImm(ExtraInfo); 939210299Sed 940243830Sdim // Remember to operand index of the group flags. 941243830Sdim SmallVector<unsigned, 8> GroupIdx; 942243830Sdim 943198090Srdivacky // Add all of the operand registers to the instruction. 944207618Srdivacky for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 945198090Srdivacky unsigned Flags = 946198090Srdivacky cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 947243830Sdim const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 948226633Sdim 949249423Sdim GroupIdx.push_back(MIB->getNumOperands()); 950249423Sdim MIB.addImm(Flags); 951198090Srdivacky ++i; // Skip the ID value. 952226633Sdim 953207618Srdivacky switch (InlineAsm::getKind(Flags)) { 954198090Srdivacky default: llvm_unreachable("Bad flags!"); 955207618Srdivacky case InlineAsm::Kind_RegDef: 956243830Sdim for (unsigned j = 0; j != NumVals; ++j, ++i) { 957198090Srdivacky unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 958210299Sed // FIXME: Add dead flags for physical and virtual registers defined. 959210299Sed // For now, mark physical register defs as implicit to help fast 960210299Sed // regalloc. This makes inline asm look a lot like calls. 961249423Sdim MIB.addReg(Reg, RegState::Define | 962249423Sdim getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg))); 963198090Srdivacky } 964198090Srdivacky break; 965207618Srdivacky case InlineAsm::Kind_RegDefEarlyClobber: 966224145Sdim case InlineAsm::Kind_Clobber: 967243830Sdim for (unsigned j = 0; j != NumVals; ++j, ++i) { 968198090Srdivacky unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 969249423Sdim MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber | 970249423Sdim getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg))); 971198090Srdivacky } 972198090Srdivacky break; 973207618Srdivacky case InlineAsm::Kind_RegUse: // Use of register. 974207618Srdivacky case InlineAsm::Kind_Imm: // Immediate. 975207618Srdivacky case InlineAsm::Kind_Mem: // Addressing mode. 976198090Srdivacky // The addressing mode has been selected, just add all of the 977198090Srdivacky // operands to the machine instruction. 978243830Sdim for (unsigned j = 0; j != NumVals; ++j, ++i) 979249423Sdim AddOperand(MIB, Node->getOperand(i), 0, 0, VRBaseMap, 980208599Srdivacky /*IsDebug=*/false, IsClone, IsCloned); 981243830Sdim 982243830Sdim // Manually set isTied bits. 983243830Sdim if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) { 984243830Sdim unsigned DefGroup = 0; 985243830Sdim if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) { 986243830Sdim unsigned DefIdx = GroupIdx[DefGroup] + 1; 987243830Sdim unsigned UseIdx = GroupIdx.back() + 1; 988243830Sdim for (unsigned j = 0; j != NumVals; ++j) 989249423Sdim MIB->tieOperands(DefIdx + j, UseIdx + j); 990243830Sdim } 991243830Sdim } 992198090Srdivacky break; 993198090Srdivacky } 994198090Srdivacky } 995226633Sdim 996207618Srdivacky // Get the mdnode from the asm if it exists and add it to the instruction. 997207618Srdivacky SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode); 998207618Srdivacky const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD(); 999207618Srdivacky if (MD) 1000249423Sdim MIB.addMetadata(MD); 1001226633Sdim 1002249423Sdim MBB->insert(InsertPos, MIB); 1003198090Srdivacky break; 1004198090Srdivacky } 1005198090Srdivacky } 1006198090Srdivacky} 1007198090Srdivacky 1008198090Srdivacky/// InstrEmitter - Construct an InstrEmitter and set it to start inserting 1009198090Srdivacky/// at the given position in the given block. 1010198090SrdivackyInstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 1011198090Srdivacky MachineBasicBlock::iterator insertpos) 1012198090Srdivacky : MF(mbb->getParent()), 1013198090Srdivacky MRI(&MF->getRegInfo()), 1014198090Srdivacky TM(&MF->getTarget()), 1015198090Srdivacky TII(TM->getInstrInfo()), 1016198090Srdivacky TRI(TM->getRegisterInfo()), 1017198090Srdivacky TLI(TM->getTargetLowering()), 1018198090Srdivacky MBB(mbb), InsertPos(insertpos) { 1019198090Srdivacky} 1020