Searched refs:Cond (Results 1 - 25 of 148) sorted by relevance

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/freebsd-10-stable/contrib/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp73 SmallVectorImpl<MachineOperand> &Cond) const {
80 Cond.push_back(MachineOperand::CreateImm(Opc));
83 Cond.push_back(Inst->getOperand(i));
89 SmallVectorImpl<MachineOperand> &Cond,
92 BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
99 const SmallVectorImpl<MachineOperand>& Cond)
101 unsigned Opc = Cond[0].getImm();
105 for (unsigned i = 1; i < Cond.size(); ++i) {
106 if (Cond[i].isReg())
107 MIB.addReg(Cond[
86 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
117 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
184 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify, SmallVectorImpl<MachineInstr*> &BranchInstrs) const argument
[all...]
H A DMipsInstrInfo.h52 SmallVectorImpl<MachineOperand> &Cond,
59 const SmallVectorImpl<MachineOperand> &Cond,
63 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
67 SmallVectorImpl<MachineOperand> &Cond,
132 SmallVectorImpl<MachineOperand> &Cond) const;
135 const SmallVectorImpl<MachineOperand>& Cond) const;
/freebsd-10-stable/contrib/llvm/tools/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
H A DConstraintManager.h68 DefinedSVal Cond,
75 ProgramStatePair assumeDual(ProgramStateRef State, DefinedSVal Cond) { argument
76 ProgramStateRef StTrue = assume(State, Cond, true);
78 // If StTrue is infeasible, asserting the falseness of Cond is unnecessary
86 assert(assume(State, Cond, false) && "System is over constrained.");
91 ProgramStateRef StFalse = assume(State, Cond, false);
/freebsd-10-stable/contrib/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp193 SmallVectorImpl<MachineOperand> &Cond,
226 Cond.push_back(MachineOperand::CreateImm(BranchCode));
227 Cond.push_back(LastInst->getOperand(0));
248 Cond.push_back(MachineOperand::CreateImm(BranchCode));
249 Cond.push_back(SecondLastInst->getOperand(0));
281 const SmallVectorImpl<MachineOperand> &Cond,
285 assert((Cond.size() == 2 || Cond.size() == 0) &&
289 if (Cond.empty()) {
294 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[
191 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
279 InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
[all...]
H A DXCoreInstrInfo.h55 SmallVectorImpl<MachineOperand> &Cond,
60 const SmallVectorImpl<MachineOperand> &Cond,
83 SmallVectorImpl<MachineOperand> &Cond) const;
/freebsd-10-stable/contrib/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.h75 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
79 SmallVectorImpl<MachineOperand> &Cond,
85 const SmallVectorImpl<MachineOperand> &Cond,
H A DMSP430InstrInfo.cpp130 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
131 assert(Cond.size() == 1 && "Invalid Xbranch condition!");
133 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
157 Cond[0].setImm(CC);
175 SmallVectorImpl<MachineOperand> &Cond,
210 Cond.clear();
234 if (Cond.empty()) {
237 Cond.push_back(MachineOperand::CreateImm(BranchCode));
243 assert(Cond.size() == 1);
251 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[
172 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
263 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
[all...]
H A DMSP430BranchSelector.cpp150 SmallVector<MachineOperand, 1> Cond; local
151 Cond.push_back(I->getOperand(1));
154 TII->ReverseBranchCondition(Cond);
156 .addImm(4).addOperand(Cond[0]);
/freebsd-10-stable/contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/
H A DSimpleConstraintManager.cpp69 DefinedSVal Cond,
72 if (Optional<Loc> LV = Cond.getAs<Loc>()) {
81 Cond = SVB.evalCast(*LV, SVB.getContext().BoolTy, T).castAs<DefinedSVal>();
84 return assume(state, Cond.castAs<NonLoc>(), Assumption);
115 NonLoc Cond,
120 if (!canReasonAbout(Cond)) {
122 SymbolRef sym = Cond.getAsSymExpr();
126 switch (Cond.getSubKind()) {
131 nonloc::SymbolVal SV = Cond.castAs<nonloc::SymbolVal>();
182 bool b = Cond
68 assume(ProgramStateRef state, DefinedSVal Cond, bool Assumption) argument
114 assumeAux(ProgramStateRef state, NonLoc Cond, bool Assumption) argument
[all...]
H A DSimpleConstraintManager.h36 ProgramStateRef assume(ProgramStateRef state, DefinedSVal Cond,
39 ProgramStateRef assume(ProgramStateRef state, NonLoc Cond, bool Assumption);
88 NonLoc Cond,
/freebsd-10-stable/contrib/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h59 SmallVectorImpl<MachineOperand> &Cond,
63 const SmallVectorImpl<MachineOperand> &Cond,
66 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
H A DAArch64InstrInfo.cpp157 /// setting TBB to the destination basic block and populating the Cond vector
162 SmallVectorImpl<MachineOperand> &Cond) {
171 Cond.push_back(MachineOperand::CreateImm(I->getOpcode()));
172 Cond.push_back(I->getOperand(0));
180 Cond.push_back(MachineOperand::CreateImm(I->getOpcode()));
181 Cond.push_back(I->getOperand(0));
182 Cond.push_back(I->getOperand(1));
194 SmallVectorImpl<MachineOperand> &Cond,
220 classifyCondBranch(LastInst, TBB, Cond);
256 Cond
161 classifyCondBranch(MachineInstr *I, MachineBasicBlock *&TBB, SmallVectorImpl<MachineOperand> &Cond) argument
192 AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
321 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
[all...]
/freebsd-10-stable/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp171 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const {
188 Cond.push_back(LastInst->getOperand(0));
206 Cond.push_back(SecondLastInst->getOperand(0));
252 const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const {
255 assert((Cond.size() == 1 || Cond.size() == 0) &&
260 if (Cond.empty()) // Unconditional branch
263 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
269 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
169 AnalyzeBranch( MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
250 InsertBranch( MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
H A DNVPTXInstrInfo.h66 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
70 const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
/freebsd-10-stable/contrib/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.h68 SmallVectorImpl<MachineOperand> &Cond,
75 const SmallVectorImpl<MachineOperand> &Cond,
/freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h117 SmallVectorImpl<MachineOperand> &Cond,
122 const SmallVectorImpl<MachineOperand> &Cond,
127 const SmallVectorImpl<MachineOperand> &Cond,
132 const SmallVectorImpl<MachineOperand> &Cond,
153 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
H A DPPCInstrInfo.cpp231 SmallVectorImpl<MachineOperand> &Cond,
263 Cond.push_back(LastInst->getOperand(0));
264 Cond.push_back(LastInst->getOperand(1));
273 Cond.push_back(MachineOperand::CreateImm(1));
274 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
284 Cond.push_back(MachineOperand::CreateImm(0));
285 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
309 Cond.push_back(SecondLastInst->getOperand(0));
310 Cond.push_back(SecondLastInst->getOperand(1));
322 Cond
229 AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
392 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
430 canInsertSelect(const MachineBasicBlock &MBB, const SmallVectorImpl<MachineOperand> &Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
470 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc dl, unsigned DestReg, const SmallVectorImpl<MachineOperand> &Cond, unsigned TrueReg, unsigned FalseReg) const argument
[all...]
/freebsd-10-stable/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp1122 ISD::CondCode Cond, bool foldBooleans,
1127 switch (Cond) {
1141 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
1158 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1160 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1163 Cond = ISD::SETNE;
1167 Cond = ISD::SETEQ;
1171 Zero, Cond);
1188 if ((Cond
1121 SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const argument
[all...]
/freebsd-10-stable/contrib/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h765 inline bool isTrueWhenEqual(CondCode Cond) { argument
766 return ((int)Cond & 1) != 0;
773 inline unsigned getUnorderedFlavor(CondCode Cond) { argument
774 return ((int)Cond >> 3) & 3;
/freebsd-10-stable/contrib/llvm/tools/clang/lib/Sema/
H A DScopeInfo.cpp141 if (const ConditionalOperator *Cond = dyn_cast<ConditionalOperator>(E)) {
142 markSafeWeakUse(Cond->getTrueExpr());
143 markSafeWeakUse(Cond->getFalseExpr());
147 if (const BinaryConditionalOperator *Cond =
149 markSafeWeakUse(Cond->getCommon());
150 markSafeWeakUse(Cond->getFalseExpr());
/freebsd-10-stable/contrib/llvm/lib/Target/R600/
H A DSIAnnotateControlFlow.cpp82 void handleLoopCondition(Value *Cond);
205 void SIAnnotateControlFlow::handleLoopCondition(Value *Cond) { argument
206 if (PHINode *Phi = dyn_cast<PHINode>(Cond)) {
248 } else if (Instruction *Inst = dyn_cast<Instruction>(Cond)) {
251 Value *Args[] = { Cond, PhiInserter.GetValueAtEndOfBlock(Parent) };
268 Value *Cond = Term->getCondition(); local
270 handleLoopCondition(Cond);
/freebsd-10-stable/contrib/llvm/lib/Transforms/Scalar/
H A DCorrelatedValuePropagation.cpp206 Value *Cond = SI->getCondition(); local
211 if (isa<Instruction>(Cond) && cast<Instruction>(Cond)->getParent() == BB)
231 Cond, Case, *PI, BB);
260 Cond = SI->getCondition();
/freebsd-10-stable/tools/regression/ia64/emulated/
H A Dtest.c35 #define Cond 2 macro
161 #elif TYPE == Cond
/freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp121 const SmallVectorImpl<MachineOperand> &Cond,
133 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
139 if (Cond.empty()) {
145 SmallVector<MachineOperand, 4> Cond; local
147 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
152 ReverseBranchCondition(Cond);
154 return InsertBranch(MBB, TBB, 0, Cond, DL);
160 get(BccOpc)).addReg(Cond[regPo
119 InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
172 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
[all...]
/freebsd-10-stable/contrib/llvm/lib/IR/
H A DConstantFold.h35 Constant *ConstantFoldSelectInstruction(Constant *Cond,

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