1249259Sdim//===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim// This file contains the AArch64 implementation of the TargetInstrInfo class. 11249259Sdim// 12249259Sdim//===----------------------------------------------------------------------===// 13249259Sdim 14249259Sdim#ifndef LLVM_TARGET_AARCH64INSTRINFO_H 15249259Sdim#define LLVM_TARGET_AARCH64INSTRINFO_H 16249259Sdim 17249259Sdim#include "llvm/Target/TargetInstrInfo.h" 18249259Sdim#include "AArch64RegisterInfo.h" 19249259Sdim 20249259Sdim#define GET_INSTRINFO_HEADER 21249259Sdim#include "AArch64GenInstrInfo.inc" 22249259Sdim 23249259Sdimnamespace llvm { 24249259Sdim 25249259Sdimclass AArch64Subtarget; 26249259Sdim 27249259Sdimclass AArch64InstrInfo : public AArch64GenInstrInfo { 28249259Sdim const AArch64RegisterInfo RI; 29249259Sdim const AArch64Subtarget &Subtarget; 30249259Sdimpublic: 31249259Sdim explicit AArch64InstrInfo(const AArch64Subtarget &TM); 32249259Sdim 33249259Sdim /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 34249259Sdim /// such, whenever a client has an instance of instruction info, it should 35249259Sdim /// always be able to get register info as well (through this method). 36249259Sdim /// 37249259Sdim const TargetRegisterInfo &getRegisterInfo() const { return RI; } 38249259Sdim 39249259Sdim const AArch64Subtarget &getSubTarget() const { return Subtarget; } 40249259Sdim 41249259Sdim void copyPhysReg(MachineBasicBlock &MBB, 42249259Sdim MachineBasicBlock::iterator I, DebugLoc DL, 43249259Sdim unsigned DestReg, unsigned SrcReg, 44249259Sdim bool KillSrc) const; 45249259Sdim 46249259Sdim void storeRegToStackSlot(MachineBasicBlock &MBB, 47249259Sdim MachineBasicBlock::iterator MI, 48249259Sdim unsigned SrcReg, bool isKill, int FrameIndex, 49249259Sdim const TargetRegisterClass *RC, 50249259Sdim const TargetRegisterInfo *TRI) const; 51249259Sdim void loadRegFromStackSlot(MachineBasicBlock &MBB, 52249259Sdim MachineBasicBlock::iterator MBBI, 53249259Sdim unsigned DestReg, int FrameIdx, 54249259Sdim const TargetRegisterClass *RC, 55249259Sdim const TargetRegisterInfo *TRI) const; 56249259Sdim 57249259Sdim bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 58249259Sdim MachineBasicBlock *&FBB, 59249259Sdim SmallVectorImpl<MachineOperand> &Cond, 60249259Sdim bool AllowModify = false) const; 61249259Sdim unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 62249259Sdim MachineBasicBlock *FBB, 63249259Sdim const SmallVectorImpl<MachineOperand> &Cond, 64249259Sdim DebugLoc DL) const; 65249259Sdim unsigned RemoveBranch(MachineBasicBlock &MBB) const; 66249259Sdim bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 67249259Sdim 68249259Sdim bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; 69249259Sdim 70249259Sdim /// Look through the instructions in this function and work out the largest 71249259Sdim /// the stack frame can be while maintaining the ability to address local 72249259Sdim /// slots with no complexities. 73249259Sdim unsigned estimateRSStackLimit(MachineFunction &MF) const; 74249259Sdim 75249259Sdim /// getAddressConstraints - For loads and stores (and PRFMs) taking an 76249259Sdim /// immediate offset, this function determines the constraints required for 77249259Sdim /// the immediate. It must satisfy: 78249259Sdim /// + MinOffset <= imm <= MaxOffset 79249259Sdim /// + imm % OffsetScale == 0 80249259Sdim void getAddressConstraints(const MachineInstr &MI, int &AccessScale, 81249259Sdim int &MinOffset, int &MaxOffset) const; 82249259Sdim 83249259Sdim 84249259Sdim unsigned getInstSizeInBytes(const MachineInstr &MI) const; 85249259Sdim 86249259Sdim unsigned getInstBundleLength(const MachineInstr &MI) const; 87249259Sdim 88249259Sdim}; 89249259Sdim 90249259Sdimbool rewriteA64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 91249259Sdim unsigned FrameReg, int &Offset, 92249259Sdim const AArch64InstrInfo &TII); 93249259Sdim 94249259Sdim 95249259Sdimvoid emitRegUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 96249259Sdim DebugLoc dl, const TargetInstrInfo &TII, 97249259Sdim unsigned DstReg, unsigned SrcReg, unsigned ScratchReg, 98249259Sdim int64_t NumBytes, 99249259Sdim MachineInstr::MIFlag MIFlags = MachineInstr::NoFlags); 100249259Sdim 101249259Sdimvoid emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 102249259Sdim DebugLoc dl, const TargetInstrInfo &TII, 103249259Sdim unsigned ScratchReg, int64_t NumBytes, 104249259Sdim MachineInstr::MIFlag MIFlags = MachineInstr::NoFlags); 105249259Sdim 106249259Sdim} 107249259Sdim 108249259Sdim#endif 109