Searched refs:rdmsr64 (Results 1 - 16 of 16) sorted by relevance
| /darwin-on-arm/xnu/osfmk/i386/ |
| H A D | machine_check.c | 109 ia32_mcg_cap.u64 = rdmsr64(IA32_MCG_CAP);
216 rdmsr64(IA32_MCG_CTL) : 0ULL;
217 mca_state->mca_mcg_status.u64 = rdmsr64(IA32_MCG_STATUS);
221 bank->mca_mci_ctl = rdmsr64(IA32_MCi_CTL(i));
222 bank->mca_mci_status.u64 = rdmsr64(IA32_MCi_STATUS(i));
226 rdmsr64(IA32_MCi_MISC(i)) : 0ULL;
228 rdmsr64(IA32_MCi_ADDR(i)) : 0ULL;
252 kdb_printf(" IA32_MCG_RAX: 0x%016qx\n", rdmsr64(IA32_MCG_RAX));
253 kdb_printf(" IA32_MCG_RBX: 0x%016qx\n", rdmsr64(IA32_MCG_RBX));
254 kdb_printf(" IA32_MCG_RCX: 0x%016qx\n", rdmsr64(IA32_MCG_RC
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| H A D | mtrr.c | 134 range[i].base = rdmsr64(MSR_IA32_MTRR_PHYSBASE(i));
135 range[i].mask = rdmsr64(MSR_IA32_MTRR_PHYSMASK(i));
168 range[0].types = rdmsr64(MSR_IA32_MTRR_FIX64K_00000);
169 range[1].types = rdmsr64(MSR_IA32_MTRR_FIX16K_80000);
170 range[2].types = rdmsr64(MSR_IA32_MTRR_FIX16K_A0000);
172 range[3 + i].types = rdmsr64(MSR_IA32_MTRR_FIX4K_C0000 + i);
200 match = range[0].types == rdmsr64(MSR_IA32_MTRR_FIX64K_00000) &&
201 range[1].types == rdmsr64(MSR_IA32_MTRR_FIX16K_80000) &&
202 range[2].types == rdmsr64(MSR_IA32_MTRR_FIX16K_A0000);
205 rdmsr64(MSR_IA32_MTRR_FIX4K_C000
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| H A D | startup64.c | 75 (rdmsr64(MSR_IA32_EFER) & MSR_IA32_EFER_LMA) != 0)
122 if ((rdmsr64(MSR_IA32_EFER) & MSR_IA32_EFER_LMA) == 0)
138 (rdmsr64(MSR_IA32_EFER) & MSR_IA32_EFER_LMA) == 0)
181 if ((rdmsr64(MSR_IA32_EFER) & MSR_IA32_EFER_LMA) != 0)
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| H A D | tsc.c | 177 msr_flex_ratio = rdmsr64(MSR_FLEX_RATIO);
178 msr_platform_info = rdmsr64(MSR_PLATFORM_INFO);
201 prfsts = rdmsr64(IA32_PERF_STS);
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| H A D | i386_init.c | 426 DBG("CPU: %d, GSBASE initial value: 0x%llx\n", cpu, rdmsr64(MSR_IA32_GS_BASE));
448 wrmsr64(MSR_IA32_EFER, rdmsr64(MSR_IA32_EFER) | MSR_IA32_EFER_NXE);
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| H A D | proc_reg.h | 436 static inline uint64_t rdmsr64(uint32_t msr) function
467 static inline uint64_t rdmsr64(uint32_t msr) function
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| H A D | bsd_i386_native.c | 211 (pcb->cthread_self != rdmsr64(MSR_IA32_KERNEL_GS_BASE)))
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| H A D | cpuid.c | 582 (uint32_t) (rdmsr64(MSR_IA32_BIOS_SIGN_ID) >> 32);
594 info_p->cpuid_processor_flag = (rdmsr64(MSR_IA32_PLATFORM_ID)>> 50) & 0x7;
830 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT);
839 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT);
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| H A D | lapic_native.c | 226 return rdmsr64(LAPIC_MSR(ICR));;
629 return rdmsr64(MSR_IA32_TSC_DEADLINE);
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| H A D | mp_desc.c | 736 wrmsr64(MSR_IA32_EFER, rdmsr64(MSR_IA32_EFER) | MSR_IA32_EFER_SCE);
764 rdmsr64(MSR_IA32_KERNEL_GS_BASE));
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| H A D | trap.c | 253 kprintf("Current GS base MSR 0x%llx\n", rdmsr64(MSR_IA32_GS_BASE));
254 kprintf("Kernel GS base MSR 0x%llx\n", rdmsr64(MSR_IA32_KERNEL_GS_BASE));
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| H A D | pcb_native.c | 207 if ((cdp->cpu_uber.cu_user_gs_base != pcb->cthread_self) || (pcb->cthread_self != rdmsr64(MSR_IA32_KERNEL_GS_BASE))) {
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| /darwin-on-arm/xnu/osfmk/i386/vmx/ |
| H A D | vmx_cpu.c | 64 (rdmsr64(MSR_IA32_FEATURE_CONTROL) & MSR_IA32_FEATCTL_VMXON));
101 msr_image = rdmsr64(MSR_IA32_FEATURE_CONTROL);
143 msr_image = rdmsr64(MSR_IA32_VMX_BASIC);
149 msr_image = rdmsr64(MSR_IA32_VMXPINBASED_CTLS);
154 msr_image = rdmsr64(MSR_IA32_PROCBASED_CTLS);
159 msr_image = rdmsr64(MSR_IA32_VMX_EXIT_CTLS);
164 msr_image = rdmsr64(MSR_IA32_VMX_ENTRY_CTLS);
169 msr_image = rdmsr64(MSR_IA32_VMX_MISC);
179 specs->cr0_fixed_0 = (uint32_t)rdmsr64(MSR_IA32_VMX_CR0_FIXED0) & 0xFFFFFFFF;
180 specs->cr0_fixed_1 = (uint32_t)rdmsr64(MSR_IA32_VMX_CR0_FIXED
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| /darwin-on-arm/xnu/pexpert/i386/ |
| H A D | pe_kprintf.c | 110 if (rdmsr64(MSR_IA32_GS_BASE) == 0) {
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| /darwin-on-arm/xnu/osfmk/i386/commpage/ |
| H A D | commpage.c | 285 uint64_t misc_enable = rdmsr64(MSR_IA32_MISC_ENABLE);
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| /darwin-on-arm/xnu/osfmk/kdp/ml/i386/ |
| H A D | kdp_x86_common.c | 373 *value = rdmsr64(msr);
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