1/* 2 * Copyright (c) 2000-2010 Apple Inc. All rights reserved. 3 * 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. The rights granted to you under the License 10 * may not be used to create, or enable the creation or redistribution of, 11 * unlawful or unlicensed copies of an Apple operating system, or to 12 * circumvent, violate, or enable the circumvention or violation of, any 13 * terms of an Apple operating system software license agreement. 14 * 15 * Please obtain a copy of the License at 16 * http://www.opensource.apple.com/apsl/ and read it before using this file. 17 * 18 * The Original Code and all software distributed under the License are 19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 23 * Please see the License for the specific language governing rights and 24 * limitations under the License. 25 * 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 27 */ 28/* 29 * @OSF_COPYRIGHT@ 30 */ 31/* CMU_ENDHIST */ 32/* 33 * Mach Operating System 34 * Copyright (c) 1991,1990 Carnegie Mellon University 35 * All Rights Reserved. 36 * 37 * Permission to use, copy, modify and distribute this software and its 38 * documentation is hereby granted, provided that both the copyright 39 * notice and this permission notice appear in all copies of the 40 * software, derivative works or modified versions, and any portions 41 * thereof, and that both notices appear in supporting documentation. 42 * 43 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 44 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 45 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 46 * 47 * Carnegie Mellon requests users of this software to return to 48 * 49 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 50 * School of Computer Science 51 * Carnegie Mellon University 52 * Pittsburgh PA 15213-3890 53 * 54 * any improvements or extensions that they make and grant Carnegie Mellon 55 * the rights to redistribute these changes. 56 */ 57 58/* 59 */ 60 61/* 62 * Processor registers for i386 and i486. 63 */ 64#ifndef _I386_PROC_REG_H_ 65#define _I386_PROC_REG_H_ 66 67/* 68 * Model Specific Registers 69 */ 70#define MSR_P5_TSC 0x10 /* Time Stamp Register */ 71#define MSR_P5_CESR 0x11 /* Control and Event Select Register */ 72#define MSR_P5_CTR0 0x12 /* Counter #0 */ 73#define MSR_P5_CTR1 0x13 /* Counter #1 */ 74 75#define MSR_P5_CESR_PC 0x0200 /* Pin Control */ 76#define MSR_P5_CESR_CC 0x01C0 /* Counter Control mask */ 77#define MSR_P5_CESR_ES 0x003F /* Event Control mask */ 78 79#define MSR_P5_CESR_SHIFT 16 /* Shift to get Counter 1 */ 80#define MSR_P5_CESR_MASK (MSR_P5_CESR_PC|\ 81 MSR_P5_CESR_CC|\ 82 MSR_P5_CESR_ES) /* Mask Counter */ 83 84#define MSR_P5_CESR_CC_CLOCK 0x0100 /* Clock Counting (otherwise Event) */ 85#define MSR_P5_CESR_CC_DISABLE 0x0000 /* Disable counter */ 86#define MSR_P5_CESR_CC_CPL012 0x0040 /* Count if the CPL == 0, 1, 2 */ 87#define MSR_P5_CESR_CC_CPL3 0x0080 /* Count if the CPL == 3 */ 88#define MSR_P5_CESR_CC_CPL 0x00C0 /* Count regardless of the CPL */ 89 90#define MSR_P5_CESR_ES_DATA_READ 0x000000 /* Data Read */ 91#define MSR_P5_CESR_ES_DATA_WRITE 0x000001 /* Data Write */ 92#define MSR_P5_CESR_ES_DATA_RW 0x101000 /* Data Read or Write */ 93#define MSR_P5_CESR_ES_DATA_TLB_MISS 0x000010 /* Data TLB Miss */ 94#define MSR_P5_CESR_ES_DATA_READ_MISS 0x000011 /* Data Read Miss */ 95#define MSR_P5_CESR_ES_DATA_WRITE_MISS 0x000100 /* Data Write Miss */ 96#define MSR_P5_CESR_ES_DATA_RW_MISS 0x101001 /* Data Read or Write Miss */ 97#define MSR_P5_CESR_ES_HIT_EM 0x000101 /* Write (hit) to M|E state */ 98#define MSR_P5_CESR_ES_DATA_CACHE_WB 0x000110 /* Cache lines written back */ 99#define MSR_P5_CESR_ES_EXTERNAL_SNOOP 0x000111 /* External Snoop */ 100#define MSR_P5_CESR_ES_CACHE_SNOOP_HIT 0x001000 /* Data cache snoop hits */ 101#define MSR_P5_CESR_ES_MEM_ACCESS_PIPE 0x001001 /* Mem. access in both pipes */ 102#define MSR_P5_CESR_ES_BANK_CONFLICTS 0x001010 /* Bank conflicts */ 103#define MSR_P5_CESR_ES_MISALIGNED 0x001011 /* Misaligned Memory or I/O */ 104#define MSR_P5_CESR_ES_CODE_READ 0x001100 /* Code Read */ 105#define MSR_P5_CESR_ES_CODE_TLB_MISS 0x001101 /* Code TLB miss */ 106#define MSR_P5_CESR_ES_CODE_CACHE_MISS 0x001110 /* Code Cache miss */ 107#define MSR_P5_CESR_ES_SEGMENT_LOADED 0x001111 /* Any segment reg. loaded */ 108#define MSR_P5_CESR_ES_BRANCHE 0x010010 /* Branches */ 109#define MSR_P5_CESR_ES_BTB_HIT 0x010011 /* BTB Hits */ 110#define MSR_P5_CESR_ES_BRANCHE_BTB 0x010100 /* Taken branch or BTB Hit */ 111#define MSR_P5_CESR_ES_PIPELINE_FLUSH 0x010101 /* Pipeline Flushes */ 112#define MSR_P5_CESR_ES_INSTRUCTION 0x010110 /* Instruction executed */ 113#define MSR_P5_CESR_ES_INSTRUCTION_V 0x010111 /* Inst. executed (v-pipe) */ 114#define MSR_P5_CESR_ES_BUS_CYCLE 0x011000 /* Clocks while bus cycle */ 115#define MSR_P5_CESR_ES_FULL_WRITE_BUF 0x011001 /* Clocks while full wrt buf. */ 116#define MSR_P5_CESR_ES_DATA_MEM_READ 0x011010 /* Pipeline waiting for read */ 117#define MSR_P5_CESR_ES_WRITE_EM 0x011011 /* Stall on write E|M state */ 118#define MSR_P5_CESR_ES_LOCKED_CYCLE 0x011100 /* Locked bus cycles */ 119#define MSR_P5_CESR_ES_IO_CYCLE 0x011101 /* I/O Read or Write cycles */ 120#define MSR_P5_CESR_ES_NON_CACHEABLE 0x011110 /* Non-cacheable Mem. read */ 121#define MSR_P5_CESR_ES_AGI 0x011111 /* Stall because of AGI */ 122#define MSR_P5_CESR_ES_FLOP 0x100010 /* Floating Point operations */ 123#define MSR_P5_CESR_ES_BREAK_DR0 0x100011 /* Breakpoint matches on DR0 */ 124#define MSR_P5_CESR_ES_BREAK_DR1 0x100100 /* Breakpoint matches on DR1 */ 125#define MSR_P5_CESR_ES_BREAK_DR2 0x100101 /* Breakpoint matches on DR2 */ 126#define MSR_P5_CESR_ES_BREAK_DR3 0x100110 /* Breakpoint matches on DR3 */ 127#define MSR_P5_CESR_ES_HARDWARE_IT 0x100111 /* Hardware interrupts */ 128 129/* 130 * CR0 131 */ 132#define CR0_PG 0x80000000 /* Enable paging */ 133#define CR0_CD 0x40000000 /* i486: Cache disable */ 134#define CR0_NW 0x20000000 /* i486: No write-through */ 135#define CR0_AM 0x00040000 /* i486: Alignment check mask */ 136#define CR0_WP 0x00010000 /* i486: Write-protect kernel access */ 137#define CR0_NE 0x00000020 /* i486: Handle numeric exceptions */ 138#define CR0_ET 0x00000010 /* Extension type is 80387 */ 139 /* (not official) */ 140#define CR0_TS 0x00000008 /* Task switch */ 141#define CR0_EM 0x00000004 /* Emulate coprocessor */ 142#define CR0_MP 0x00000002 /* Monitor coprocessor */ 143#define CR0_PE 0x00000001 /* Enable protected mode */ 144 145/* 146 * CR4 147 */ 148#define CR4_SMEP 0x00100000 /* Supervisor-Mode Execute Protect */ 149#define CR4_OSXSAVE 0x00040000 /* OS supports XSAVE */ 150#define CR4_PCIDE 0x00020000 /* PCID Enable */ 151#define CR4_RDWRFSGS 0x00010000 /* RDWRFSGS Enable */ 152#define CR4_SMXE 0x00004000 /* Enable SMX operation */ 153#define CR4_VMXE 0x00002000 /* Enable VMX operation */ 154#define CR4_OSXMM 0x00000400 /* SSE/SSE2 exception support in OS */ 155#define CR4_OSFXS 0x00000200 /* SSE/SSE2 OS supports FXSave */ 156#define CR4_PCE 0x00000100 /* Performance-Monitor Count Enable */ 157#define CR4_PGE 0x00000080 /* Page Global Enable */ 158#define CR4_MCE 0x00000040 /* Machine Check Exceptions */ 159#define CR4_PAE 0x00000020 /* Physical Address Extensions */ 160#define CR4_PSE 0x00000010 /* Page Size Extensions */ 161#define CR4_DE 0x00000008 /* Debugging Extensions */ 162#define CR4_TSD 0x00000004 /* Time Stamp Disable */ 163#define CR4_PVI 0x00000002 /* Protected-mode Virtual Interrupts */ 164#define CR4_VME 0x00000001 /* Virtual-8086 Mode Extensions */ 165 166/* 167 * XCR0 - XFEATURE_ENABLED_MASK (a.k.a. XFEM) register 168 */ 169#define XCR0_YMM 0x0000000000000004ULL /* YMM state available */ 170#define XFEM_YMM XCR0_YMM 171#define XCR0_SSE 0x0000000000000002ULL /* SSE supported by XSAVE/XRESTORE */ 172#define XCR0_X87 0x0000000000000001ULL /* x87, FPU/MMX (always set) */ 173#define XFEM_SSE XCR0_SSE 174#define XFEM_X87 XCR0_X87 175#define XCR0 (0) 176 177#define PMAP_PCID_PRESERVE (1ULL << 63) 178#define PMAP_PCID_MASK (0xFFF) 179 180#define RDRAND_RAX .byte 0x48, 0x0f, 0xc7, 0xf0 181 182#ifndef ASSEMBLER 183 184#include <sys/cdefs.h> 185#include <stdint.h> 186 187__BEGIN_DECLS 188 189#define set_ts() set_cr0(get_cr0() | CR0_TS) 190 191static inline uint16_t get_es(void) 192{ 193 uint16_t es; 194 __asm__ volatile("mov %%es, %0" : "=r" (es)); 195 return es; 196} 197 198static inline void set_es(uint16_t es) 199{ 200 __asm__ volatile("mov %0, %%es" : : "r" (es)); 201} 202 203static inline uint16_t get_ds(void) 204{ 205 uint16_t ds; 206 __asm__ volatile("mov %%ds, %0" : "=r" (ds)); 207 return ds; 208} 209 210static inline void set_ds(uint16_t ds) 211{ 212 __asm__ volatile("mov %0, %%ds" : : "r" (ds)); 213} 214 215static inline uint16_t get_fs(void) 216{ 217 uint16_t fs; 218 __asm__ volatile("mov %%fs, %0" : "=r" (fs)); 219 return fs; 220} 221 222static inline void set_fs(uint16_t fs) 223{ 224 __asm__ volatile("mov %0, %%fs" : : "r" (fs)); 225} 226 227static inline uint16_t get_gs(void) 228{ 229 uint16_t gs; 230 __asm__ volatile("mov %%gs, %0" : "=r" (gs)); 231 return gs; 232} 233 234static inline void set_gs(uint16_t gs) 235{ 236 __asm__ volatile("mov %0, %%gs" : : "r" (gs)); 237} 238 239static inline uint16_t get_ss(void) 240{ 241 uint16_t ss; 242 __asm__ volatile("mov %%ss, %0" : "=r" (ss)); 243 return ss; 244} 245 246static inline void set_ss(uint16_t ss) 247{ 248 __asm__ volatile("mov %0, %%ss" : : "r" (ss)); 249} 250 251static inline uintptr_t get_cr0(void) 252{ 253 uintptr_t cr0; 254 __asm__ volatile("mov %%cr0, %0" : "=r" (cr0)); 255 return(cr0); 256} 257 258static inline void set_cr0(uintptr_t value) 259{ 260 __asm__ volatile("mov %0, %%cr0" : : "r" (value)); 261} 262 263static inline uintptr_t get_cr2(void) 264{ 265 uintptr_t cr2; 266 __asm__ volatile("mov %%cr2, %0" : "=r" (cr2)); 267 return(cr2); 268} 269 270static inline uintptr_t get_cr3_raw(void) 271{ 272 register uintptr_t cr3; 273 __asm__ volatile("mov %%cr3, %0" : "=r" (cr3)); 274 return(cr3); 275} 276 277static inline void set_cr3_raw(uintptr_t value) 278{ 279 __asm__ volatile("mov %0, %%cr3" : : "r" (value)); 280} 281 282#if defined(__i386__) 283static inline uintptr_t get_cr3(void) 284{ 285 register uintptr_t cr3; 286 __asm__ volatile("mov %%cr3, %0" : "=r" (cr3)); 287 return(cr3); 288} 289 290static inline void set_cr3(uintptr_t value) 291{ 292 __asm__ volatile("mov %0, %%cr3" : : "r" (value)); 293} 294#else 295static inline uintptr_t get_cr3_base(void) 296{ 297 register uintptr_t cr3; 298 __asm__ volatile("mov %%cr3, %0" : "=r" (cr3)); 299 return(cr3 & ~(0xFFFULL)); 300} 301 302static inline void set_cr3_composed(uintptr_t base, uint16_t pcid, uint32_t preserve) 303{ 304 __asm__ volatile("mov %0, %%cr3" : : "r" (base | pcid | ( ( (uint64_t)preserve) << 63) ) ); 305} 306 307#endif 308static inline uintptr_t get_cr4(void) 309{ 310 uintptr_t cr4; 311 __asm__ volatile("mov %%cr4, %0" : "=r" (cr4)); 312 return(cr4); 313} 314 315static inline void set_cr4(uintptr_t value) 316{ 317 __asm__ volatile("mov %0, %%cr4" : : "r" (value)); 318} 319 320static inline uintptr_t x86_get_flags(void) 321{ 322 uintptr_t erflags; 323 __asm__ volatile("pushf; pop %0" : "=r" (erflags)); 324 return erflags; 325} 326 327static inline void clear_ts(void) 328{ 329 __asm__ volatile("clts"); 330} 331 332static inline unsigned short get_tr(void) 333{ 334 unsigned short seg; 335 __asm__ volatile("str %0" : "=rm" (seg)); 336 return(seg); 337} 338 339static inline void set_tr(unsigned int seg) 340{ 341 __asm__ volatile("ltr %0" : : "rm" ((unsigned short)(seg))); 342} 343 344static inline unsigned short sldt(void) 345{ 346 unsigned short seg; 347 __asm__ volatile("sldt %0" : "=rm" (seg)); 348 return(seg); 349} 350 351static inline void lldt(unsigned int seg) 352{ 353 __asm__ volatile("lldt %0" : : "rm" ((unsigned short)(seg))); 354} 355 356static inline void lgdt(uintptr_t *desc) 357{ 358 __asm__ volatile("lgdt %0" : : "m" (*desc)); 359} 360 361static inline void lidt(uintptr_t *desc) 362{ 363 __asm__ volatile("lidt %0" : : "m" (*desc)); 364} 365 366static inline void swapgs(void) 367{ 368 __asm__ volatile("swapgs"); 369} 370 371#ifdef MACH_KERNEL_PRIVATE 372 373#ifdef __i386__ 374 375#include <i386/cpu_data.h> 376 377extern void cpuid64(uint32_t); 378extern void flush_tlb64(void); 379extern uint64_t get64_cr3(void); 380extern void set64_cr3(uint64_t); 381static inline void flush_tlb(void) 382{ 383 if (cpu_mode_is64bit()) { 384 flush_tlb64(); 385 } else { 386 set_cr3(get_cr3()); 387 } 388} 389static inline void flush_tlb_raw(void) 390{ 391 flush_tlb(); 392} 393 394#elif defined(__x86_64__) 395static inline void flush_tlb_raw(void) 396{ 397 set_cr3_raw(get_cr3_raw()); 398} 399#endif 400extern int rdmsr64_carefully(uint32_t msr, uint64_t *val); 401extern int wrmsr64_carefully(uint32_t msr, uint64_t val); 402#endif /* MACH_KERNEL_PRIVATE */ 403 404static inline void wbinvd(void) 405{ 406 __asm__ volatile("wbinvd"); 407} 408 409static inline void invlpg(uintptr_t addr) 410{ 411 __asm__ volatile("invlpg (%0)" :: "r" (addr) : "memory"); 412} 413 414/* 415 * Access to machine-specific registers (available on 586 and better only) 416 * Note: the rd* operations modify the parameters directly (without using 417 * pointer indirection), this allows gcc to optimize better 418 */ 419 420#define rdmsr(msr,lo,hi) \ 421 __asm__ volatile("rdmsr" : "=a" (lo), "=d" (hi) : "c" (msr)) 422 423#define wrmsr(msr,lo,hi) \ 424 __asm__ volatile("wrmsr" : : "c" (msr), "a" (lo), "d" (hi)) 425 426#define rdtsc(lo,hi) \ 427 __asm__ volatile("lfence; rdtsc; lfence" : "=a" (lo), "=d" (hi)) 428 429#define write_tsc(lo,hi) wrmsr(0x10, lo, hi) 430 431#define rdpmc(counter,lo,hi) \ 432 __asm__ volatile("rdpmc" : "=a" (lo), "=d" (hi) : "c" (counter)) 433 434#ifdef __i386__ 435 436static inline uint64_t rdmsr64(uint32_t msr) 437{ 438 uint64_t ret; 439 __asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr)); 440 return ret; 441} 442 443static inline void wrmsr64(uint32_t msr, uint64_t val) 444{ 445 __asm__ volatile("wrmsr" : : "c" (msr), "A" (val)); 446} 447 448static inline uint64_t rdtsc64(void) 449{ 450 uint64_t ret; 451 __asm__ volatile("lfence; rdtsc; lfence" : "=A" (ret)); 452 return ret; 453} 454 455static inline uint64_t rdtscp64(uint32_t *aux) 456{ 457 uint64_t ret; 458 __asm__ volatile("rdtscp; mov %%ecx, %1" 459 : "=A" (ret), "=m" (*aux) 460 : 461 : "ecx"); 462 return ret; 463} 464 465#elif defined(__x86_64__) 466 467static inline uint64_t rdmsr64(uint32_t msr) 468{ 469 uint32_t lo=0, hi=0; 470 rdmsr(msr, lo, hi); 471 return (((uint64_t)hi) << 32) | ((uint64_t)lo); 472} 473 474static inline void wrmsr64(uint32_t msr, uint64_t val) 475{ 476 wrmsr(msr, (val & 0xFFFFFFFFUL), ((val >> 32) & 0xFFFFFFFFUL)); 477} 478 479static inline uint64_t rdtsc64(void) 480{ 481 uint64_t lo, hi; 482 rdtsc(lo, hi); 483 return ((hi) << 32) | (lo); 484} 485 486static inline uint64_t rdtscp64(uint32_t *aux) 487{ 488 uint64_t lo, hi; 489 __asm__ volatile("rdtscp; mov %%ecx, %1" 490 : "=a" (lo), "=d" (hi), "=m" (*aux) 491 : 492 : "ecx"); 493 return ((hi) << 32) | (lo); 494} 495 496#else 497#error Unsupported architecture 498#endif 499 500/* 501 * rdmsr_carefully() returns 0 when the MSR has been read successfully, 502 * or non-zero (1) if the MSR does not exist. 503 * The implementation is in locore.s. 504 */ 505extern int rdmsr_carefully(uint32_t msr, uint32_t *lo, uint32_t *hi); 506__END_DECLS 507 508#endif /* ASSEMBLER */ 509 510#define MSR_IA32_P5_MC_ADDR 0 511#define MSR_IA32_P5_MC_TYPE 1 512#define MSR_IA32_PLATFORM_ID 0x17 513#define MSR_IA32_EBL_CR_POWERON 0x2a 514 515#define MSR_IA32_APIC_BASE 0x1b 516#define MSR_IA32_APIC_BASE_BSP (1<<8) 517#define MSR_IA32_APIC_BASE_EXTENDED (1<<10) 518#define MSR_IA32_APIC_BASE_ENABLE (1<<11) 519#define MSR_IA32_APIC_BASE_BASE (0xfffff<<12) 520 521#define MSR_CORE_THREAD_COUNT 0x35 522 523#define MSR_IA32_FEATURE_CONTROL 0x3a 524#define MSR_IA32_FEATCTL_LOCK (1<<0) 525#define MSR_IA32_FEATCTL_VMXON_SMX (1<<1) 526#define MSR_IA32_FEATCTL_VMXON (1<<2) 527#define MSR_IA32_FEATCTL_CSTATE_SMI (1<<16) 528 529#define MSR_IA32_UPDT_TRIG 0x79 530#define MSR_IA32_BIOS_SIGN_ID 0x8b 531#define MSR_IA32_UCODE_WRITE MSR_IA32_UPDT_TRIG 532#define MSR_IA32_UCODE_REV MSR_IA32_BIOS_SIGN_ID 533 534#define MSR_IA32_PERFCTR0 0xc1 535#define MSR_IA32_PERFCTR1 0xc2 536 537#define MSR_PLATFORM_INFO 0xce 538 539#define MSR_IA32_MPERF 0xE7 540#define MSR_IA32_APERF 0xE8 541 542#define MSR_IA32_BBL_CR_CTL 0x119 543 544#define MSR_IA32_SYSENTER_CS 0x174 545#define MSR_IA32_SYSENTER_ESP 0x175 546#define MSR_IA32_SYSENTER_EIP 0x176 547 548#define MSR_IA32_MCG_CAP 0x179 549#define MSR_IA32_MCG_STATUS 0x17a 550#define MSR_IA32_MCG_CTL 0x17b 551 552#define MSR_IA32_EVNTSEL0 0x186 553#define MSR_IA32_EVNTSEL1 0x187 554 555#define MSR_FLEX_RATIO 0x194 556#define MSR_IA32_PERF_STS 0x198 557#define MSR_IA32_PERF_CTL 0x199 558#define MSR_IA32_CLOCK_MODULATION 0x19a 559 560#define MSR_IA32_MISC_ENABLE 0x1a0 561 562#define MSR_IA32_PACKAGE_THERM_STATUS 0x1b1 563#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x1b2 564 565#define MSR_IA32_DEBUGCTLMSR 0x1d9 566#define MSR_IA32_LASTBRANCHFROMIP 0x1db 567#define MSR_IA32_LASTBRANCHTOIP 0x1dc 568#define MSR_IA32_LASTINTFROMIP 0x1dd 569#define MSR_IA32_LASTINTTOIP 0x1de 570 571#define MSR_IA32_CR_PAT 0x277 572 573#define MSR_IA32_MTRRCAP 0xfe 574#define MSR_IA32_MTRR_DEF_TYPE 0x2ff 575#define MSR_IA32_MTRR_PHYSBASE(n) (0x200 + 2*(n)) 576#define MSR_IA32_MTRR_PHYSMASK(n) (0x200 + 2*(n) + 1) 577#define MSR_IA32_MTRR_FIX64K_00000 0x250 578#define MSR_IA32_MTRR_FIX16K_80000 0x258 579#define MSR_IA32_MTRR_FIX16K_A0000 0x259 580#define MSR_IA32_MTRR_FIX4K_C0000 0x268 581#define MSR_IA32_MTRR_FIX4K_C8000 0x269 582#define MSR_IA32_MTRR_FIX4K_D0000 0x26a 583#define MSR_IA32_MTRR_FIX4K_D8000 0x26b 584#define MSR_IA32_MTRR_FIX4K_E0000 0x26c 585#define MSR_IA32_MTRR_FIX4K_E8000 0x26d 586#define MSR_IA32_MTRR_FIX4K_F0000 0x26e 587#define MSR_IA32_MTRR_FIX4K_F8000 0x26f 588 589#define MSR_IA32_PKG_C3_RESIDENCY 0x3F8 590#define MSR_IA32_PKG_C6_RESIDENCY 0x3F9 591#define MSR_IA32_PKG_C7_RESIDENCY 0x3FA 592 593#define MSR_IA32_CORE_C3_RESIDENCY 0x3FC 594#define MSR_IA32_CORE_C6_RESIDENCY 0x3FD 595#define MSR_IA32_CORE_C7_RESIDENCY 0x3FE 596 597#define MSR_IA32_MC0_CTL 0x400 598#define MSR_IA32_MC0_STATUS 0x401 599#define MSR_IA32_MC0_ADDR 0x402 600#define MSR_IA32_MC0_MISC 0x403 601 602#define MSR_IA32_VMX_BASE 0x480 603#define MSR_IA32_VMX_BASIC MSR_IA32_VMX_BASE 604#define MSR_IA32_VMXPINBASED_CTLS MSR_IA32_VMX_BASE+1 605#define MSR_IA32_PROCBASED_CTLS MSR_IA32_VMX_BASE+2 606#define MSR_IA32_VMX_EXIT_CTLS MSR_IA32_VMX_BASE+3 607#define MSR_IA32_VMX_ENTRY_CTLS MSR_IA32_VMX_BASE+4 608#define MSR_IA32_VMX_MISC MSR_IA32_VMX_BASE+5 609#define MSR_IA32_VMX_CR0_FIXED0 MSR_IA32_VMX_BASE+6 610#define MSR_IA32_VMX_CR0_FIXED1 MSR_IA32_VMX_BASE+7 611#define MSR_IA32_VMX_CR4_FIXED0 MSR_IA32_VMX_BASE+8 612#define MSR_IA32_VMX_CR4_FIXED1 MSR_IA32_VMX_BASE+9 613 614#define MSR_IA32_DS_AREA 0x600 615 616#define MSR_IA32_PKG_POWER_SKU_UNIT 0x606 617#define MSR_IA32_PKG_C2_RESIDENCY 0x60D 618#define MSR_IA32_PKG_ENERGY_STATUS 0x611 619 620#define MSR_IA32_DDR_ENERGY_STATUS 0x619 621#define MSR_IA32_LLC_FLUSHED_RESIDENCY_TIMER 0x61D 622#define MSR_IA32_RING_PERF_STATUS 0x621 623 624#define MSR_IA32_PKG_C8_RESIDENCY 0x630 625#define MSR_IA32_PKG_C9_RESIDENCY 0x631 626#define MSR_IA32_PKG_C10_RESIDENCY 0x632 627 628#define MSR_IA32_PP0_ENERGY_STATUS 0x639 629#define MSR_IA32_PP1_ENERGY_STATUS 0x641 630#define MSR_IA32_IA_PERF_LIMIT_REASONS 0x690 631#define MSR_IA32_GT_PERF_LIMIT_REASONS 0x6B0 632 633#define MSR_IA32_TSC_DEADLINE 0x6e0 634 635#define MSR_IA32_EFER 0xC0000080 636#define MSR_IA32_EFER_SCE 0x00000001 637#define MSR_IA32_EFER_LME 0x00000100 638#define MSR_IA32_EFER_LMA 0x00000400 639#define MSR_IA32_EFER_NXE 0x00000800 640 641#define MSR_IA32_STAR 0xC0000081 642#define MSR_IA32_LSTAR 0xC0000082 643#define MSR_IA32_CSTAR 0xC0000083 644#define MSR_IA32_FMASK 0xC0000084 645 646#define MSR_IA32_FS_BASE 0xC0000100 647#define MSR_IA32_GS_BASE 0xC0000101 648#define MSR_IA32_KERNEL_GS_BASE 0xC0000102 649#define MSR_IA32_TSC_AUX 0xC0000103 650 651#endif /* _I386_PROC_REG_H_ */ 652