1/* 2 * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved. 3 * 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. The rights granted to you under the License 10 * may not be used to create, or enable the creation or redistribution of, 11 * unlawful or unlicensed copies of an Apple operating system, or to 12 * circumvent, violate, or enable the circumvention or violation of, any 13 * terms of an Apple operating system software license agreement. 14 * 15 * Please obtain a copy of the License at 16 * http://www.opensource.apple.com/apsl/ and read it before using this file. 17 * 18 * The Original Code and all software distributed under the License are 19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 23 * Please see the License for the specific language governing rights and 24 * limitations under the License. 25 * 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 27 */ 28/* 29 * @OSF_COPYRIGHT@ 30 */ 31#include <platforms.h> 32#include <vm/vm_page.h> 33#include <pexpert/pexpert.h> 34 35#include <i386/cpuid.h> 36 37static boolean_t cpuid_dbg 38#if DEBUG 39 = TRUE; 40#else 41 = FALSE; 42#endif 43#define DBG(x...) \ 44 do { \ 45 if (cpuid_dbg) \ 46 kprintf(x); \ 47 } while (0) \ 48 49#define min(a,b) ((a) < (b) ? (a) : (b)) 50#define quad(hi,lo) (((uint64_t)(hi)) << 32 | (lo)) 51 52/* Only for 32bit values */ 53#define bit32(n) (1U << (n)) 54#define bitmask32(h,l) ((bit32(h)|(bit32(h)-1)) & ~(bit32(l)-1)) 55#define bitfield32(x,h,l) ((((x) & bitmask32(h,l)) >> l)) 56 57/* 58 * Leaf 2 cache descriptor encodings. 59 */ 60typedef enum { 61 _NULL_, /* NULL (empty) descriptor */ 62 CACHE, /* Cache */ 63 TLB, /* TLB */ 64 STLB, /* Shared second-level unified TLB */ 65 PREFETCH /* Prefetch size */ 66} cpuid_leaf2_desc_type_t; 67 68typedef enum { 69 NA, /* Not Applicable */ 70 FULLY, /* Fully-associative */ 71 TRACE, /* Trace Cache (P4 only) */ 72 INST, /* Instruction TLB */ 73 DATA, /* Data TLB */ 74 DATA0, /* Data TLB, 1st level */ 75 DATA1, /* Data TLB, 2nd level */ 76 L1, /* L1 (unified) cache */ 77 L1_INST, /* L1 Instruction cache */ 78 L1_DATA, /* L1 Data cache */ 79 L2, /* L2 (unified) cache */ 80 L3, /* L3 (unified) cache */ 81 L2_2LINESECTOR, /* L2 (unified) cache with 2 lines per sector */ 82 L3_2LINESECTOR, /* L3(unified) cache with 2 lines per sector */ 83 SMALL, /* Small page TLB */ 84 LARGE, /* Large page TLB */ 85 BOTH /* Small and Large page TLB */ 86} cpuid_leaf2_qualifier_t; 87 88typedef struct cpuid_cache_descriptor { 89 uint8_t value; /* descriptor code */ 90 uint8_t type; /* cpuid_leaf2_desc_type_t */ 91 uint8_t level; /* level of cache/TLB hierachy */ 92 uint8_t ways; /* wayness of cache */ 93 uint16_t size; /* cachesize or TLB pagesize */ 94 uint16_t entries; /* number of TLB entries or linesize */ 95} cpuid_cache_descriptor_t; 96 97/* 98 * These multipliers are used to encode 1*K .. 64*M in a 16 bit size field 99 */ 100#define K (1) 101#define M (1024) 102 103/* 104 * Intel cache descriptor table: 105 */ 106static cpuid_cache_descriptor_t intel_cpuid_leaf2_descriptor_table[] = { 107// ------------------------------------------------------- 108// value type level ways size entries 109// ------------------------------------------------------- 110 { 0x00, _NULL_, NA, NA, NA, NA }, 111 { 0x01, TLB, INST, 4, SMALL, 32 }, 112 { 0x02, TLB, INST, FULLY, LARGE, 2 }, 113 { 0x03, TLB, DATA, 4, SMALL, 64 }, 114 { 0x04, TLB, DATA, 4, LARGE, 8 }, 115 { 0x05, TLB, DATA1, 4, LARGE, 32 }, 116 { 0x06, CACHE, L1_INST, 4, 8*K, 32 }, 117 { 0x08, CACHE, L1_INST, 4, 16*K, 32 }, 118 { 0x09, CACHE, L1_INST, 4, 32*K, 64 }, 119 { 0x0A, CACHE, L1_DATA, 2, 8*K, 32 }, 120 { 0x0B, TLB, INST, 4, LARGE, 4 }, 121 { 0x0C, CACHE, L1_DATA, 4, 16*K, 32 }, 122 { 0x0D, CACHE, L1_DATA, 4, 16*K, 64 }, 123 { 0x0E, CACHE, L1_DATA, 6, 24*K, 64 }, 124 { 0x21, CACHE, L2, 8, 256*K, 64 }, 125 { 0x22, CACHE, L3_2LINESECTOR, 4, 512*K, 64 }, 126 { 0x23, CACHE, L3_2LINESECTOR, 8, 1*M, 64 }, 127 { 0x25, CACHE, L3_2LINESECTOR, 8, 2*M, 64 }, 128 { 0x29, CACHE, L3_2LINESECTOR, 8, 4*M, 64 }, 129 { 0x2C, CACHE, L1_DATA, 8, 32*K, 64 }, 130 { 0x30, CACHE, L1_INST, 8, 32*K, 64 }, 131 { 0x40, CACHE, L2, NA, 0, NA }, 132 { 0x41, CACHE, L2, 4, 128*K, 32 }, 133 { 0x42, CACHE, L2, 4, 256*K, 32 }, 134 { 0x43, CACHE, L2, 4, 512*K, 32 }, 135 { 0x44, CACHE, L2, 4, 1*M, 32 }, 136 { 0x45, CACHE, L2, 4, 2*M, 32 }, 137 { 0x46, CACHE, L3, 4, 4*M, 64 }, 138 { 0x47, CACHE, L3, 8, 8*M, 64 }, 139 { 0x48, CACHE, L2, 12, 3*M, 64 }, 140 { 0x49, CACHE, L2, 16, 4*M, 64 }, 141 { 0x4A, CACHE, L3, 12, 6*M, 64 }, 142 { 0x4B, CACHE, L3, 16, 8*M, 64 }, 143 { 0x4C, CACHE, L3, 12, 12*M, 64 }, 144 { 0x4D, CACHE, L3, 16, 16*M, 64 }, 145 { 0x4E, CACHE, L2, 24, 6*M, 64 }, 146 { 0x4F, TLB, INST, NA, SMALL, 32 }, 147 { 0x50, TLB, INST, NA, BOTH, 64 }, 148 { 0x51, TLB, INST, NA, BOTH, 128 }, 149 { 0x52, TLB, INST, NA, BOTH, 256 }, 150 { 0x55, TLB, INST, FULLY, BOTH, 7 }, 151 { 0x56, TLB, DATA0, 4, LARGE, 16 }, 152 { 0x57, TLB, DATA0, 4, SMALL, 16 }, 153 { 0x59, TLB, DATA0, FULLY, SMALL, 16 }, 154 { 0x5A, TLB, DATA0, 4, LARGE, 32 }, 155 { 0x5B, TLB, DATA, NA, BOTH, 64 }, 156 { 0x5C, TLB, DATA, NA, BOTH, 128 }, 157 { 0x5D, TLB, DATA, NA, BOTH, 256 }, 158 { 0x60, CACHE, L1, 16*K, 8, 64 }, 159 { 0x61, CACHE, L1, 4, 8*K, 64 }, 160 { 0x62, CACHE, L1, 4, 16*K, 64 }, 161 { 0x63, CACHE, L1, 4, 32*K, 64 }, 162 { 0x70, CACHE, TRACE, 8, 12*K, NA }, 163 { 0x71, CACHE, TRACE, 8, 16*K, NA }, 164 { 0x72, CACHE, TRACE, 8, 32*K, NA }, 165 { 0x76, TLB, INST, NA, BOTH, 8 }, 166 { 0x78, CACHE, L2, 4, 1*M, 64 }, 167 { 0x79, CACHE, L2_2LINESECTOR, 8, 128*K, 64 }, 168 { 0x7A, CACHE, L2_2LINESECTOR, 8, 256*K, 64 }, 169 { 0x7B, CACHE, L2_2LINESECTOR, 8, 512*K, 64 }, 170 { 0x7C, CACHE, L2_2LINESECTOR, 8, 1*M, 64 }, 171 { 0x7D, CACHE, L2, 8, 2*M, 64 }, 172 { 0x7F, CACHE, L2, 2, 512*K, 64 }, 173 { 0x80, CACHE, L2, 8, 512*K, 64 }, 174 { 0x82, CACHE, L2, 8, 256*K, 32 }, 175 { 0x83, CACHE, L2, 8, 512*K, 32 }, 176 { 0x84, CACHE, L2, 8, 1*M, 32 }, 177 { 0x85, CACHE, L2, 8, 2*M, 32 }, 178 { 0x86, CACHE, L2, 4, 512*K, 64 }, 179 { 0x87, CACHE, L2, 8, 1*M, 64 }, 180 { 0xB0, TLB, INST, 4, SMALL, 128 }, 181 { 0xB1, TLB, INST, 4, LARGE, 8 }, 182 { 0xB2, TLB, INST, 4, SMALL, 64 }, 183 { 0xB3, TLB, DATA, 4, SMALL, 128 }, 184 { 0xB4, TLB, DATA1, 4, SMALL, 256 }, 185 { 0xB5, TLB, DATA1, 8, SMALL, 64 }, 186 { 0xB6, TLB, DATA1, 8, SMALL, 128 }, 187 { 0xBA, TLB, DATA1, 4, BOTH, 64 }, 188 { 0xC1, STLB, DATA1, 8, SMALL, 1024}, 189 { 0xCA, STLB, DATA1, 4, SMALL, 512 }, 190 { 0xD0, CACHE, L3, 4, 512*K, 64 }, 191 { 0xD1, CACHE, L3, 4, 1*M, 64 }, 192 { 0xD2, CACHE, L3, 4, 2*M, 64 }, 193 { 0xD3, CACHE, L3, 4, 4*M, 64 }, 194 { 0xD4, CACHE, L3, 4, 8*M, 64 }, 195 { 0xD6, CACHE, L3, 8, 1*M, 64 }, 196 { 0xD7, CACHE, L3, 8, 2*M, 64 }, 197 { 0xD8, CACHE, L3, 8, 4*M, 64 }, 198 { 0xD9, CACHE, L3, 8, 8*M, 64 }, 199 { 0xDA, CACHE, L3, 8, 12*M, 64 }, 200 { 0xDC, CACHE, L3, 12, 1536*K, 64 }, 201 { 0xDD, CACHE, L3, 12, 3*M, 64 }, 202 { 0xDE, CACHE, L3, 12, 6*M, 64 }, 203 { 0xDF, CACHE, L3, 12, 12*M, 64 }, 204 { 0xE0, CACHE, L3, 12, 18*M, 64 }, 205 { 0xE2, CACHE, L3, 16, 2*M, 64 }, 206 { 0xE3, CACHE, L3, 16, 4*M, 64 }, 207 { 0xE4, CACHE, L3, 16, 8*M, 64 }, 208 { 0xE5, CACHE, L3, 16, 16*M, 64 }, 209 { 0xE6, CACHE, L3, 16, 24*M, 64 }, 210 { 0xF0, PREFETCH, NA, NA, 64, NA }, 211 { 0xF1, PREFETCH, NA, NA, 128, NA }, 212 { 0xFF, CACHE, NA, NA, 0, NA } 213}; 214#define INTEL_LEAF2_DESC_NUM (sizeof(intel_cpuid_leaf2_descriptor_table) / \ 215 sizeof(cpuid_cache_descriptor_t)) 216 217static inline cpuid_cache_descriptor_t * 218cpuid_leaf2_find(uint8_t value) 219{ 220 unsigned int i; 221 222 for (i = 0; i < INTEL_LEAF2_DESC_NUM; i++) 223 if (intel_cpuid_leaf2_descriptor_table[i].value == value) 224 return &intel_cpuid_leaf2_descriptor_table[i]; 225 return NULL; 226} 227 228/* 229 * CPU identification routines. 230 */ 231 232static i386_cpu_info_t *cpuid_cpu_infop = NULL; 233static i386_cpu_info_t cpuid_cpu_info; 234 235#if defined(__x86_64__) 236static void cpuid_fn(uint32_t selector, uint32_t *result) 237{ 238 do_cpuid(selector, result); 239 DBG("cpuid_fn(0x%08x) eax:0x%08x ebx:0x%08x ecx:0x%08x edx:0x%08x\n", 240 selector, result[0], result[1], result[2], result[3]); 241} 242#else 243static void cpuid_fn(uint32_t selector, uint32_t *result) 244{ 245 if (get_is64bit()) { 246 asm("call _cpuid64" 247 : "=a" (result[0]), 248 "=b" (result[1]), 249 "=c" (result[2]), 250 "=d" (result[3]) 251 : "a"(selector), 252 "b" (0), 253 "c" (0), 254 "d" (0)); 255 } else { 256 do_cpuid(selector, result); 257 } 258 DBG("cpuid_fn(0x%08x) eax:0x%08x ebx:0x%08x ecx:0x%08x edx:0x%08x\n", 259 selector, result[0], result[1], result[2], result[3]); 260} 261#endif 262 263static const char *cache_type_str[LCACHE_MAX] = { 264 "Lnone", "L1I", "L1D", "L2U", "L3U" 265}; 266 267/* this function is Intel-specific */ 268static void 269cpuid_set_cache_info( i386_cpu_info_t * info_p ) 270{ 271 uint32_t cpuid_result[4]; 272 uint32_t reg[4]; 273 uint32_t index; 274 uint32_t linesizes[LCACHE_MAX]; 275 unsigned int i; 276 unsigned int j; 277 boolean_t cpuid_deterministic_supported = FALSE; 278 279 DBG("cpuid_set_cache_info(%p)\n", info_p); 280 281 bzero( linesizes, sizeof(linesizes) ); 282 283 /* Get processor cache descriptor info using leaf 2. We don't use 284 * this internally, but must publish it for KEXTs. 285 */ 286 cpuid_fn(2, cpuid_result); 287 for (j = 0; j < 4; j++) { 288 if ((cpuid_result[j] >> 31) == 1) /* bit31 is validity */ 289 continue; 290 ((uint32_t *) info_p->cache_info)[j] = cpuid_result[j]; 291 } 292 /* first byte gives number of cpuid calls to get all descriptors */ 293 for (i = 1; i < info_p->cache_info[0]; i++) { 294 if (i*16 > sizeof(info_p->cache_info)) 295 break; 296 cpuid_fn(2, cpuid_result); 297 for (j = 0; j < 4; j++) { 298 if ((cpuid_result[j] >> 31) == 1) 299 continue; 300 ((uint32_t *) info_p->cache_info)[4*i+j] = 301 cpuid_result[j]; 302 } 303 } 304 305 /* 306 * Get cache info using leaf 4, the "deterministic cache parameters." 307 * Most processors Mac OS X supports implement this flavor of CPUID. 308 * Loop over each cache on the processor. 309 */ 310 cpuid_fn(0, cpuid_result); 311 if (cpuid_result[eax] >= 4) 312 cpuid_deterministic_supported = TRUE; 313 314 for (index = 0; cpuid_deterministic_supported; index++) { 315 cache_type_t type = Lnone; 316 uint32_t cache_type; 317 uint32_t cache_level; 318 uint32_t cache_sharing; 319 uint32_t cache_linesize; 320 uint32_t cache_sets; 321 uint32_t cache_associativity; 322 uint32_t cache_size; 323 uint32_t cache_partitions; 324 uint32_t colors; 325 326 reg[eax] = 4; /* cpuid request 4 */ 327 reg[ecx] = index; /* index starting at 0 */ 328 cpuid(reg); 329 DBG("cpuid(4) index=%d eax=0x%x\n", index, reg[eax]); 330 cache_type = bitfield32(reg[eax], 4, 0); 331 if (cache_type == 0) 332 break; /* no more caches */ 333 cache_level = bitfield32(reg[eax], 7, 5); 334 cache_sharing = bitfield32(reg[eax], 25, 14) + 1; 335 info_p->cpuid_cores_per_package 336 = bitfield32(reg[eax], 31, 26) + 1; 337 cache_linesize = bitfield32(reg[ebx], 11, 0) + 1; 338 cache_partitions = bitfield32(reg[ebx], 21, 12) + 1; 339 cache_associativity = bitfield32(reg[ebx], 31, 22) + 1; 340 cache_sets = bitfield32(reg[ecx], 31, 0) + 1; 341 342 /* Map type/levels returned by CPUID into cache_type_t */ 343 switch (cache_level) { 344 case 1: 345 type = cache_type == 1 ? L1D : 346 cache_type == 2 ? L1I : 347 Lnone; 348 break; 349 case 2: 350 type = cache_type == 3 ? L2U : 351 Lnone; 352 break; 353 case 3: 354 type = cache_type == 3 ? L3U : 355 Lnone; 356 break; 357 default: 358 type = Lnone; 359 } 360 361 /* The total size of a cache is: 362 * ( linesize * sets * associativity * partitions ) 363 */ 364 if (type != Lnone) { 365 cache_size = cache_linesize * cache_sets * 366 cache_associativity * cache_partitions; 367 info_p->cache_size[type] = cache_size; 368 info_p->cache_sharing[type] = cache_sharing; 369 info_p->cache_partitions[type] = cache_partitions; 370 linesizes[type] = cache_linesize; 371 372 DBG(" cache_size[%s] : %d\n", 373 cache_type_str[type], cache_size); 374 DBG(" cache_sharing[%s] : %d\n", 375 cache_type_str[type], cache_sharing); 376 DBG(" cache_partitions[%s]: %d\n", 377 cache_type_str[type], cache_partitions); 378 379 /* 380 * Overwrite associativity determined via 381 * CPUID.0x80000006 -- this leaf is more 382 * accurate 383 */ 384 if (type == L2U) 385 info_p->cpuid_cache_L2_associativity = cache_associativity; 386 387 /* Compute the number of page colors for this cache, 388 * which is: 389 * ( linesize * sets ) / page_size 390 * 391 * To help visualize this, consider two views of a 392 * physical address. To the cache, it is composed 393 * of a line offset, a set selector, and a tag. 394 * To VM, it is composed of a page offset, a page 395 * color, and other bits in the pageframe number: 396 * 397 * +-----------------+---------+--------+ 398 * cache: | tag | set | offset | 399 * +-----------------+---------+--------+ 400 * 401 * +-----------------+-------+----------+ 402 * VM: | don't care | color | pg offset| 403 * +-----------------+-------+----------+ 404 * 405 * The color is those bits in (set+offset) not covered 406 * by the page offset. 407 */ 408 colors = ( cache_linesize * cache_sets ) >> 12; 409 410 if ( colors > vm_cache_geometry_colors ) 411 vm_cache_geometry_colors = colors; 412 } 413 } 414 DBG(" vm_cache_geometry_colors: %d\n", vm_cache_geometry_colors); 415 416 /* 417 * If deterministic cache parameters are not available, use 418 * something else 419 */ 420 if (info_p->cpuid_cores_per_package == 0) { 421 info_p->cpuid_cores_per_package = 1; 422 423 /* cpuid define in 1024 quantities */ 424 info_p->cache_size[L2U] = info_p->cpuid_cache_size * 1024; 425 info_p->cache_sharing[L2U] = 1; 426 info_p->cache_partitions[L2U] = 1; 427 428 linesizes[L2U] = info_p->cpuid_cache_linesize; 429 430 DBG(" cache_size[L2U] : %d\n", 431 info_p->cache_size[L2U]); 432 DBG(" cache_sharing[L2U] : 1\n"); 433 DBG(" cache_partitions[L2U]: 1\n"); 434 DBG(" linesizes[L2U] : %d\n", 435 info_p->cpuid_cache_linesize); 436 } 437 438 /* 439 * What linesize to publish? We use the L2 linesize if any, 440 * else the L1D. 441 */ 442 if ( linesizes[L2U] ) 443 info_p->cache_linesize = linesizes[L2U]; 444 else if (linesizes[L1D]) 445 info_p->cache_linesize = linesizes[L1D]; 446 else panic("no linesize"); 447 DBG(" cache_linesize : %d\n", info_p->cache_linesize); 448 449 /* 450 * Extract and publish TLB information from Leaf 2 descriptors. 451 */ 452 DBG(" %ld leaf2 descriptors:\n", sizeof(info_p->cache_info)); 453 for (i = 1; i < sizeof(info_p->cache_info); i++) { 454 cpuid_cache_descriptor_t *descp; 455 int id; 456 int level; 457 int page; 458 459 DBG(" 0x%02x", info_p->cache_info[i]); 460 descp = cpuid_leaf2_find(info_p->cache_info[i]); 461 if (descp == NULL) 462 continue; 463 464 switch (descp->type) { 465 case TLB: 466 page = (descp->size == SMALL) ? TLB_SMALL : TLB_LARGE; 467 /* determine I or D: */ 468 switch (descp->level) { 469 case INST: 470 id = TLB_INST; 471 break; 472 case DATA: 473 case DATA0: 474 case DATA1: 475 id = TLB_DATA; 476 break; 477 default: 478 continue; 479 } 480 /* determine level: */ 481 switch (descp->level) { 482 case DATA1: 483 level = 1; 484 break; 485 default: 486 level = 0; 487 } 488 info_p->cpuid_tlb[id][page][level] = descp->entries; 489 break; 490 case STLB: 491 info_p->cpuid_stlb = descp->entries; 492 } 493 } 494 DBG("\n"); 495} 496 497static void 498cpuid_set_generic_info(i386_cpu_info_t *info_p) 499{ 500 uint32_t reg[4]; 501 char str[128], *p; 502 503 DBG("cpuid_set_generic_info(%p)\n", info_p); 504 505 /* do cpuid 0 to get vendor */ 506 cpuid_fn(0, reg); 507 info_p->cpuid_max_basic = reg[eax]; 508 bcopy((char *)®[ebx], &info_p->cpuid_vendor[0], 4); /* ug */ 509 bcopy((char *)®[ecx], &info_p->cpuid_vendor[8], 4); 510 bcopy((char *)®[edx], &info_p->cpuid_vendor[4], 4); 511 info_p->cpuid_vendor[12] = 0; 512 513 /* get extended cpuid results */ 514 cpuid_fn(0x80000000, reg); 515 info_p->cpuid_max_ext = reg[eax]; 516 517 /* check to see if we can get brand string */ 518 if (info_p->cpuid_max_ext >= 0x80000004) { 519 /* 520 * The brand string 48 bytes (max), guaranteed to 521 * be NUL terminated. 522 */ 523 cpuid_fn(0x80000002, reg); 524 bcopy((char *)reg, &str[0], 16); 525 cpuid_fn(0x80000003, reg); 526 bcopy((char *)reg, &str[16], 16); 527 cpuid_fn(0x80000004, reg); 528 bcopy((char *)reg, &str[32], 16); 529 for (p = str; *p != '\0'; p++) { 530 if (*p != ' ') break; 531 } 532 strlcpy(info_p->cpuid_brand_string, 533 p, sizeof(info_p->cpuid_brand_string)); 534 535 if (!strncmp(info_p->cpuid_brand_string, CPUID_STRING_UNKNOWN, 536 min(sizeof(info_p->cpuid_brand_string), 537 strlen(CPUID_STRING_UNKNOWN) + 1))) { 538 /* 539 * This string means we have a firmware-programmable brand string, 540 * and the firmware couldn't figure out what sort of CPU we have. 541 */ 542 info_p->cpuid_brand_string[0] = '\0'; 543 } 544 } 545 546 /* Get cache and addressing info. */ 547 if (info_p->cpuid_max_ext >= 0x80000006) { 548 uint32_t assoc; 549 cpuid_fn(0x80000006, reg); 550 info_p->cpuid_cache_linesize = bitfield32(reg[ecx], 7, 0); 551 assoc = bitfield32(reg[ecx],15,12); 552 /* 553 * L2 associativity is encoded, though in an insufficiently 554 * descriptive fashion, e.g. 24-way is mapped to 16-way. 555 * Represent a fully associative cache as 0xFFFF. 556 * Overwritten by associativity as determined via CPUID.4 557 * if available. 558 */ 559 if (assoc == 6) 560 assoc = 8; 561 else if (assoc == 8) 562 assoc = 16; 563 else if (assoc == 0xF) 564 assoc = 0xFFFF; 565 info_p->cpuid_cache_L2_associativity = assoc; 566 info_p->cpuid_cache_size = bitfield32(reg[ecx],31,16); 567 cpuid_fn(0x80000008, reg); 568 info_p->cpuid_address_bits_physical = 569 bitfield32(reg[eax], 7, 0); 570 info_p->cpuid_address_bits_virtual = 571 bitfield32(reg[eax],15, 8); 572 } 573 574 /* 575 * Get processor signature and decode 576 * and bracket this with the approved procedure for reading the 577 * the microcode version number a.k.a. signature a.k.a. BIOS ID 578 */ 579 wrmsr64(MSR_IA32_BIOS_SIGN_ID, 0); 580 cpuid_fn(1, reg); 581 info_p->cpuid_microcode_version = 582 (uint32_t) (rdmsr64(MSR_IA32_BIOS_SIGN_ID) >> 32); 583 info_p->cpuid_signature = reg[eax]; 584 info_p->cpuid_stepping = bitfield32(reg[eax], 3, 0); 585 info_p->cpuid_model = bitfield32(reg[eax], 7, 4); 586 info_p->cpuid_family = bitfield32(reg[eax], 11, 8); 587 info_p->cpuid_type = bitfield32(reg[eax], 13, 12); 588 info_p->cpuid_extmodel = bitfield32(reg[eax], 19, 16); 589 info_p->cpuid_extfamily = bitfield32(reg[eax], 27, 20); 590 info_p->cpuid_brand = bitfield32(reg[ebx], 7, 0); 591 info_p->cpuid_features = quad(reg[ecx], reg[edx]); 592 593 /* Get "processor flag"; necessary for microcode update matching */ 594 info_p->cpuid_processor_flag = (rdmsr64(MSR_IA32_PLATFORM_ID)>> 50) & 0x7; 595 596 /* Fold extensions into family/model */ 597 if (info_p->cpuid_family == 0x0f) 598 info_p->cpuid_family += info_p->cpuid_extfamily; 599 if (info_p->cpuid_family == 0x0f || info_p->cpuid_family == 0x06) 600 info_p->cpuid_model += (info_p->cpuid_extmodel << 4); 601 602 if (info_p->cpuid_features & CPUID_FEATURE_HTT) 603 info_p->cpuid_logical_per_package = 604 bitfield32(reg[ebx], 23, 16); 605 else 606 info_p->cpuid_logical_per_package = 1; 607 608 if (info_p->cpuid_max_ext >= 0x80000001) { 609 cpuid_fn(0x80000001, reg); 610 info_p->cpuid_extfeatures = 611 quad(reg[ecx], reg[edx]); 612 } 613 614 DBG(" max_basic : %d\n", info_p->cpuid_max_basic); 615 DBG(" max_ext : 0x%08x\n", info_p->cpuid_max_ext); 616 DBG(" vendor : %s\n", info_p->cpuid_vendor); 617 DBG(" brand_string : %s\n", info_p->cpuid_brand_string); 618 DBG(" signature : 0x%08x\n", info_p->cpuid_signature); 619 DBG(" stepping : %d\n", info_p->cpuid_stepping); 620 DBG(" model : %d\n", info_p->cpuid_model); 621 DBG(" family : %d\n", info_p->cpuid_family); 622 DBG(" type : %d\n", info_p->cpuid_type); 623 DBG(" extmodel : %d\n", info_p->cpuid_extmodel); 624 DBG(" extfamily : %d\n", info_p->cpuid_extfamily); 625 DBG(" brand : %d\n", info_p->cpuid_brand); 626 DBG(" features : 0x%016llx\n", info_p->cpuid_features); 627 DBG(" extfeatures : 0x%016llx\n", info_p->cpuid_extfeatures); 628 DBG(" logical_per_package : %d\n", info_p->cpuid_logical_per_package); 629 DBG(" microcode_version : 0x%08x\n", info_p->cpuid_microcode_version); 630 631 /* Fold in the Invariant TSC feature bit, if present */ 632 if (info_p->cpuid_max_ext >= 0x80000007) { 633 cpuid_fn(0x80000007, reg); 634 info_p->cpuid_extfeatures |= 635 reg[edx] & (uint32_t)CPUID_EXTFEATURE_TSCI; 636 DBG(" extfeatures : 0x%016llx\n", 637 info_p->cpuid_extfeatures); 638 } 639 640 if (info_p->cpuid_max_basic >= 0x5) { 641 cpuid_mwait_leaf_t *cmp = &info_p->cpuid_mwait_leaf; 642 643 /* 644 * Extract the Monitor/Mwait Leaf info: 645 */ 646 cpuid_fn(5, reg); 647 cmp->linesize_min = reg[eax]; 648 cmp->linesize_max = reg[ebx]; 649 cmp->extensions = reg[ecx]; 650 cmp->sub_Cstates = reg[edx]; 651 info_p->cpuid_mwait_leafp = cmp; 652 653 DBG(" Monitor/Mwait Leaf:\n"); 654 DBG(" linesize_min : %d\n", cmp->linesize_min); 655 DBG(" linesize_max : %d\n", cmp->linesize_max); 656 DBG(" extensions : %d\n", cmp->extensions); 657 DBG(" sub_Cstates : 0x%08x\n", cmp->sub_Cstates); 658 } 659 660 if (info_p->cpuid_max_basic >= 0x6) { 661 cpuid_thermal_leaf_t *ctp = &info_p->cpuid_thermal_leaf; 662 663 /* 664 * The thermal and Power Leaf: 665 */ 666 cpuid_fn(6, reg); 667 ctp->sensor = bitfield32(reg[eax], 0, 0); 668 ctp->dynamic_acceleration = bitfield32(reg[eax], 1, 1); 669 ctp->invariant_APIC_timer = bitfield32(reg[eax], 2, 2); 670 ctp->core_power_limits = bitfield32(reg[eax], 4, 4); 671 ctp->fine_grain_clock_mod = bitfield32(reg[eax], 5, 5); 672 ctp->package_thermal_intr = bitfield32(reg[eax], 6, 6); 673 ctp->thresholds = bitfield32(reg[ebx], 3, 0); 674 ctp->ACNT_MCNT = bitfield32(reg[ecx], 0, 0); 675 ctp->hardware_feedback = bitfield32(reg[ecx], 1, 1); 676 ctp->energy_policy = bitfield32(reg[ecx], 3, 3); 677 info_p->cpuid_thermal_leafp = ctp; 678 679 DBG(" Thermal/Power Leaf:\n"); 680 DBG(" sensor : %d\n", ctp->sensor); 681 DBG(" dynamic_acceleration : %d\n", ctp->dynamic_acceleration); 682 DBG(" invariant_APIC_timer : %d\n", ctp->invariant_APIC_timer); 683 DBG(" core_power_limits : %d\n", ctp->core_power_limits); 684 DBG(" fine_grain_clock_mod : %d\n", ctp->fine_grain_clock_mod); 685 DBG(" package_thermal_intr : %d\n", ctp->package_thermal_intr); 686 DBG(" thresholds : %d\n", ctp->thresholds); 687 DBG(" ACNT_MCNT : %d\n", ctp->ACNT_MCNT); 688 DBG(" ACNT2 : %d\n", ctp->hardware_feedback); 689 DBG(" energy_policy : %d\n", ctp->energy_policy); 690 } 691 692 if (info_p->cpuid_max_basic >= 0xa) { 693 cpuid_arch_perf_leaf_t *capp = &info_p->cpuid_arch_perf_leaf; 694 695 /* 696 * Architectural Performance Monitoring Leaf: 697 */ 698 cpuid_fn(0xa, reg); 699 capp->version = bitfield32(reg[eax], 7, 0); 700 capp->number = bitfield32(reg[eax], 15, 8); 701 capp->width = bitfield32(reg[eax], 23, 16); 702 capp->events_number = bitfield32(reg[eax], 31, 24); 703 capp->events = reg[ebx]; 704 capp->fixed_number = bitfield32(reg[edx], 4, 0); 705 capp->fixed_width = bitfield32(reg[edx], 12, 5); 706 info_p->cpuid_arch_perf_leafp = capp; 707 708 DBG(" Architectural Performance Monitoring Leaf:\n"); 709 DBG(" version : %d\n", capp->version); 710 DBG(" number : %d\n", capp->number); 711 DBG(" width : %d\n", capp->width); 712 DBG(" events_number : %d\n", capp->events_number); 713 DBG(" events : %d\n", capp->events); 714 DBG(" fixed_number : %d\n", capp->fixed_number); 715 DBG(" fixed_width : %d\n", capp->fixed_width); 716 } 717 718 if (info_p->cpuid_max_basic >= 0xd) { 719 cpuid_xsave_leaf_t *xsp = &info_p->cpuid_xsave_leaf; 720 /* 721 * XSAVE Features: 722 */ 723 cpuid_fn(0xd, info_p->cpuid_xsave_leaf.extended_state); 724 info_p->cpuid_xsave_leafp = xsp; 725 726 DBG(" XSAVE Leaf:\n"); 727 DBG(" EAX : 0x%x\n", xsp->extended_state[eax]); 728 DBG(" EBX : 0x%x\n", xsp->extended_state[ebx]); 729 DBG(" ECX : 0x%x\n", xsp->extended_state[ecx]); 730 DBG(" EDX : 0x%x\n", xsp->extended_state[edx]); 731 } 732 733 if (info_p->cpuid_model >= CPUID_MODEL_IVYBRIDGE) { 734 /* 735 * Leaf7 Features: 736 */ 737 cpuid_fn(0x7, reg); 738 info_p->cpuid_leaf7_features = reg[ebx]; 739 740 DBG(" Feature Leaf7:\n"); 741 DBG(" EBX : 0x%x\n", reg[ebx]); 742 } 743 744 return; 745} 746 747static uint32_t 748cpuid_set_cpufamily(i386_cpu_info_t *info_p) 749{ 750 uint32_t cpufamily = CPUFAMILY_UNKNOWN; 751 752 switch (info_p->cpuid_family) { 753 case 6: 754 switch (info_p->cpuid_model) { 755#if CONFIG_YONAH 756 case 14: 757 cpufamily = CPUFAMILY_INTEL_YONAH; 758 break; 759#endif 760 case 15: 761 cpufamily = CPUFAMILY_INTEL_MEROM; 762 break; 763 case 23: 764 cpufamily = CPUFAMILY_INTEL_PENRYN; 765 break; 766 case CPUID_MODEL_NEHALEM: 767 case CPUID_MODEL_FIELDS: 768 case CPUID_MODEL_DALES: 769 case CPUID_MODEL_NEHALEM_EX: 770 cpufamily = CPUFAMILY_INTEL_NEHALEM; 771 break; 772 case CPUID_MODEL_DALES_32NM: 773 case CPUID_MODEL_WESTMERE: 774 case CPUID_MODEL_WESTMERE_EX: 775 cpufamily = CPUFAMILY_INTEL_WESTMERE; 776 break; 777 case CPUID_MODEL_SANDYBRIDGE: 778 case CPUID_MODEL_JAKETOWN: 779 cpufamily = CPUFAMILY_INTEL_SANDYBRIDGE; 780 break; 781 case CPUID_MODEL_IVYBRIDGE: 782 cpufamily = CPUFAMILY_INTEL_IVYBRIDGE; 783 break; 784 case CPUID_MODEL_HASWELL: 785 case CPUID_MODEL_HASWELL_ULT: 786 case CPUID_MODEL_CRYSTALWELL: 787 cpufamily = CPUFAMILY_INTEL_HASWELL; 788 break; 789 } 790 break; 791 } 792 793 info_p->cpuid_cpufamily = cpufamily; 794 DBG("cpuid_set_cpufamily(%p) returning 0x%x\n", info_p, cpufamily); 795 return cpufamily; 796} 797/* 798 * Must be invoked either when executing single threaded, or with 799 * independent synchronization. 800 */ 801void 802cpuid_set_info(void) 803{ 804 i386_cpu_info_t *info_p = &cpuid_cpu_info; 805 806 PE_parse_boot_argn("-cpuid", &cpuid_dbg, sizeof(cpuid_dbg)); 807 808 bzero((void *)info_p, sizeof(cpuid_cpu_info)); 809 810 cpuid_set_generic_info(info_p); 811 812 /* verify we are running on a supported CPU */ 813 if ((strncmp(CPUID_VID_INTEL, info_p->cpuid_vendor, 814 min(strlen(CPUID_STRING_UNKNOWN) + 1, 815 sizeof(info_p->cpuid_vendor)))) || 816 (cpuid_set_cpufamily(info_p) == CPUFAMILY_UNKNOWN)) 817 panic("Unsupported CPU"); 818 819 info_p->cpuid_cpu_type = CPU_TYPE_X86; 820 info_p->cpuid_cpu_subtype = CPU_SUBTYPE_X86_ARCH1; 821 /* Must be invoked after set_generic_info */ 822 cpuid_set_cache_info(&cpuid_cpu_info); 823 824 /* 825 * Find the number of enabled cores and threads 826 * (which determines whether SMT/Hyperthreading is active). 827 */ 828 switch (info_p->cpuid_cpufamily) { 829 case CPUFAMILY_INTEL_WESTMERE: { 830 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT); 831 info_p->core_count = bitfield32((uint32_t)msr, 19, 16); 832 info_p->thread_count = bitfield32((uint32_t)msr, 15, 0); 833 break; 834 } 835 case CPUFAMILY_INTEL_HASWELL: 836 case CPUFAMILY_INTEL_IVYBRIDGE: 837 case CPUFAMILY_INTEL_SANDYBRIDGE: 838 case CPUFAMILY_INTEL_NEHALEM: { 839 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT); 840 info_p->core_count = bitfield32((uint32_t)msr, 31, 16); 841 info_p->thread_count = bitfield32((uint32_t)msr, 15, 0); 842 break; 843 } 844 } 845 if (info_p->core_count == 0) { 846 info_p->core_count = info_p->cpuid_cores_per_package; 847 info_p->thread_count = info_p->cpuid_logical_per_package; 848 } 849 DBG("cpuid_set_info():\n"); 850 DBG(" core_count : %d\n", info_p->core_count); 851 DBG(" thread_count : %d\n", info_p->thread_count); 852 853 cpuid_cpu_info.cpuid_model_string = ""; /* deprecated */ 854} 855 856static struct table { 857 uint64_t mask; 858 const char *name; 859} feature_map[] = { 860 {CPUID_FEATURE_FPU, "FPU"}, 861 {CPUID_FEATURE_VME, "VME"}, 862 {CPUID_FEATURE_DE, "DE"}, 863 {CPUID_FEATURE_PSE, "PSE"}, 864 {CPUID_FEATURE_TSC, "TSC"}, 865 {CPUID_FEATURE_MSR, "MSR"}, 866 {CPUID_FEATURE_PAE, "PAE"}, 867 {CPUID_FEATURE_MCE, "MCE"}, 868 {CPUID_FEATURE_CX8, "CX8"}, 869 {CPUID_FEATURE_APIC, "APIC"}, 870 {CPUID_FEATURE_SEP, "SEP"}, 871 {CPUID_FEATURE_MTRR, "MTRR"}, 872 {CPUID_FEATURE_PGE, "PGE"}, 873 {CPUID_FEATURE_MCA, "MCA"}, 874 {CPUID_FEATURE_CMOV, "CMOV"}, 875 {CPUID_FEATURE_PAT, "PAT"}, 876 {CPUID_FEATURE_PSE36, "PSE36"}, 877 {CPUID_FEATURE_PSN, "PSN"}, 878 {CPUID_FEATURE_CLFSH, "CLFSH"}, 879 {CPUID_FEATURE_DS, "DS"}, 880 {CPUID_FEATURE_ACPI, "ACPI"}, 881 {CPUID_FEATURE_MMX, "MMX"}, 882 {CPUID_FEATURE_FXSR, "FXSR"}, 883 {CPUID_FEATURE_SSE, "SSE"}, 884 {CPUID_FEATURE_SSE2, "SSE2"}, 885 {CPUID_FEATURE_SS, "SS"}, 886 {CPUID_FEATURE_HTT, "HTT"}, 887 {CPUID_FEATURE_TM, "TM"}, 888 {CPUID_FEATURE_PBE, "PBE"}, 889 {CPUID_FEATURE_SSE3, "SSE3"}, 890 {CPUID_FEATURE_PCLMULQDQ, "PCLMULQDQ"}, 891 {CPUID_FEATURE_DTES64, "DTES64"}, 892 {CPUID_FEATURE_MONITOR, "MON"}, 893 {CPUID_FEATURE_DSCPL, "DSCPL"}, 894 {CPUID_FEATURE_VMX, "VMX"}, 895 {CPUID_FEATURE_SMX, "SMX"}, 896 {CPUID_FEATURE_EST, "EST"}, 897 {CPUID_FEATURE_TM2, "TM2"}, 898 {CPUID_FEATURE_SSSE3, "SSSE3"}, 899 {CPUID_FEATURE_CID, "CID"}, 900 {CPUID_FEATURE_FMA, "FMA"}, 901 {CPUID_FEATURE_CX16, "CX16"}, 902 {CPUID_FEATURE_xTPR, "TPR"}, 903 {CPUID_FEATURE_PDCM, "PDCM"}, 904 {CPUID_FEATURE_SSE4_1, "SSE4.1"}, 905 {CPUID_FEATURE_SSE4_2, "SSE4.2"}, 906 {CPUID_FEATURE_x2APIC, "x2APIC"}, 907 {CPUID_FEATURE_MOVBE, "MOVBE"}, 908 {CPUID_FEATURE_POPCNT, "POPCNT"}, 909 {CPUID_FEATURE_AES, "AES"}, 910 {CPUID_FEATURE_VMM, "VMM"}, 911 {CPUID_FEATURE_PCID, "PCID"}, 912 {CPUID_FEATURE_XSAVE, "XSAVE"}, 913 {CPUID_FEATURE_OSXSAVE, "OSXSAVE"}, 914 {CPUID_FEATURE_SEGLIM64, "SEGLIM64"}, 915 {CPUID_FEATURE_TSCTMR, "TSCTMR"}, 916 {CPUID_FEATURE_AVX1_0, "AVX1.0"}, 917 {CPUID_FEATURE_RDRAND, "RDRAND"}, 918 {CPUID_FEATURE_F16C, "F16C"}, 919 {0, 0} 920}, 921extfeature_map[] = { 922 {CPUID_EXTFEATURE_SYSCALL, "SYSCALL"}, 923 {CPUID_EXTFEATURE_XD, "XD"}, 924 {CPUID_EXTFEATURE_1GBPAGE, "1GBPAGE"}, 925 {CPUID_EXTFEATURE_EM64T, "EM64T"}, 926 {CPUID_EXTFEATURE_LAHF, "LAHF"}, 927 {CPUID_EXTFEATURE_RDTSCP, "RDTSCP"}, 928 {CPUID_EXTFEATURE_TSCI, "TSCI"}, 929 {0, 0} 930 931}, 932leaf7_feature_map[] = { 933 {CPUID_LEAF7_FEATURE_RDWRFSGS, "RDWRFSGS"}, 934 {CPUID_LEAF7_FEATURE_TSCOFF, "TSC_THREAD_OFFSET"}, 935 {CPUID_LEAF7_FEATURE_BMI1, "BMI1"}, 936 {CPUID_LEAF7_FEATURE_HLE, "HLE"}, 937 {CPUID_LEAF7_FEATURE_SMEP, "SMEP"}, 938 {CPUID_LEAF7_FEATURE_AVX2, "AVX2"}, 939 {CPUID_LEAF7_FEATURE_BMI2, "BMI2"}, 940 {CPUID_LEAF7_FEATURE_ENFSTRG, "ENFSTRG"}, 941 {CPUID_LEAF7_FEATURE_INVPCID, "INVPCID"}, 942 {CPUID_LEAF7_FEATURE_RTM, "RTM"}, 943 {0, 0} 944}; 945 946static char * 947cpuid_get_names(struct table *map, uint64_t bits, char *buf, unsigned buf_len) 948{ 949 size_t len = 0; 950 char *p = buf; 951 int i; 952 953 for (i = 0; map[i].mask != 0; i++) { 954 if ((bits & map[i].mask) == 0) 955 continue; 956 if (len && ((size_t) (p - buf) < (buf_len - 1))) 957 *p++ = ' '; 958 len = min(strlen(map[i].name), (size_t)((buf_len-1)-(p-buf))); 959 if (len == 0) 960 break; 961 bcopy(map[i].name, p, len); 962 p += len; 963 } 964 *p = '\0'; 965 return buf; 966} 967 968i386_cpu_info_t * 969cpuid_info(void) 970{ 971 /* Set-up the cpuid_info stucture lazily */ 972 if (cpuid_cpu_infop == NULL) { 973 cpuid_set_info(); 974 cpuid_cpu_infop = &cpuid_cpu_info; 975 } 976 return cpuid_cpu_infop; 977} 978 979char * 980cpuid_get_feature_names(uint64_t features, char *buf, unsigned buf_len) 981{ 982 return cpuid_get_names(feature_map, features, buf, buf_len); 983} 984 985char * 986cpuid_get_extfeature_names(uint64_t extfeatures, char *buf, unsigned buf_len) 987{ 988 return cpuid_get_names(extfeature_map, extfeatures, buf, buf_len); 989} 990 991char * 992cpuid_get_leaf7_feature_names(uint64_t features, char *buf, unsigned buf_len) 993{ 994 return cpuid_get_names(leaf7_feature_map, features, buf, buf_len); 995} 996 997void 998cpuid_feature_display( 999 const char *header) 1000{ 1001 char buf[256]; 1002 1003 kprintf("%s: %s", header, 1004 cpuid_get_feature_names(cpuid_features(), buf, sizeof(buf))); 1005 if (cpuid_leaf7_features()) 1006 kprintf(" %s", cpuid_get_leaf7_feature_names( 1007 cpuid_leaf7_features(), buf, sizeof(buf))); 1008 kprintf("\n"); 1009 if (cpuid_features() & CPUID_FEATURE_HTT) { 1010#define s_if_plural(n) ((n > 1) ? "s" : "") 1011 kprintf(" HTT: %d core%s per package;" 1012 " %d logical cpu%s per package\n", 1013 cpuid_cpu_info.cpuid_cores_per_package, 1014 s_if_plural(cpuid_cpu_info.cpuid_cores_per_package), 1015 cpuid_cpu_info.cpuid_logical_per_package, 1016 s_if_plural(cpuid_cpu_info.cpuid_logical_per_package)); 1017 } 1018} 1019 1020void 1021cpuid_extfeature_display( 1022 const char *header) 1023{ 1024 char buf[256]; 1025 1026 kprintf("%s: %s\n", header, 1027 cpuid_get_extfeature_names(cpuid_extfeatures(), 1028 buf, sizeof(buf))); 1029} 1030 1031void 1032cpuid_cpu_display( 1033 const char *header) 1034{ 1035 if (cpuid_cpu_info.cpuid_brand_string[0] != '\0') { 1036 kprintf("%s: %s\n", header, cpuid_cpu_info.cpuid_brand_string); 1037 } 1038} 1039 1040unsigned int 1041cpuid_family(void) 1042{ 1043 return cpuid_info()->cpuid_family; 1044} 1045 1046uint32_t 1047cpuid_cpufamily(void) 1048{ 1049 return cpuid_info()->cpuid_cpufamily; 1050} 1051 1052cpu_type_t 1053cpuid_cputype(void) 1054{ 1055 return cpuid_info()->cpuid_cpu_type; 1056} 1057 1058cpu_subtype_t 1059cpuid_cpusubtype(void) 1060{ 1061 return cpuid_info()->cpuid_cpu_subtype; 1062} 1063 1064uint64_t 1065cpuid_features(void) 1066{ 1067 static int checked = 0; 1068 char fpu_arg[20] = { 0 }; 1069 1070 (void) cpuid_info(); 1071 if (!checked) { 1072 /* check for boot-time fpu limitations */ 1073 if (PE_parse_boot_argn("_fpu", &fpu_arg[0], sizeof (fpu_arg))) { 1074 printf("limiting fpu features to: %s\n", fpu_arg); 1075 if (!strncmp("387", fpu_arg, sizeof("387")) || !strncmp("mmx", fpu_arg, sizeof("mmx"))) { 1076 printf("no sse or sse2\n"); 1077 cpuid_cpu_info.cpuid_features &= ~(CPUID_FEATURE_SSE | CPUID_FEATURE_SSE2 | CPUID_FEATURE_FXSR); 1078 } else if (!strncmp("sse", fpu_arg, sizeof("sse"))) { 1079 printf("no sse2\n"); 1080 cpuid_cpu_info.cpuid_features &= ~(CPUID_FEATURE_SSE2); 1081 } 1082 } 1083 checked = 1; 1084 } 1085 return cpuid_cpu_info.cpuid_features; 1086} 1087 1088uint64_t 1089cpuid_extfeatures(void) 1090{ 1091 return cpuid_info()->cpuid_extfeatures; 1092} 1093 1094uint64_t 1095cpuid_leaf7_features(void) 1096{ 1097 return cpuid_info()->cpuid_leaf7_features; 1098} 1099 1100static i386_vmm_info_t *_cpuid_vmm_infop = NULL; 1101static i386_vmm_info_t _cpuid_vmm_info; 1102 1103static void 1104cpuid_init_vmm_info(i386_vmm_info_t *info_p) 1105{ 1106 uint32_t reg[4]; 1107 uint32_t max_vmm_leaf; 1108 1109 bzero(info_p, sizeof(*info_p)); 1110 1111 if (!cpuid_vmm_present()) 1112 return; 1113 1114 DBG("cpuid_init_vmm_info(%p)\n", info_p); 1115 1116 /* do cpuid 0x40000000 to get VMM vendor */ 1117 cpuid_fn(0x40000000, reg); 1118 max_vmm_leaf = reg[eax]; 1119 bcopy((char *)®[ebx], &info_p->cpuid_vmm_vendor[0], 4); 1120 bcopy((char *)®[ecx], &info_p->cpuid_vmm_vendor[4], 4); 1121 bcopy((char *)®[edx], &info_p->cpuid_vmm_vendor[8], 4); 1122 info_p->cpuid_vmm_vendor[12] = '\0'; 1123 1124 if (0 == strcmp(info_p->cpuid_vmm_vendor, CPUID_VMM_ID_VMWARE)) { 1125 /* VMware identification string: kb.vmware.com/kb/1009458 */ 1126 info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_VMWARE; 1127 } else { 1128 info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_UNKNOWN; 1129 } 1130 1131 /* VMM generic leaves: https://lkml.org/lkml/2008/10/1/246 */ 1132 if (max_vmm_leaf >= 0x40000010) { 1133 cpuid_fn(0x40000010, reg); 1134 1135 info_p->cpuid_vmm_tsc_frequency = reg[eax]; 1136 info_p->cpuid_vmm_bus_frequency = reg[ebx]; 1137 } 1138 1139 DBG(" vmm_vendor : %s\n", info_p->cpuid_vmm_vendor); 1140 DBG(" vmm_family : %u\n", info_p->cpuid_vmm_family); 1141 DBG(" vmm_bus_frequency : %u\n", info_p->cpuid_vmm_bus_frequency); 1142 DBG(" vmm_tsc_frequency : %u\n", info_p->cpuid_vmm_tsc_frequency); 1143} 1144 1145boolean_t 1146cpuid_vmm_present(void) 1147{ 1148 return (cpuid_features() & CPUID_FEATURE_VMM) ? TRUE : FALSE; 1149} 1150 1151i386_vmm_info_t * 1152cpuid_vmm_info(void) 1153{ 1154 if (_cpuid_vmm_infop == NULL) { 1155 cpuid_init_vmm_info(&_cpuid_vmm_info); 1156 _cpuid_vmm_infop = &_cpuid_vmm_info; 1157 } 1158 return _cpuid_vmm_infop; 1159} 1160 1161uint32_t 1162cpuid_vmm_family(void) 1163{ 1164 return cpuid_vmm_info()->cpuid_vmm_family; 1165} 1166