/broadcom-cfe-1.4.2/build/broadcom/tiny/ |
H A D | tiny_init.S | 93 # Some CSWARM boards have the SER0 enable bit when 95 # into synchronous mode. Kill off the SCD bit.
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/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125cpci/src/ |
H A D | bcm91125cpci_init.S | 106 # Some BCM91125CPCI boards have the SER0 enable bit when 108 # into synchronous mode. Kill off the SCD bit. 220 # Program the mode register for 1 stop bit, ignore CTS
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/broadcom-cfe-1.4.2/cfe/x86emu/ |
H A D | ops2.c | 304 int bit,disp; local 319 bit = *shiftreg & 0x1F; 322 CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); 331 bit = *shiftreg & 0xF; 334 CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); 346 bit = *shiftreg & 0x1F; 349 CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); 358 bit = *shiftreg & 0xF; 361 CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); 373 bit 710 int bit,disp; local 1332 int bit,disp; local 1741 int bit; local 1991 int bit,disp; local [all...] |
/broadcom-cfe-1.4.2/cfe/arch/mips/board/lausanne/src/ |
H A D | lausanne_init.S | 109 # Some CSWARM boards have the SER0 enable bit when 111 # into synchronous mode. Kill off the SCD bit. 222 # Program the mode register for 1 stop bit, ignore CTS
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/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcm1480/src/ |
H A D | bcm1480_l2cache.S | 93 * config bit for this purpose. 103 # Save the old status register, and set the KX bit. 111 # area, but leave the address bit for "Valid" zero. 114 # so we will need to use a 64-bit address to get to it. 151 # Restore old KX bit setting 195 # Save the old status register, and set the KX bit. 252 # Save the old status register, and set the KX bit. 308 # Save the old status register, and set the KX bit. 324 # disable buserrs in global config, and put a bit 357 # bit [all...] |
H A D | bcm1480_altcpu.S | 88 * and using that to index a bit array to get the number of 269 not t1 # clear this bit 281 beq t0,zero,2b # Loop till the bit is set 460 not t1 # clear this bit 472 beq t0,zero,2b # Loop till the bit is set 584 li t1,1 # make a bit mask depending on CPU 586 sd t1,0(a0) # set corresponding bit in mailbox 628 * a1 - pointer to start parameters (four 64-bit values) 775 beq t0,zero,1b # Loop till the bit is set 798 * (except the lower bit i [all...] |
H A D | bcm1480_pci_machdep.c | 210 1, /* we support 64 bit addressing and DAC */
501 /* The ResetIntr bit is always set here; clear it. */
665 #define M_BCM1480_HTD_ALL_PORTS(bit) (V_BCM1480_HTD_PORTCTRL_PORT0(bit) | \
666 V_BCM1480_HTD_PORTCTRL_PORT1(bit) | \
667 V_BCM1480_HTD_PORTCTRL_PORT2(bit))
849 unsigned freq_cap; /* bit mask of advertised frequencies */
863 /* Encode the capabilities as a bit vector (see Table 171) */
1466 pci_tagprintf(tag, "pci_map_mem: bad 64-bit reguest\n");
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/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/sb1250/src/ |
H A D | sb1250_l2cache.S | 104 # Save the old status register, and set the KX bit. 112 # area, but leave the address bit for "Valid" zero. 115 # so we will need to use a 64-bit address to get to it. 141 # Restore old KX bit setting 182 # Save the old status register, and set the KX bit. 234 # Save the old status register, and set the KX bit. 284 # Save the old status register, and set the KX bit. 392 # Restore old KX bit setting
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H A D | sb1250_altcpu.S | 218 not t1 # clear this bit 229 beq t0,zero,1b # Loop till the bit is set 494 li t1,1 # make a bit mask depending on CPU 496 sd t1,0(a0) # set corresponding bit in mailbox 538 * a1 - pointer to start parameters (four 64-bit values) 680 beq t0,zero,1b # Loop till the bit is set 697 * (except the lower bit is set just in case the reloc was 703 and t0,t1 # clear lower bit.
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/broadcom-cfe-1.4.2/cfe/hosttools/ |
H A D | mkflashimage.c | 108 unsigned int idx, bit, data, crc = 0xFFFFFFFFUL; local 111 for (data = *databuf++, bit = 0; bit < 8; bit++, data >>= 1) { 160 if (verbose) fprintf(stderr,"[Image file will be marked 64-bit]\n");
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H A D | swapflashimage.c | 83 unsigned int idx, bit, data, crc = 0xFFFFFFFFUL; local 86 for (data = *databuf++, bit = 0; bit < 8; bit++, data >>= 1) {
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/broadcom-cfe-1.4.2/cfe/ui/ |
H A D | ui_flash.c | 146 unsigned int idx, bit, data, crc = 0xFFFFFFFFUL; local 149 for (data = *databuf++, bit = 0; bit < 8; bit++, data >>= 1) {
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/broadcom-cfe-1.4.2/cfe/arch/mips/board/swarm/src/ |
H A D | swarm_init.S | 209 # Some CSWARM boards have the SER0 enable bit when 211 # into synchronous mode. Kill off the SCD bit. 346 # Program the mode register for 1 stop bit, ignore CTS
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/broadcom-cfe-1.4.2/cfe/arch/mips/common/src/ |
H A D | dev_flash_all.S | 139 bne t0,0xFF,1b # go till bit is set
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H A D | tools.mk | 54 # Check for 64-bit mode. ZipStart is always built as 32-bit, so
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H A D | disasm.c | 57 #define SEXT_32(bit, val) \ 58 ((((int32_t)(val))<<(31-(bit)))>>(31-(bit))) 59 #define SEXT_64(bit, val) \ 60 ((((int64_t)(val))<<(63-(bit)))>>(63-(bit)))
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/broadcom-cfe-1.4.2/cfe/pci/ |
H A D | pci_subr.c | 397 #define onoff(str, bit) \ 399 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); \ 515 type = "32-bit"; 518 type = "32-bit-1M"; 521 type = "64-bit"; 558 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 574 #define on(str, bit) \ 575 do { if (rval & (bit)) printf(" %s: on\n", (str)); } while (0)
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/broadcom-cfe-1.4.2/cfe/arch/ppc/common/src/ |
H A D | tools.mk | 58 # Check for 64-bit mode
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/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125pcix/src/ |
H A D | bcm91125pcix_init.S | 234 # Program the mode register for 1 stop bit, ignore CTS
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/broadcom-cfe-1.4.2/cfe/arch/mips/board/sentosa/src/ |
H A D | sentosa_init.S | 158 # Program the mode register for 1 stop bit, ignore CTS
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/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91280e/src/ |
H A D | bcm91280e_init.S | 207 # Program the mode register for 1 stop bit, ignore CTS
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/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125e/src/ |
H A D | bcm91125e_init.S | 238 # Program the mode register for 1 stop bit, ignore CTS
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/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125f/src/ |
H A D | bcm91125f_init.S | 226 # Program the mode register for 1 stop bit, ignore CTS
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/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91480b/src/ |
H A D | bcm91480b_init.S | 313 # Program the mode register for 1 stop bit, ignore CTS 489 * Two 64-bit channels with two DIMM slots/channel. 527 * 64-bit channels. Channel 1: 256 MB 541 * 64-bit channels. Channel 0: CS0 and CS4
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/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91480ht/src/ |
H A D | bcm91480ht_init.S | 239 # Program the mode register for 1 stop bit, ignore CTS 334 * Four 32 bit ECC channels 365 * MC_23CHANINTLV Valid in 32-bit channels only 366 * MC_01_23CHANINTLV Valid in 32-bit channels only 367 * MC_FULLCHANINTLV Valid in 32-bit channels only 374 * CSINTLV_8CS Valid in 64-bit channels only
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