| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/include/asm/ |
| H A D | dpmc.h | 12 /* PLL_CTL Masks */
143 R0 = [P0 + (x - PLL_CTL)];\
148 [P0 + (x - PLL_CTL)] = R0;\
151 R0 = w[P0 + (x - PLL_CTL)];\
156 w[P0 + (x - PLL_CTL)] = R0;\
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/include/asm/ |
| H A D | dpmc.h | 12 /* PLL_CTL Masks */
143 R0 = [P0 + (x - PLL_CTL)];\
148 [P0 + (x - PLL_CTL)] = R0;\
151 R0 = w[P0 + (x - PLL_CTL)];\
156 w[P0 + (x - PLL_CTL)] = R0;\
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/sound/pci/ctxfi/ |
| H A D | ct20k2reg.h | 32 #define PLL_CTL 0x1B7080 macro
|
| H A D | cthw20k2.c | 1304 hw_write_20kx(hw, PLL_CTL, pllctl);
1306 pllctl = hw_read_20kx(hw, PLL_CTL);
1315 hw_write_20kx(hw, PLL_CTL, pllctl);
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/sound/pci/ctxfi/ |
| H A D | ct20k2reg.h | 32 #define PLL_CTL 0x1B7080 macro
|
| H A D | cthw20k2.c | 1304 hw_write_20kx(hw, PLL_CTL, pllctl);
1306 pllctl = hw_read_20kx(hw, PLL_CTL);
1315 hw_write_20kx(hw, PLL_CTL, pllctl);
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-common/ |
| H A D | clocks-init.c | 76 /* We always write PLL_CTL thus avoiding Anomaly 05000242 */
77 bfin_write16(PLL_CTL, PLL_CTL_VAL);
|
| H A D | dpmc_modes.S | 20 P0.H = hi(PLL_CTL);
21 P0.L = lo(PLL_CTL);
39 P0.H = hi(PLL_CTL);
40 P0.L = lo(PLL_CTL);
98 P0.H = hi(PLL_CTL);
99 P0.L = lo(PLL_CTL);
130 P0.H = hi(PLL_CTL);
131 P0.L = lo(PLL_CTL);
159 P0.H = hi(PLL_CTL);
160 P0.L = lo(PLL_CTL);
[all...] |
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-common/ |
| H A D | clocks-init.c | 76 /* We always write PLL_CTL thus avoiding Anomaly 05000242 */
77 bfin_write16(PLL_CTL, PLL_CTL_VAL);
|
| H A D | dpmc_modes.S | 20 P0.H = hi(PLL_CTL);
21 P0.L = lo(PLL_CTL);
39 P0.H = hi(PLL_CTL);
40 P0.L = lo(PLL_CTL);
98 P0.H = hi(PLL_CTL);
99 P0.L = lo(PLL_CTL);
130 P0.H = hi(PLL_CTL);
131 P0.L = lo(PLL_CTL);
159 P0.H = hi(PLL_CTL);
160 P0.L = lo(PLL_CTL);
[all...] |
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf533/include/mach/ |
| H A D | cdefBF532.h | 19 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
700 /* Writing to PLL_CTL initiates a PLL relock sequence. */
714 bfin_write16(PLL_CTL, val);
|
| H A D | defBF532.h | 20 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ macro
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf533/include/mach/ |
| H A D | cdefBF532.h | 19 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
700 /* Writing to PLL_CTL initiates a PLL relock sequence. */
714 bfin_write16(PLL_CTL, val);
|
| H A D | defBF532.h | 20 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ macro
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf518/include/mach/ |
| H A D | cdefBF51x_base.h | 20 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
1061 /* Writing to PLL_CTL initiates a PLL relock sequence. */
1077 bfin_write16(PLL_CTL, val);
|
| H A D | defBF51x_base.h | 16 #define PLL_CTL 0xFFC00000 /* PLL Control Register */ macro
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf527/include/mach/ |
| H A D | cdefBF52x_base.h | 20 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
1113 /* Writing to PLL_CTL initiates a PLL relock sequence. */
1129 bfin_write16(PLL_CTL, val);
|
| H A D | defBF52x_base.h | 18 #define PLL_CTL 0xFFC00000 /* PLL Control Register */ macro
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf518/include/mach/ |
| H A D | cdefBF51x_base.h | 20 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
1061 /* Writing to PLL_CTL initiates a PLL relock sequence. */
1077 bfin_write16(PLL_CTL, val);
|
| H A D | defBF51x_base.h | 16 #define PLL_CTL 0xFFC00000 /* PLL Control Register */ macro
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf527/include/mach/ |
| H A D | cdefBF52x_base.h | 20 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
1113 /* Writing to PLL_CTL initiates a PLL relock sequence. */
1129 bfin_write16(PLL_CTL, val);
|
| H A D | defBF52x_base.h | 18 #define PLL_CTL 0xFFC00000 /* PLL Control Register */ macro
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf537/include/mach/ |
| H A D | defBF534.h | 17 #define PLL_CTL 0xFFC00000 /* PLL Control Register */ macro
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf561/include/mach/ |
| H A D | defBF561.h | 23 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ macro
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf537/include/mach/ |
| H A D | defBF534.h | 17 #define PLL_CTL 0xFFC00000 /* PLL Control Register */ macro
|