1/* 2 * Copyright 2004-2008 Analog Devices Inc. 3 * 4 * Licensed under the GPL-2 or later. 5 */ 6 7#include <linux/linkage.h> 8#include <asm/blackfin.h> 9#include <mach/irq.h> 10#include <asm/dpmc.h> 11 12.section .l1.text 13 14ENTRY(_sleep_mode) 15 [--SP] = ( R7:0, P5:0 ); 16 [--SP] = RETS; 17 18 call _set_sic_iwr; 19 20 P0.H = hi(PLL_CTL); 21 P0.L = lo(PLL_CTL); 22 R1 = W[P0](z); 23 BITSET (R1, 3); 24 W[P0] = R1.L; 25 26 CLI R2; 27 SSYNC; 28 IDLE; 29 STI R2; 30 31 call _test_pll_locked; 32 33 R0 = IWR_ENABLE(0); 34 R1 = IWR_DISABLE_ALL; 35 R2 = IWR_DISABLE_ALL; 36 37 call _set_sic_iwr; 38 39 P0.H = hi(PLL_CTL); 40 P0.L = lo(PLL_CTL); 41 R7 = w[p0](z); 42 BITCLR (R7, 3); 43 BITCLR (R7, 5); 44 w[p0] = R7.L; 45 IDLE; 46 call _test_pll_locked; 47 48 RETS = [SP++]; 49 ( R7:0, P5:0 ) = [SP++]; 50 RTS; 51ENDPROC(_sleep_mode) 52 53ENTRY(_hibernate_mode) 54 [--SP] = ( R7:0, P5:0 ); 55 [--SP] = RETS; 56 57 R3 = R0; 58 R0 = IWR_DISABLE_ALL; 59 R1 = IWR_DISABLE_ALL; 60 R2 = IWR_DISABLE_ALL; 61 call _set_sic_iwr; 62 call _set_dram_srfs; 63 SSYNC; 64 65 P0.H = hi(VR_CTL); 66 P0.L = lo(VR_CTL); 67 68 W[P0] = R3.L; 69 CLI R2; 70 IDLE; 71.Lforever: 72 jump .Lforever; 73ENDPROC(_hibernate_mode) 74 75ENTRY(_sleep_deeper) 76 [--SP] = ( R7:0, P5:0 ); 77 [--SP] = RETS; 78 79 CLI R4; 80 81 P3 = R0; 82 P4 = R1; 83 P5 = R2; 84 85 R0 = IWR_ENABLE(0); 86 R1 = IWR_DISABLE_ALL; 87 R2 = IWR_DISABLE_ALL; 88 89 call _set_sic_iwr; 90 call _set_dram_srfs; /* Set SDRAM Self Refresh */ 91 92 P0.H = hi(PLL_DIV); 93 P0.L = lo(PLL_DIV); 94 R6 = W[P0](z); 95 R0.L = 0xF; 96 W[P0] = R0.l; /* Set Max VCO to SCLK divider */ 97 98 P0.H = hi(PLL_CTL); 99 P0.L = lo(PLL_CTL); 100 R5 = W[P0](z); 101 R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9; 102 W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */ 103 104 SSYNC; 105 IDLE; 106 107 call _test_pll_locked; 108 109 P0.H = hi(VR_CTL); 110 P0.L = lo(VR_CTL); 111 R7 = W[P0](z); 112 R1 = 0x6; 113 R1 <<= 16; 114 R2 = 0x0404(Z); 115 R1 = R1|R2; 116 117 R2 = DEPOSIT(R7, R1); 118 W[P0] = R2; /* Set Min Core Voltage */ 119 120 SSYNC; 121 IDLE; 122 123 call _test_pll_locked; 124 125 R0 = P3; 126 R1 = P4; 127 R3 = P5; 128 call _set_sic_iwr; /* Set Awake from IDLE */ 129 130 P0.H = hi(PLL_CTL); 131 P0.L = lo(PLL_CTL); 132 R0 = W[P0](z); 133 BITSET (R0, 3); 134 W[P0] = R0.L; /* Turn CCLK OFF */ 135 SSYNC; 136 IDLE; 137 138 call _test_pll_locked; 139 140 R0 = IWR_ENABLE(0); 141 R1 = IWR_DISABLE_ALL; 142 R2 = IWR_DISABLE_ALL; 143 144 call _set_sic_iwr; /* Set Awake from IDLE PLL */ 145 146 P0.H = hi(VR_CTL); 147 P0.L = lo(VR_CTL); 148 W[P0]= R7; 149 150 SSYNC; 151 IDLE; 152 153 call _test_pll_locked; 154 155 P0.H = hi(PLL_DIV); 156 P0.L = lo(PLL_DIV); 157 W[P0]= R6; /* Restore CCLK and SCLK divider */ 158 159 P0.H = hi(PLL_CTL); 160 P0.L = lo(PLL_CTL); 161 w[p0] = R5; /* Restore VCO multiplier */ 162 IDLE; 163 call _test_pll_locked; 164 165 call _unset_dram_srfs; /* SDRAM Self Refresh Off */ 166 167 STI R4; 168 169 RETS = [SP++]; 170 ( R7:0, P5:0 ) = [SP++]; 171 RTS; 172ENDPROC(_sleep_deeper) 173 174ENTRY(_set_dram_srfs) 175 /* set the dram to self refresh mode */ 176 SSYNC; 177#if defined(EBIU_RSTCTL) /* DDR */ 178 P0.H = hi(EBIU_RSTCTL); 179 P0.L = lo(EBIU_RSTCTL); 180 R2 = [P0]; 181 BITSET(R2, 3); /* SRREQ enter self-refresh mode */ 182 [P0] = R2; 183 SSYNC; 1841: 185 R2 = [P0]; 186 CC = BITTST(R2, 4); 187 if !CC JUMP 1b; 188#else /* SDRAM */ 189 P0.L = lo(EBIU_SDGCTL); 190 P0.H = hi(EBIU_SDGCTL); 191 R2 = [P0]; 192 BITSET(R2, 24); /* SRFS enter self-refresh mode */ 193 [P0] = R2; 194 SSYNC; 195 196 P0.L = lo(EBIU_SDSTAT); 197 P0.H = hi(EBIU_SDSTAT); 1981: 199 R2 = w[P0]; 200 SSYNC; 201 cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */ 202 if !cc jump 1b; 203 204 P0.L = lo(EBIU_SDGCTL); 205 P0.H = hi(EBIU_SDGCTL); 206 R2 = [P0]; 207 BITCLR(R2, 0); /* SCTLE disable CLKOUT */ 208 [P0] = R2; 209#endif 210 RTS; 211ENDPROC(_set_dram_srfs) 212 213ENTRY(_unset_dram_srfs) 214 /* set the dram out of self refresh mode */ 215#if defined(EBIU_RSTCTL) /* DDR */ 216 P0.H = hi(EBIU_RSTCTL); 217 P0.L = lo(EBIU_RSTCTL); 218 R2 = [P0]; 219 BITCLR(R2, 3); /* clear SRREQ bit */ 220 [P0] = R2; 221#elif defined(EBIU_SDGCTL) /* SDRAM */ 222 223 P0.L = lo(EBIU_SDGCTL); /* release CLKOUT from self-refresh */ 224 P0.H = hi(EBIU_SDGCTL); 225 R2 = [P0]; 226 BITSET(R2, 0); /* SCTLE enable CLKOUT */ 227 [P0] = R2 228 SSYNC; 229 230 P0.L = lo(EBIU_SDGCTL); /* release SDRAM from self-refresh */ 231 P0.H = hi(EBIU_SDGCTL); 232 R2 = [P0]; 233 BITCLR(R2, 24); /* clear SRFS bit */ 234 [P0] = R2 235#endif 236 SSYNC; 237 RTS; 238ENDPROC(_unset_dram_srfs) 239 240ENTRY(_set_sic_iwr) 241#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \ 242 defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x) 243 P0.H = hi(SIC_IWR0); 244 P0.L = lo(SIC_IWR0); 245 P1.H = hi(SIC_IWR1); 246 P1.L = lo(SIC_IWR1); 247 [P1] = R1; 248#if defined(CONFIG_BF54x) 249 P1.H = hi(SIC_IWR2); 250 P1.L = lo(SIC_IWR2); 251 [P1] = R2; 252#endif 253#else 254 P0.H = hi(SIC_IWR); 255 P0.L = lo(SIC_IWR); 256#endif 257 [P0] = R0; 258 259 SSYNC; 260 RTS; 261ENDPROC(_set_sic_iwr) 262 263ENTRY(_test_pll_locked) 264 P0.H = hi(PLL_STAT); 265 P0.L = lo(PLL_STAT); 2661: 267 R0 = W[P0] (Z); 268 CC = BITTST(R0,5); 269 IF !CC JUMP 1b; 270 RTS; 271ENDPROC(_test_pll_locked) 272 273.section .text 274 275ENTRY(_do_hibernate) 276 [--SP] = ( R7:0, P5:0 ); 277 [--SP] = RETS; 278 /* Save System MMRs */ 279 R2 = R0; 280 P0.H = hi(PLL_CTL); 281 P0.L = lo(PLL_CTL); 282 283#ifdef SIC_IMASK0 284 PM_SYS_PUSH(SIC_IMASK0) 285#endif 286#ifdef SIC_IMASK1 287 PM_SYS_PUSH(SIC_IMASK1) 288#endif 289#ifdef SIC_IMASK2 290 PM_SYS_PUSH(SIC_IMASK2) 291#endif 292#ifdef SIC_IMASK 293 PM_SYS_PUSH(SIC_IMASK) 294#endif 295#ifdef SICA_IMASK0 296 PM_SYS_PUSH(SICA_IMASK0) 297#endif 298#ifdef SICA_IMASK1 299 PM_SYS_PUSH(SICA_IMASK1) 300#endif 301#ifdef SIC_IAR2 302 PM_SYS_PUSH(SIC_IAR0) 303 PM_SYS_PUSH(SIC_IAR1) 304 PM_SYS_PUSH(SIC_IAR2) 305#endif 306#ifdef SIC_IAR3 307 PM_SYS_PUSH(SIC_IAR3) 308#endif 309#ifdef SIC_IAR4 310 PM_SYS_PUSH(SIC_IAR4) 311 PM_SYS_PUSH(SIC_IAR5) 312 PM_SYS_PUSH(SIC_IAR6) 313#endif 314#ifdef SIC_IAR7 315 PM_SYS_PUSH(SIC_IAR7) 316#endif 317#ifdef SIC_IAR8 318 PM_SYS_PUSH(SIC_IAR8) 319 PM_SYS_PUSH(SIC_IAR9) 320 PM_SYS_PUSH(SIC_IAR10) 321 PM_SYS_PUSH(SIC_IAR11) 322#endif 323 324#ifdef SICA_IAR0 325 PM_SYS_PUSH(SICA_IAR0) 326 PM_SYS_PUSH(SICA_IAR1) 327 PM_SYS_PUSH(SICA_IAR2) 328 PM_SYS_PUSH(SICA_IAR3) 329 PM_SYS_PUSH(SICA_IAR4) 330 PM_SYS_PUSH(SICA_IAR5) 331 PM_SYS_PUSH(SICA_IAR6) 332 PM_SYS_PUSH(SICA_IAR7) 333#endif 334 335#ifdef SIC_IWR 336 PM_SYS_PUSH(SIC_IWR) 337#endif 338#ifdef SIC_IWR0 339 PM_SYS_PUSH(SIC_IWR0) 340#endif 341#ifdef SIC_IWR1 342 PM_SYS_PUSH(SIC_IWR1) 343#endif 344#ifdef SIC_IWR2 345 PM_SYS_PUSH(SIC_IWR2) 346#endif 347#ifdef SICA_IWR0 348 PM_SYS_PUSH(SICA_IWR0) 349#endif 350#ifdef SICA_IWR1 351 PM_SYS_PUSH(SICA_IWR1) 352#endif 353 354#ifdef PINT0_ASSIGN 355 PM_SYS_PUSH(PINT0_MASK_SET) 356 PM_SYS_PUSH(PINT1_MASK_SET) 357 PM_SYS_PUSH(PINT2_MASK_SET) 358 PM_SYS_PUSH(PINT3_MASK_SET) 359 PM_SYS_PUSH(PINT0_ASSIGN) 360 PM_SYS_PUSH(PINT1_ASSIGN) 361 PM_SYS_PUSH(PINT2_ASSIGN) 362 PM_SYS_PUSH(PINT3_ASSIGN) 363 PM_SYS_PUSH(PINT0_INVERT_SET) 364 PM_SYS_PUSH(PINT1_INVERT_SET) 365 PM_SYS_PUSH(PINT2_INVERT_SET) 366 PM_SYS_PUSH(PINT3_INVERT_SET) 367 PM_SYS_PUSH(PINT0_EDGE_SET) 368 PM_SYS_PUSH(PINT1_EDGE_SET) 369 PM_SYS_PUSH(PINT2_EDGE_SET) 370 PM_SYS_PUSH(PINT3_EDGE_SET) 371#endif 372 373 PM_SYS_PUSH(EBIU_AMBCTL0) 374 PM_SYS_PUSH(EBIU_AMBCTL1) 375 PM_SYS_PUSH16(EBIU_AMGCTL) 376 377#ifdef EBIU_FCTL 378 PM_SYS_PUSH(EBIU_MBSCTL) 379 PM_SYS_PUSH(EBIU_MODE) 380 PM_SYS_PUSH(EBIU_FCTL) 381#endif 382 383#ifdef PORTCIO_FER 384 PM_SYS_PUSH16(PORTCIO_DIR) 385 PM_SYS_PUSH16(PORTCIO_INEN) 386 PM_SYS_PUSH16(PORTCIO) 387 PM_SYS_PUSH16(PORTCIO_FER) 388 PM_SYS_PUSH16(PORTDIO_DIR) 389 PM_SYS_PUSH16(PORTDIO_INEN) 390 PM_SYS_PUSH16(PORTDIO) 391 PM_SYS_PUSH16(PORTDIO_FER) 392 PM_SYS_PUSH16(PORTEIO_DIR) 393 PM_SYS_PUSH16(PORTEIO_INEN) 394 PM_SYS_PUSH16(PORTEIO) 395 PM_SYS_PUSH16(PORTEIO_FER) 396#endif 397 398 PM_SYS_PUSH16(SYSCR) 399 400 /* Save Core MMRs */ 401 P0.H = hi(SRAM_BASE_ADDRESS); 402 P0.L = lo(SRAM_BASE_ADDRESS); 403 404 PM_PUSH(DMEM_CONTROL) 405 PM_PUSH(DCPLB_ADDR0) 406 PM_PUSH(DCPLB_ADDR1) 407 PM_PUSH(DCPLB_ADDR2) 408 PM_PUSH(DCPLB_ADDR3) 409 PM_PUSH(DCPLB_ADDR4) 410 PM_PUSH(DCPLB_ADDR5) 411 PM_PUSH(DCPLB_ADDR6) 412 PM_PUSH(DCPLB_ADDR7) 413 PM_PUSH(DCPLB_ADDR8) 414 PM_PUSH(DCPLB_ADDR9) 415 PM_PUSH(DCPLB_ADDR10) 416 PM_PUSH(DCPLB_ADDR11) 417 PM_PUSH(DCPLB_ADDR12) 418 PM_PUSH(DCPLB_ADDR13) 419 PM_PUSH(DCPLB_ADDR14) 420 PM_PUSH(DCPLB_ADDR15) 421 PM_PUSH(DCPLB_DATA0) 422 PM_PUSH(DCPLB_DATA1) 423 PM_PUSH(DCPLB_DATA2) 424 PM_PUSH(DCPLB_DATA3) 425 PM_PUSH(DCPLB_DATA4) 426 PM_PUSH(DCPLB_DATA5) 427 PM_PUSH(DCPLB_DATA6) 428 PM_PUSH(DCPLB_DATA7) 429 PM_PUSH(DCPLB_DATA8) 430 PM_PUSH(DCPLB_DATA9) 431 PM_PUSH(DCPLB_DATA10) 432 PM_PUSH(DCPLB_DATA11) 433 PM_PUSH(DCPLB_DATA12) 434 PM_PUSH(DCPLB_DATA13) 435 PM_PUSH(DCPLB_DATA14) 436 PM_PUSH(DCPLB_DATA15) 437 PM_PUSH(IMEM_CONTROL) 438 PM_PUSH(ICPLB_ADDR0) 439 PM_PUSH(ICPLB_ADDR1) 440 PM_PUSH(ICPLB_ADDR2) 441 PM_PUSH(ICPLB_ADDR3) 442 PM_PUSH(ICPLB_ADDR4) 443 PM_PUSH(ICPLB_ADDR5) 444 PM_PUSH(ICPLB_ADDR6) 445 PM_PUSH(ICPLB_ADDR7) 446 PM_PUSH(ICPLB_ADDR8) 447 PM_PUSH(ICPLB_ADDR9) 448 PM_PUSH(ICPLB_ADDR10) 449 PM_PUSH(ICPLB_ADDR11) 450 PM_PUSH(ICPLB_ADDR12) 451 PM_PUSH(ICPLB_ADDR13) 452 PM_PUSH(ICPLB_ADDR14) 453 PM_PUSH(ICPLB_ADDR15) 454 PM_PUSH(ICPLB_DATA0) 455 PM_PUSH(ICPLB_DATA1) 456 PM_PUSH(ICPLB_DATA2) 457 PM_PUSH(ICPLB_DATA3) 458 PM_PUSH(ICPLB_DATA4) 459 PM_PUSH(ICPLB_DATA5) 460 PM_PUSH(ICPLB_DATA6) 461 PM_PUSH(ICPLB_DATA7) 462 PM_PUSH(ICPLB_DATA8) 463 PM_PUSH(ICPLB_DATA9) 464 PM_PUSH(ICPLB_DATA10) 465 PM_PUSH(ICPLB_DATA11) 466 PM_PUSH(ICPLB_DATA12) 467 PM_PUSH(ICPLB_DATA13) 468 PM_PUSH(ICPLB_DATA14) 469 PM_PUSH(ICPLB_DATA15) 470 PM_PUSH(EVT0) 471 PM_PUSH(EVT1) 472 PM_PUSH(EVT2) 473 PM_PUSH(EVT3) 474 PM_PUSH(EVT4) 475 PM_PUSH(EVT5) 476 PM_PUSH(EVT6) 477 PM_PUSH(EVT7) 478 PM_PUSH(EVT8) 479 PM_PUSH(EVT9) 480 PM_PUSH(EVT10) 481 PM_PUSH(EVT11) 482 PM_PUSH(EVT12) 483 PM_PUSH(EVT13) 484 PM_PUSH(EVT14) 485 PM_PUSH(EVT15) 486 PM_PUSH(IMASK) 487 PM_PUSH(ILAT) 488 PM_PUSH(IPRIO) 489 PM_PUSH(TCNTL) 490 PM_PUSH(TPERIOD) 491 PM_PUSH(TSCALE) 492 PM_PUSH(TCOUNT) 493 PM_PUSH(TBUFCTL) 494 495 /* Save Core Registers */ 496 [--sp] = SYSCFG; 497 [--sp] = ( R7:0, P5:0 ); 498 [--sp] = fp; 499 [--sp] = usp; 500 501 [--sp] = i0; 502 [--sp] = i1; 503 [--sp] = i2; 504 [--sp] = i3; 505 506 [--sp] = m0; 507 [--sp] = m1; 508 [--sp] = m2; 509 [--sp] = m3; 510 511 [--sp] = l0; 512 [--sp] = l1; 513 [--sp] = l2; 514 [--sp] = l3; 515 516 [--sp] = b0; 517 [--sp] = b1; 518 [--sp] = b2; 519 [--sp] = b3; 520 [--sp] = a0.x; 521 [--sp] = a0.w; 522 [--sp] = a1.x; 523 [--sp] = a1.w; 524 525 [--sp] = LC0; 526 [--sp] = LC1; 527 [--sp] = LT0; 528 [--sp] = LT1; 529 [--sp] = LB0; 530 [--sp] = LB1; 531 532 [--sp] = ASTAT; 533 [--sp] = CYCLES; 534 [--sp] = CYCLES2; 535 536 [--sp] = RETS; 537 r0 = RETI; 538 [--sp] = r0; 539 [--sp] = RETX; 540 [--sp] = RETN; 541 [--sp] = RETE; 542 [--sp] = SEQSTAT; 543 544 /* Save Magic, return address and Stack Pointer */ 545 P0.H = 0; 546 P0.L = 0; 547 R0.H = 0xDEAD; /* Hibernate Magic */ 548 R0.L = 0xBEEF; 549 [P0++] = R0; /* Store Hibernate Magic */ 550 R0.H = .Lpm_resume_here; 551 R0.L = .Lpm_resume_here; 552 [P0++] = R0; /* Save Return Address */ 553 [P0++] = SP; /* Save Stack Pointer */ 554 P0.H = _hibernate_mode; 555 P0.L = _hibernate_mode; 556 R0 = R2; 557 call (P0); /* Goodbye */ 558 559.Lpm_resume_here: 560 561 /* Restore Core Registers */ 562 SEQSTAT = [sp++]; 563 RETE = [sp++]; 564 RETN = [sp++]; 565 RETX = [sp++]; 566 r0 = [sp++]; 567 RETI = r0; 568 RETS = [sp++]; 569 570 CYCLES2 = [sp++]; 571 CYCLES = [sp++]; 572 ASTAT = [sp++]; 573 574 LB1 = [sp++]; 575 LB0 = [sp++]; 576 LT1 = [sp++]; 577 LT0 = [sp++]; 578 LC1 = [sp++]; 579 LC0 = [sp++]; 580 581 a1.w = [sp++]; 582 a1.x = [sp++]; 583 a0.w = [sp++]; 584 a0.x = [sp++]; 585 b3 = [sp++]; 586 b2 = [sp++]; 587 b1 = [sp++]; 588 b0 = [sp++]; 589 590 l3 = [sp++]; 591 l2 = [sp++]; 592 l1 = [sp++]; 593 l0 = [sp++]; 594 595 m3 = [sp++]; 596 m2 = [sp++]; 597 m1 = [sp++]; 598 m0 = [sp++]; 599 600 i3 = [sp++]; 601 i2 = [sp++]; 602 i1 = [sp++]; 603 i0 = [sp++]; 604 605 usp = [sp++]; 606 fp = [sp++]; 607 608 ( R7 : 0, P5 : 0) = [ SP ++ ]; 609 SYSCFG = [sp++]; 610 611 /* Restore Core MMRs */ 612 613 PM_POP(TBUFCTL) 614 PM_POP(TCOUNT) 615 PM_POP(TSCALE) 616 PM_POP(TPERIOD) 617 PM_POP(TCNTL) 618 PM_POP(IPRIO) 619 PM_POP(ILAT) 620 PM_POP(IMASK) 621 PM_POP(EVT15) 622 PM_POP(EVT14) 623 PM_POP(EVT13) 624 PM_POP(EVT12) 625 PM_POP(EVT11) 626 PM_POP(EVT10) 627 PM_POP(EVT9) 628 PM_POP(EVT8) 629 PM_POP(EVT7) 630 PM_POP(EVT6) 631 PM_POP(EVT5) 632 PM_POP(EVT4) 633 PM_POP(EVT3) 634 PM_POP(EVT2) 635 PM_POP(EVT1) 636 PM_POP(EVT0) 637 PM_POP(ICPLB_DATA15) 638 PM_POP(ICPLB_DATA14) 639 PM_POP(ICPLB_DATA13) 640 PM_POP(ICPLB_DATA12) 641 PM_POP(ICPLB_DATA11) 642 PM_POP(ICPLB_DATA10) 643 PM_POP(ICPLB_DATA9) 644 PM_POP(ICPLB_DATA8) 645 PM_POP(ICPLB_DATA7) 646 PM_POP(ICPLB_DATA6) 647 PM_POP(ICPLB_DATA5) 648 PM_POP(ICPLB_DATA4) 649 PM_POP(ICPLB_DATA3) 650 PM_POP(ICPLB_DATA2) 651 PM_POP(ICPLB_DATA1) 652 PM_POP(ICPLB_DATA0) 653 PM_POP(ICPLB_ADDR15) 654 PM_POP(ICPLB_ADDR14) 655 PM_POP(ICPLB_ADDR13) 656 PM_POP(ICPLB_ADDR12) 657 PM_POP(ICPLB_ADDR11) 658 PM_POP(ICPLB_ADDR10) 659 PM_POP(ICPLB_ADDR9) 660 PM_POP(ICPLB_ADDR8) 661 PM_POP(ICPLB_ADDR7) 662 PM_POP(ICPLB_ADDR6) 663 PM_POP(ICPLB_ADDR5) 664 PM_POP(ICPLB_ADDR4) 665 PM_POP(ICPLB_ADDR3) 666 PM_POP(ICPLB_ADDR2) 667 PM_POP(ICPLB_ADDR1) 668 PM_POP(ICPLB_ADDR0) 669 PM_POP(IMEM_CONTROL) 670 PM_POP(DCPLB_DATA15) 671 PM_POP(DCPLB_DATA14) 672 PM_POP(DCPLB_DATA13) 673 PM_POP(DCPLB_DATA12) 674 PM_POP(DCPLB_DATA11) 675 PM_POP(DCPLB_DATA10) 676 PM_POP(DCPLB_DATA9) 677 PM_POP(DCPLB_DATA8) 678 PM_POP(DCPLB_DATA7) 679 PM_POP(DCPLB_DATA6) 680 PM_POP(DCPLB_DATA5) 681 PM_POP(DCPLB_DATA4) 682 PM_POP(DCPLB_DATA3) 683 PM_POP(DCPLB_DATA2) 684 PM_POP(DCPLB_DATA1) 685 PM_POP(DCPLB_DATA0) 686 PM_POP(DCPLB_ADDR15) 687 PM_POP(DCPLB_ADDR14) 688 PM_POP(DCPLB_ADDR13) 689 PM_POP(DCPLB_ADDR12) 690 PM_POP(DCPLB_ADDR11) 691 PM_POP(DCPLB_ADDR10) 692 PM_POP(DCPLB_ADDR9) 693 PM_POP(DCPLB_ADDR8) 694 PM_POP(DCPLB_ADDR7) 695 PM_POP(DCPLB_ADDR6) 696 PM_POP(DCPLB_ADDR5) 697 PM_POP(DCPLB_ADDR4) 698 PM_POP(DCPLB_ADDR3) 699 PM_POP(DCPLB_ADDR2) 700 PM_POP(DCPLB_ADDR1) 701 PM_POP(DCPLB_ADDR0) 702 PM_POP(DMEM_CONTROL) 703 704 /* Restore System MMRs */ 705 706 P0.H = hi(PLL_CTL); 707 P0.L = lo(PLL_CTL); 708 PM_SYS_POP16(SYSCR) 709 710#ifdef PORTCIO_FER 711 PM_SYS_POP16(PORTEIO_FER) 712 PM_SYS_POP16(PORTEIO) 713 PM_SYS_POP16(PORTEIO_INEN) 714 PM_SYS_POP16(PORTEIO_DIR) 715 PM_SYS_POP16(PORTDIO_FER) 716 PM_SYS_POP16(PORTDIO) 717 PM_SYS_POP16(PORTDIO_INEN) 718 PM_SYS_POP16(PORTDIO_DIR) 719 PM_SYS_POP16(PORTCIO_FER) 720 PM_SYS_POP16(PORTCIO) 721 PM_SYS_POP16(PORTCIO_INEN) 722 PM_SYS_POP16(PORTCIO_DIR) 723#endif 724 725#ifdef EBIU_FCTL 726 PM_SYS_POP(EBIU_FCTL) 727 PM_SYS_POP(EBIU_MODE) 728 PM_SYS_POP(EBIU_MBSCTL) 729#endif 730 PM_SYS_POP16(EBIU_AMGCTL) 731 PM_SYS_POP(EBIU_AMBCTL1) 732 PM_SYS_POP(EBIU_AMBCTL0) 733 734#ifdef PINT0_ASSIGN 735 PM_SYS_POP(PINT3_EDGE_SET) 736 PM_SYS_POP(PINT2_EDGE_SET) 737 PM_SYS_POP(PINT1_EDGE_SET) 738 PM_SYS_POP(PINT0_EDGE_SET) 739 PM_SYS_POP(PINT3_INVERT_SET) 740 PM_SYS_POP(PINT2_INVERT_SET) 741 PM_SYS_POP(PINT1_INVERT_SET) 742 PM_SYS_POP(PINT0_INVERT_SET) 743 PM_SYS_POP(PINT3_ASSIGN) 744 PM_SYS_POP(PINT2_ASSIGN) 745 PM_SYS_POP(PINT1_ASSIGN) 746 PM_SYS_POP(PINT0_ASSIGN) 747 PM_SYS_POP(PINT3_MASK_SET) 748 PM_SYS_POP(PINT2_MASK_SET) 749 PM_SYS_POP(PINT1_MASK_SET) 750 PM_SYS_POP(PINT0_MASK_SET) 751#endif 752 753#ifdef SICA_IWR1 754 PM_SYS_POP(SICA_IWR1) 755#endif 756#ifdef SICA_IWR0 757 PM_SYS_POP(SICA_IWR0) 758#endif 759#ifdef SIC_IWR2 760 PM_SYS_POP(SIC_IWR2) 761#endif 762#ifdef SIC_IWR1 763 PM_SYS_POP(SIC_IWR1) 764#endif 765#ifdef SIC_IWR0 766 PM_SYS_POP(SIC_IWR0) 767#endif 768#ifdef SIC_IWR 769 PM_SYS_POP(SIC_IWR) 770#endif 771 772#ifdef SICA_IAR0 773 PM_SYS_POP(SICA_IAR7) 774 PM_SYS_POP(SICA_IAR6) 775 PM_SYS_POP(SICA_IAR5) 776 PM_SYS_POP(SICA_IAR4) 777 PM_SYS_POP(SICA_IAR3) 778 PM_SYS_POP(SICA_IAR2) 779 PM_SYS_POP(SICA_IAR1) 780 PM_SYS_POP(SICA_IAR0) 781#endif 782 783#ifdef SIC_IAR8 784 PM_SYS_POP(SIC_IAR11) 785 PM_SYS_POP(SIC_IAR10) 786 PM_SYS_POP(SIC_IAR9) 787 PM_SYS_POP(SIC_IAR8) 788#endif 789#ifdef SIC_IAR7 790 PM_SYS_POP(SIC_IAR7) 791#endif 792#ifdef SIC_IAR6 793 PM_SYS_POP(SIC_IAR6) 794 PM_SYS_POP(SIC_IAR5) 795 PM_SYS_POP(SIC_IAR4) 796#endif 797#ifdef SIC_IAR3 798 PM_SYS_POP(SIC_IAR3) 799#endif 800#ifdef SIC_IAR2 801 PM_SYS_POP(SIC_IAR2) 802 PM_SYS_POP(SIC_IAR1) 803 PM_SYS_POP(SIC_IAR0) 804#endif 805#ifdef SICA_IMASK1 806 PM_SYS_POP(SICA_IMASK1) 807#endif 808#ifdef SICA_IMASK0 809 PM_SYS_POP(SICA_IMASK0) 810#endif 811#ifdef SIC_IMASK 812 PM_SYS_POP(SIC_IMASK) 813#endif 814#ifdef SIC_IMASK2 815 PM_SYS_POP(SIC_IMASK2) 816#endif 817#ifdef SIC_IMASK1 818 PM_SYS_POP(SIC_IMASK1) 819#endif 820#ifdef SIC_IMASK0 821 PM_SYS_POP(SIC_IMASK0) 822#endif 823 824 [--sp] = RETI; /* Clear Global Interrupt Disable */ 825 SP += 4; 826 827 RETS = [SP++]; 828 ( R7:0, P5:0 ) = [SP++]; 829 RTS; 830ENDPROC(_do_hibernate) 831