1/* 2 * Miscellaneous IOCTL commands for Dynamic Power Management Controller Driver 3 * 4 * Copyright (C) 2004-2009 Analog Device Inc. 5 * 6 * Licensed under the GPL-2 7 */ 8 9#ifndef _BLACKFIN_DPMC_H_ 10#define _BLACKFIN_DPMC_H_ 11 12/* PLL_CTL Masks */ 13#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ 14#define PLL_OFF 0x0002 /* PLL Not Powered */ 15#define STOPCK 0x0008 /* Core Clock Off */ 16#define PDWN 0x0020 /* Enter Deep Sleep Mode */ 17#ifdef __ADSPBF539__ 18# define IN_DELAY 0x0014 /* Add 200ps Delay To EBIU Input Latches */ 19# define OUT_DELAY 0x00C0 /* Add 200ps Delay To EBIU Output Signals */ 20#else 21# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ 22# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ 23#endif 24#define BYPASS 0x0100 /* Bypass the PLL */ 25#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ 26#define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */ 27#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ 28 29/* PLL_DIV Masks */ 30#define SSEL 0x000F /* System Select */ 31#define CSEL 0x0030 /* Core Select */ 32#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ 33#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ 34#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ 35#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ 36 37#define CCLK_DIV1 CSEL_DIV1 38#define CCLK_DIV2 CSEL_DIV2 39#define CCLK_DIV4 CSEL_DIV4 40#define CCLK_DIV8 CSEL_DIV8 41 42#define SET_SSEL(x) ((x) & 0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ 43#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ 44 45/* PLL_STAT Masks */ 46#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ 47#define FULL_ON 0x0002 /* Processor In Full On Mode */ 48#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ 49#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ 50 51#define RTCWS 0x0400 /* RTC/Reset Wake-Up Status */ 52#define CANWS 0x0800 /* CAN Wake-Up Status */ 53#define USBWS 0x2000 /* USB Wake-Up Status */ 54#define KPADWS 0x4000 /* Keypad Wake-Up Status */ 55#define ROTWS 0x8000 /* Rotary Wake-Up Status */ 56#define GPWS 0x1000 /* General-Purpose Wake-Up Status */ 57 58/* VR_CTL Masks */ 59#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__) 60#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */ 61#define FREQ_1000 0x3000 /* Switching Frequency Is 1 MHz */ 62#else 63#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ 64#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ 65#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ 66#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ 67#endif 68#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ 69 70#define GAIN 0x000C /* Voltage Level Gain */ 71#define GAIN_5 0x0000 /* GAIN = 5 */ 72#define GAIN_10 0x0004 /* GAIN = 1 */ 73#define GAIN_20 0x0008 /* GAIN = 2 */ 74#define GAIN_50 0x000C /* GAIN = 5 */ 75 76#define VLEV 0x00F0 /* Internal Voltage Level */ 77#ifdef __ADSPBF52x__ 78#define VLEV_085 0x0040 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ 79#define VLEV_090 0x0050 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ 80#define VLEV_095 0x0060 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ 81#define VLEV_100 0x0070 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ 82#define VLEV_105 0x0080 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ 83#define VLEV_110 0x0090 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ 84#define VLEV_115 0x00A0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ 85#define VLEV_120 0x00B0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ 86#else 87#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ 88#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ 89#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ 90#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ 91#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ 92#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ 93#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ 94#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ 95#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ 96#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ 97#endif 98 99#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ 100#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ 101#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ 102#define GPWE 0x0400 /* General-Purpose Wake-Up Enable */ 103#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */ 104#define KPADWE 0x1000 /* Keypad Wake-Up Enable */ 105#define ROTWE 0x2000 /* Rotary Wake-Up Enable */ 106#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ 107#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ 108 109#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__) 110#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */ 111#else 112#define USBWE 0x0800 /* Enable USB Wakeup From Hibernate */ 113#endif 114 115#ifndef __ASSEMBLY__ 116 117void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); 118void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); 119void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); 120void do_hibernate(int wakeup); 121void set_dram_srfs(void); 122void unset_dram_srfs(void); 123 124#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16)) 125 126struct bfin_dpmc_platform_data { 127 const unsigned int *tuple_tab; 128 unsigned short tabsize; 129 unsigned short vr_settling_time; /* in us */ 130}; 131 132#else 133 134#define PM_PUSH(x) \ 135 R0 = [P0 + (x - SRAM_BASE_ADDRESS)];\ 136 [--SP] = R0;\ 137 138#define PM_POP(x) \ 139 R0 = [SP++];\ 140 [P0 + (x - SRAM_BASE_ADDRESS)] = R0;\ 141 142#define PM_SYS_PUSH(x) \ 143 R0 = [P0 + (x - PLL_CTL)];\ 144 [--SP] = R0;\ 145 146#define PM_SYS_POP(x) \ 147 R0 = [SP++];\ 148 [P0 + (x - PLL_CTL)] = R0;\ 149 150#define PM_SYS_PUSH16(x) \ 151 R0 = w[P0 + (x - PLL_CTL)];\ 152 [--SP] = R0;\ 153 154#define PM_SYS_POP16(x) \ 155 R0 = [SP++];\ 156 w[P0 + (x - PLL_CTL)] = R0;\ 157 158#endif 159 160#endif /*_BLACKFIN_DPMC_H_*/ 161