/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/video/omap2/dss/ |
H A D | dsi.c | 107 dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end)) 1023 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */ 1024 l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */ 1025 l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */ 1026 l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0, 1028 l = FLD_MOD(l, cinfo->regm4 > 0 ? cinfo->regm4 - 1 : 0, 1045 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */ 1046 l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1, 1048 l = FLD_MOD(l, cinfo->highfreq, 1050 l = FLD_MOD( [all...] |
H A D | dss.c | 59 dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) 132 l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ 133 l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ 134 l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ 138 l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ 139 l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ 140 l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */
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H A D | rfbi.c | 68 rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end)) 325 l = FLD_MOD(l, 1, 0, 0); /* enable */ 327 l = FLD_MOD(l, 1, 4, 4); /* ITE */ 809 l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */ 810 l = FLD_MOD(l, 0, 1, 1); /* clear bypass */
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H A D | dispc.c | 146 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end)) 894 val = FLD_MOD(val, channel, shift, shift); 920 val = FLD_MOD(val, burst_size, shift+1, shift); 933 val = FLD_MOD(val, enable, 9, 9); 2100 l = FLD_MOD(l, stallmode, 11, 11); 2101 l = FLD_MOD(l, gpout0, 15, 15); 2102 l = FLD_MOD(l, gpout1, 16, 16); 3069 l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */ 3070 l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */ 3071 l = FLD_MOD( [all...] |
H A D | dss.h | 97 #define FLD_MOD(orig, val, start, end) \ macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/video/omap2/dss/ |
H A D | dsi.c | 107 dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end)) 1023 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */ 1024 l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */ 1025 l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */ 1026 l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0, 1028 l = FLD_MOD(l, cinfo->regm4 > 0 ? cinfo->regm4 - 1 : 0, 1045 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */ 1046 l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1, 1048 l = FLD_MOD(l, cinfo->highfreq, 1050 l = FLD_MOD( [all...] |
H A D | dss.c | 59 dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) 132 l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ 133 l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ 134 l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ 138 l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ 139 l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ 140 l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */
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H A D | rfbi.c | 68 rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end)) 325 l = FLD_MOD(l, 1, 0, 0); /* enable */ 327 l = FLD_MOD(l, 1, 4, 4); /* ITE */ 809 l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */ 810 l = FLD_MOD(l, 0, 1, 1); /* clear bypass */
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H A D | dispc.c | 146 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end)) 894 val = FLD_MOD(val, channel, shift, shift); 920 val = FLD_MOD(val, burst_size, shift+1, shift); 933 val = FLD_MOD(val, enable, 9, 9); 2100 l = FLD_MOD(l, stallmode, 11, 11); 2101 l = FLD_MOD(l, gpout0, 15, 15); 2102 l = FLD_MOD(l, gpout1, 16, 16); 3069 l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */ 3070 l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */ 3071 l = FLD_MOD( [all...] |
H A D | dss.h | 97 #define FLD_MOD(orig, val, start, end) \ macro
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