1/* 2 * linux/drivers/video/omap2/dss/dss.h 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 6 * 7 * Some code and ideas taken from drivers/video/omap/ driver 8 * by Imre Deak. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published by 12 * the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23#ifndef __OMAP2_DSS_H 24#define __OMAP2_DSS_H 25 26#ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT 27#define DEBUG 28#endif 29 30#ifdef DEBUG 31extern unsigned int dss_debug; 32#ifdef DSS_SUBSYS_NAME 33#define DSSDBG(format, ...) \ 34 if (dss_debug) \ 35 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \ 36 ## __VA_ARGS__) 37#else 38#define DSSDBG(format, ...) \ 39 if (dss_debug) \ 40 printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__) 41#endif 42 43#ifdef DSS_SUBSYS_NAME 44#define DSSDBGF(format, ...) \ 45 if (dss_debug) \ 46 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \ 47 ": %s(" format ")\n", \ 48 __func__, \ 49 ## __VA_ARGS__) 50#else 51#define DSSDBGF(format, ...) \ 52 if (dss_debug) \ 53 printk(KERN_DEBUG "omapdss: " \ 54 ": %s(" format ")\n", \ 55 __func__, \ 56 ## __VA_ARGS__) 57#endif 58 59#else /* DEBUG */ 60#define DSSDBG(format, ...) 61#define DSSDBGF(format, ...) 62#endif 63 64 65#ifdef DSS_SUBSYS_NAME 66#define DSSERR(format, ...) \ 67 printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \ 68 ## __VA_ARGS__) 69#else 70#define DSSERR(format, ...) \ 71 printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__) 72#endif 73 74#ifdef DSS_SUBSYS_NAME 75#define DSSINFO(format, ...) \ 76 printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \ 77 ## __VA_ARGS__) 78#else 79#define DSSINFO(format, ...) \ 80 printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__) 81#endif 82 83#ifdef DSS_SUBSYS_NAME 84#define DSSWARN(format, ...) \ 85 printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \ 86 ## __VA_ARGS__) 87#else 88#define DSSWARN(format, ...) \ 89 printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__) 90#endif 91 92/* OMAP TRM gives bitfields as start:end, where start is the higher bit 93 number. For example 7:0 */ 94#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) 95#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) 96#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end)) 97#define FLD_MOD(orig, val, start, end) \ 98 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) 99 100#define DISPC_MAX_FCK 173000000 101 102enum omap_burst_size { 103 OMAP_DSS_BURST_4x32 = 0, 104 OMAP_DSS_BURST_8x32 = 1, 105 OMAP_DSS_BURST_16x32 = 2, 106}; 107 108enum omap_parallel_interface_mode { 109 OMAP_DSS_PARALLELMODE_BYPASS, /* MIPI DPI */ 110 OMAP_DSS_PARALLELMODE_RFBI, /* MIPI DBI */ 111 OMAP_DSS_PARALLELMODE_DSI, 112}; 113 114enum dss_clock { 115 DSS_CLK_ICK = 1 << 0, 116 DSS_CLK_FCK1 = 1 << 1, 117 DSS_CLK_FCK2 = 1 << 2, 118 DSS_CLK_54M = 1 << 3, 119 DSS_CLK_96M = 1 << 4, 120}; 121 122enum dss_clk_source { 123 DSS_SRC_DSI1_PLL_FCLK, 124 DSS_SRC_DSI2_PLL_FCLK, 125 DSS_SRC_DSS1_ALWON_FCLK, 126}; 127 128struct dss_clock_info { 129 /* rates that we get with dividers below */ 130 unsigned long fck; 131 132 /* dividers */ 133 u16 fck_div; 134}; 135 136struct dispc_clock_info { 137 /* rates that we get with dividers below */ 138 unsigned long lck; 139 unsigned long pck; 140 141 /* dividers */ 142 u16 lck_div; 143 u16 pck_div; 144}; 145 146struct dsi_clock_info { 147 /* rates that we get with dividers below */ 148 unsigned long fint; 149 unsigned long clkin4ddr; 150 unsigned long clkin; 151 unsigned long dsi1_pll_fclk; 152 unsigned long dsi2_pll_fclk; 153 154 unsigned long lp_clk; 155 156 /* dividers */ 157 u16 regn; 158 u16 regm; 159 u16 regm3; 160 u16 regm4; 161 162 u16 lp_clk_div; 163 164 u8 highfreq; 165 bool use_dss2_fck; 166}; 167 168struct seq_file; 169struct platform_device; 170 171/* core */ 172void dss_clk_enable(enum dss_clock clks); 173void dss_clk_disable(enum dss_clock clks); 174unsigned long dss_clk_get_rate(enum dss_clock clk); 175int dss_need_ctx_restore(void); 176void dss_dump_clocks(struct seq_file *s); 177struct bus_type *dss_get_bus(void); 178struct regulator *dss_get_vdds_dsi(void); 179struct regulator *dss_get_vdds_sdi(void); 180struct regulator *dss_get_vdda_dac(void); 181 182/* display */ 183int dss_suspend_all_devices(void); 184int dss_resume_all_devices(void); 185void dss_disable_all_devices(void); 186 187void dss_init_device(struct platform_device *pdev, 188 struct omap_dss_device *dssdev); 189void dss_uninit_device(struct platform_device *pdev, 190 struct omap_dss_device *dssdev); 191bool dss_use_replication(struct omap_dss_device *dssdev, 192 enum omap_color_mode mode); 193void default_get_overlay_fifo_thresholds(enum omap_plane plane, 194 u32 fifo_size, enum omap_burst_size *burst_size, 195 u32 *fifo_low, u32 *fifo_high); 196 197/* manager */ 198int dss_init_overlay_managers(struct platform_device *pdev); 199void dss_uninit_overlay_managers(struct platform_device *pdev); 200int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl); 201void dss_setup_partial_planes(struct omap_dss_device *dssdev, 202 u16 *x, u16 *y, u16 *w, u16 *h, 203 bool enlarge_update_area); 204void dss_start_update(struct omap_dss_device *dssdev); 205 206/* overlay */ 207void dss_init_overlays(struct platform_device *pdev); 208void dss_uninit_overlays(struct platform_device *pdev); 209int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev); 210void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr); 211#ifdef L4_EXAMPLE 212void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr); 213#endif 214void dss_recheck_connections(struct omap_dss_device *dssdev, bool force); 215 216/* DSS */ 217int dss_init(bool skip_init); 218void dss_exit(void); 219 220void dss_save_context(void); 221void dss_restore_context(void); 222 223void dss_dump_regs(struct seq_file *s); 224 225void dss_sdi_init(u8 datapairs); 226int dss_sdi_enable(void); 227void dss_sdi_disable(void); 228 229void dss_select_dispc_clk_source(enum dss_clk_source clk_src); 230void dss_select_dsi_clk_source(enum dss_clk_source clk_src); 231enum dss_clk_source dss_get_dispc_clk_source(void); 232enum dss_clk_source dss_get_dsi_clk_source(void); 233 234void dss_set_venc_output(enum omap_dss_venc_type type); 235void dss_set_dac_pwrdn_bgz(bool enable); 236 237unsigned long dss_get_dpll4_rate(void); 238int dss_calc_clock_rates(struct dss_clock_info *cinfo); 239int dss_set_clock_div(struct dss_clock_info *cinfo); 240int dss_get_clock_div(struct dss_clock_info *cinfo); 241int dss_calc_clock_div(bool is_tft, unsigned long req_pck, 242 struct dss_clock_info *dss_cinfo, 243 struct dispc_clock_info *dispc_cinfo); 244 245/* SDI */ 246#ifdef CONFIG_OMAP2_DSS_SDI 247int sdi_init(bool skip_init); 248void sdi_exit(void); 249int sdi_init_display(struct omap_dss_device *display); 250#else 251static inline int sdi_init(bool skip_init) 252{ 253 return 0; 254} 255static inline void sdi_exit(void) 256{ 257} 258#endif 259 260/* DSI */ 261#ifdef CONFIG_OMAP2_DSS_DSI 262int dsi_init(struct platform_device *pdev); 263void dsi_exit(void); 264 265void dsi_dump_clocks(struct seq_file *s); 266void dsi_dump_irqs(struct seq_file *s); 267void dsi_dump_regs(struct seq_file *s); 268 269void dsi_save_context(void); 270void dsi_restore_context(void); 271 272int dsi_init_display(struct omap_dss_device *display); 273void dsi_irq_handler(void); 274unsigned long dsi_get_dsi1_pll_rate(void); 275int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo); 276int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck, 277 struct dsi_clock_info *cinfo, 278 struct dispc_clock_info *dispc_cinfo); 279int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk, 280 bool enable_hsdiv); 281void dsi_pll_uninit(void); 282void dsi_get_overlay_fifo_thresholds(enum omap_plane plane, 283 u32 fifo_size, enum omap_burst_size *burst_size, 284 u32 *fifo_low, u32 *fifo_high); 285void dsi_wait_dsi1_pll_active(void); 286void dsi_wait_dsi2_pll_active(void); 287#else 288static inline int dsi_init(struct platform_device *pdev) 289{ 290 return 0; 291} 292static inline void dsi_exit(void) 293{ 294} 295static inline void dsi_wait_dsi1_pll_active(void) 296{ 297} 298static inline void dsi_wait_dsi2_pll_active(void) 299{ 300} 301#endif 302 303/* DPI */ 304#ifdef CONFIG_OMAP2_DSS_DPI 305int dpi_init(struct platform_device *pdev); 306void dpi_exit(void); 307int dpi_init_display(struct omap_dss_device *dssdev); 308#else 309static inline int dpi_init(struct platform_device *pdev) 310{ 311 return 0; 312} 313static inline void dpi_exit(void) 314{ 315} 316#endif 317 318/* DISPC */ 319int dispc_init(void); 320void dispc_exit(void); 321void dispc_dump_clocks(struct seq_file *s); 322void dispc_dump_irqs(struct seq_file *s); 323void dispc_dump_regs(struct seq_file *s); 324void dispc_irq_handler(void); 325void dispc_fake_vsync_irq(void); 326 327void dispc_save_context(void); 328void dispc_restore_context(void); 329 330void dispc_enable_sidle(void); 331void dispc_disable_sidle(void); 332 333void dispc_lcd_enable_signal_polarity(bool act_high); 334void dispc_lcd_enable_signal(bool enable); 335void dispc_pck_free_enable(bool enable); 336void dispc_enable_fifohandcheck(bool enable); 337 338void dispc_set_lcd_size(u16 width, u16 height); 339void dispc_set_digit_size(u16 width, u16 height); 340u32 dispc_get_plane_fifo_size(enum omap_plane plane); 341void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high); 342void dispc_enable_fifomerge(bool enable); 343void dispc_set_burst_size(enum omap_plane plane, 344 enum omap_burst_size burst_size); 345 346void dispc_set_plane_ba0(enum omap_plane plane, u32 paddr); 347void dispc_set_plane_ba1(enum omap_plane plane, u32 paddr); 348void dispc_set_plane_pos(enum omap_plane plane, u16 x, u16 y); 349void dispc_set_plane_size(enum omap_plane plane, u16 width, u16 height); 350void dispc_set_channel_out(enum omap_plane plane, 351 enum omap_channel channel_out); 352 353int dispc_setup_plane(enum omap_plane plane, 354 u32 paddr, u16 screen_width, 355 u16 pos_x, u16 pos_y, 356 u16 width, u16 height, 357 u16 out_width, u16 out_height, 358 enum omap_color_mode color_mode, 359 bool ilace, 360 enum omap_dss_rotation_type rotation_type, 361 u8 rotation, bool mirror, 362 u8 global_alpha); 363 364bool dispc_go_busy(enum omap_channel channel); 365void dispc_go(enum omap_channel channel); 366void dispc_enable_channel(enum omap_channel channel, bool enable); 367bool dispc_is_channel_enabled(enum omap_channel channel); 368int dispc_enable_plane(enum omap_plane plane, bool enable); 369void dispc_enable_replication(enum omap_plane plane, bool enable); 370 371void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode); 372void dispc_set_tft_data_lines(u8 data_lines); 373void dispc_set_lcd_display_type(enum omap_lcd_display_type type); 374void dispc_set_loadmode(enum omap_dss_load_mode mode); 375 376void dispc_set_default_color(enum omap_channel channel, u32 color); 377u32 dispc_get_default_color(enum omap_channel channel); 378void dispc_set_trans_key(enum omap_channel ch, 379 enum omap_dss_trans_key_type type, 380 u32 trans_key); 381void dispc_get_trans_key(enum omap_channel ch, 382 enum omap_dss_trans_key_type *type, 383 u32 *trans_key); 384void dispc_enable_trans_key(enum omap_channel ch, bool enable); 385void dispc_enable_alpha_blending(enum omap_channel ch, bool enable); 386bool dispc_trans_key_enabled(enum omap_channel ch); 387bool dispc_alpha_blending_enabled(enum omap_channel ch); 388 389bool dispc_lcd_timings_ok(struct omap_video_timings *timings); 390void dispc_set_lcd_timings(struct omap_video_timings *timings); 391unsigned long dispc_fclk_rate(void); 392unsigned long dispc_lclk_rate(void); 393unsigned long dispc_pclk_rate(void); 394void dispc_set_pol_freq(enum omap_panel_config config, u8 acbi, u8 acb); 395void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck, 396 struct dispc_clock_info *cinfo); 397int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, 398 struct dispc_clock_info *cinfo); 399int dispc_set_clock_div(struct dispc_clock_info *cinfo); 400int dispc_get_clock_div(struct dispc_clock_info *cinfo); 401 402 403/* VENC */ 404#ifdef CONFIG_OMAP2_DSS_VENC 405int venc_init(struct platform_device *pdev); 406void venc_exit(void); 407void venc_dump_regs(struct seq_file *s); 408int venc_init_display(struct omap_dss_device *display); 409#else 410static inline int venc_init(struct platform_device *pdev) 411{ 412 return 0; 413} 414static inline void venc_exit(void) 415{ 416} 417#endif 418 419/* RFBI */ 420#ifdef CONFIG_OMAP2_DSS_RFBI 421int rfbi_init(void); 422void rfbi_exit(void); 423void rfbi_dump_regs(struct seq_file *s); 424 425int rfbi_configure(int rfbi_module, int bpp, int lines); 426void rfbi_enable_rfbi(bool enable); 427void rfbi_transfer_area(u16 width, u16 height, 428 void (callback)(void *data), void *data); 429void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t); 430unsigned long rfbi_get_max_tx_rate(void); 431int rfbi_init_display(struct omap_dss_device *display); 432#else 433static inline int rfbi_init(void) 434{ 435 return 0; 436} 437static inline void rfbi_exit(void) 438{ 439} 440#endif 441 442 443#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 444static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr) 445{ 446 int b; 447 for (b = 0; b < 32; ++b) { 448 if (irqstatus & (1 << b)) 449 irq_arr[b]++; 450 } 451} 452#endif 453 454#endif 455