Searched refs:BIT0 (Results 1 - 25 of 101) sorted by relevance

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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/vt6655/
H A Dhostap.h36 #define WLAN_RATE_1M BIT0
H A D80211hdr.h38 #define BIT0 0x00000001 macro
164 #define WLAN_GET_FC_PRVER(n) ((((unsigned short)(n) >> 8) & (BIT0 | BIT1))
177 #define WLAN_GET_SEQ_FRGNUM(n) (((unsigned short)(n) >> 8) & (BIT0|BIT1|BIT2|BIT3))
178 #define WLAN_GET_SEQ_SEQNUM(n) ((((unsigned short)(n) >> 8) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
182 #define WLAN_GET_CAP_INFO_ESS(n) (((n) >> 8) & BIT0)
199 #define WLAN_GET_FC_PRVER(n) (((unsigned short)(n)) & (BIT0 | BIT1))
213 #define WLAN_GET_SEQ_FRGNUM(n) (((unsigned short)(n)) & (BIT0|BIT1|BIT2|BIT3))
214 #define WLAN_GET_SEQ_SEQNUM(n) ((((unsigned short)(n)) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
218 #define WLAN_GET_CAP_INFO_ESS(n) ((n) & BIT0)
266 #define WLAN_GET_ERP_NONERP_PRESENT(n) ((n) & BIT0)
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/vt6656/
H A Dhostap.h36 #define WLAN_RATE_1M BIT0
H A D80211hdr.h36 #define BIT0 0x00000001 macro
160 #define WLAN_GET_FC_PRVER(n) ((((WORD)(n) >> 8) & (BIT0 | BIT1))
174 #define WLAN_GET_SEQ_FRGNUM(n) (((WORD)(n) >> 8) & (BIT0|BIT1|BIT2|BIT3))
176 & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
179 #define WLAN_GET_CAP_INFO_ESS(n) (((n) >> 8) & BIT0)
195 #define WLAN_GET_FC_PRVER(n) (((WORD)(n)) & (BIT0 | BIT1))
208 #define WLAN_GET_SEQ_FRGNUM(n) (((WORD)(n)) & (BIT0|BIT1|BIT2|BIT3))
209 #define WLAN_GET_SEQ_SEQNUM(n) ((((WORD)(n)) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
212 #define WLAN_GET_CAP_INFO_ESS(n) ((n) & BIT0)
257 #define WLAN_GET_ERP_NONERP_PRESENT(n) ((n) & BIT0)
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/vt6655/
H A Dhostap.h36 #define WLAN_RATE_1M BIT0
H A D80211hdr.h38 #define BIT0 0x00000001 macro
164 #define WLAN_GET_FC_PRVER(n) ((((unsigned short)(n) >> 8) & (BIT0 | BIT1))
177 #define WLAN_GET_SEQ_FRGNUM(n) (((unsigned short)(n) >> 8) & (BIT0|BIT1|BIT2|BIT3))
178 #define WLAN_GET_SEQ_SEQNUM(n) ((((unsigned short)(n) >> 8) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
182 #define WLAN_GET_CAP_INFO_ESS(n) (((n) >> 8) & BIT0)
199 #define WLAN_GET_FC_PRVER(n) (((unsigned short)(n)) & (BIT0 | BIT1))
213 #define WLAN_GET_SEQ_FRGNUM(n) (((unsigned short)(n)) & (BIT0|BIT1|BIT2|BIT3))
214 #define WLAN_GET_SEQ_SEQNUM(n) ((((unsigned short)(n)) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
218 #define WLAN_GET_CAP_INFO_ESS(n) ((n) & BIT0)
266 #define WLAN_GET_ERP_NONERP_PRESENT(n) ((n) & BIT0)
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/vt6656/
H A Dhostap.h36 #define WLAN_RATE_1M BIT0
H A D80211hdr.h36 #define BIT0 0x00000001 macro
160 #define WLAN_GET_FC_PRVER(n) ((((WORD)(n) >> 8) & (BIT0 | BIT1))
174 #define WLAN_GET_SEQ_FRGNUM(n) (((WORD)(n) >> 8) & (BIT0|BIT1|BIT2|BIT3))
176 & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
179 #define WLAN_GET_CAP_INFO_ESS(n) (((n) >> 8) & BIT0)
195 #define WLAN_GET_FC_PRVER(n) (((WORD)(n)) & (BIT0 | BIT1))
208 #define WLAN_GET_SEQ_FRGNUM(n) (((WORD)(n)) & (BIT0|BIT1|BIT2|BIT3))
209 #define WLAN_GET_SEQ_SEQNUM(n) ((((WORD)(n)) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
212 #define WLAN_GET_CAP_INFO_ESS(n) ((n) & BIT0)
257 #define WLAN_GET_ERP_NONERP_PRESENT(n) ((n) & BIT0)
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/scsi/
H A Dtmscsim.h192 #define BIT0 0x00000001 macro
195 #define UNIT_ALLOCATED BIT0
201 #define DASD_SUPPORT BIT0
207 #define SRB_WAIT BIT0
224 #define SRB_OK BIT0
232 #define RESET_DEV BIT0
237 #define ABORT_DEV_ BIT0
246 #define AUTO_REQSENSE BIT0
279 #define SYNC_ENABLE BIT0
334 #define PARITY_CHK_ BIT0
[all...]
H A Ddc395x.h72 #define BIT0 0x00000001 macro
75 #define UNIT_ALLOCATED BIT0
81 #define DASD_SUPPORT BIT0
117 #define RESET_DEV BIT0
122 #define ABORT_DEV_ BIT0
125 #define SRB_OK BIT0
139 #define AUTO_REQSENSE BIT0
170 #define SYNC_NEGO_ENABLE BIT0
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/scsi/
H A Dtmscsim.h192 #define BIT0 0x00000001 macro
195 #define UNIT_ALLOCATED BIT0
201 #define DASD_SUPPORT BIT0
207 #define SRB_WAIT BIT0
224 #define SRB_OK BIT0
232 #define RESET_DEV BIT0
237 #define ABORT_DEV_ BIT0
246 #define AUTO_REQSENSE BIT0
279 #define SYNC_ENABLE BIT0
334 #define PARITY_CHK_ BIT0
[all...]
H A Ddc395x.h72 #define BIT0 0x00000001 macro
75 #define UNIT_ALLOCATED BIT0
81 #define DASD_SUPPORT BIT0
117 #define RESET_DEV BIT0
122 #define ABORT_DEV_ BIT0
125 #define SRB_OK BIT0
139 #define AUTO_REQSENSE BIT0
170 #define SYNC_NEGO_ENABLE BIT0
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192su/
H A Dr8192S_hw.h537 #define ISO_MD2PP BIT0 // MACTOP/BB/PCIe Digital to Power On.
558 #define SYS_CLKSEL_80M BIT0 // System Clock 80MHz
580 #define AFE_BGEN BIT0 // Enable AFE Macro Block's Bandgap.
586 #define SPS1_LDEN BIT0 // Enable VSPS12 LDO Macro block.
591 #define RF_EN BIT0 // Enable RF module.
598 #define LDA15_EN BIT0 // Enable LDOA15 Macro Block
603 #define LDV12_EN BIT0 // Enable LDOVD12 Macro Block
615 #define APLL_EN BIT0 // Enable AFE PLL Macro Block.
618 #define AFR_CardBEn BIT0
651 #define StopBK BIT0
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192su/
H A Dr8192S_hw.h537 #define ISO_MD2PP BIT0 // MACTOP/BB/PCIe Digital to Power On.
558 #define SYS_CLKSEL_80M BIT0 // System Clock 80MHz
580 #define AFE_BGEN BIT0 // Enable AFE Macro Block's Bandgap.
586 #define SPS1_LDEN BIT0 // Enable VSPS12 LDO Macro block.
591 #define RF_EN BIT0 // Enable RF module.
598 #define LDA15_EN BIT0 // Enable LDOA15 Macro Block
603 #define LDV12_EN BIT0 // Enable LDOVD12 Macro Block
615 #define APLL_EN BIT0 // Enable AFE PLL Macro Block.
618 #define AFR_CardBEn BIT0
651 #define StopBK BIT0
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-integrator/include/mach/
H A Dbits.h26 #define BIT0 0x00000001 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-integrator/include/mach/
H A Dbits.h26 #define BIT0 0x00000001 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192e/
H A Dr8192E_hw.h184 #define RCR_FILTER_MASK (BIT0|BIT1|BIT2|BIT3|BIT5|BIT12|BIT18|BIT19|BIT20|BIT21|BIT22|BIT23)
202 #define RCR_AAP BIT0 // Accept all unicast packet
257 #define SCR_TxUseDK BIT0 //Force Tx Use Default Key
287 #define IMR_ROK BIT0 // Receive DMA OK Interrupt
290 #define TPPoll_BKQ BIT0 // BK queue polling
337 #define AcmHw_HwEn BIT0
345 #define AcmFw_BeqStatus BIT0
400 #define BW_OPMODE_11J BIT0
423 #define RRSR_1M BIT0
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192e/
H A Dr8192E_hw.h184 #define RCR_FILTER_MASK (BIT0|BIT1|BIT2|BIT3|BIT5|BIT12|BIT18|BIT19|BIT20|BIT21|BIT22|BIT23)
202 #define RCR_AAP BIT0 // Accept all unicast packet
257 #define SCR_TxUseDK BIT0 //Force Tx Use Default Key
287 #define IMR_ROK BIT0 // Receive DMA OK Interrupt
290 #define TPPoll_BKQ BIT0 // BK queue polling
337 #define AcmHw_HwEn BIT0
345 #define AcmFw_BeqStatus BIT0
400 #define BW_OPMODE_11J BIT0
423 #define RRSR_1M BIT0
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/video/via/
H A Dvia_utility.c166 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0);
183 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
221 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0);
H A Dlcd.c412 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
588 BIT0 + BIT1 + BIT2 + BIT3);
641 BIT0 + BIT1 + BIT2);
666 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
704 viafb_write_reg_mask(SR2A, VIASR, 0, BIT0 + BIT1 + BIT2 + BIT3);
735 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
737 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
744 viafb_write_reg_mask(CR91, VIACR, 0, BIT0);
753 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);
762 viafb_write_reg_mask(SR2A, VIASR, 0x0F, BIT0
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H A Dhw.c747 viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
890 BIT0 + BIT1 + BIT2);
893 BIT0 + BIT1 + BIT2);
900 BIT0 + BIT1 + BIT2 + BIT3);
933 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
940 BIT0 + BIT1 + BIT2 + BIT3);
947 BIT0 + BIT1 + BIT2 + BIT3);
962 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
966 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 +
970 viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/video/via/
H A Dvia_utility.c166 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0);
183 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
221 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0);
H A Dlcd.c412 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
588 BIT0 + BIT1 + BIT2 + BIT3);
641 BIT0 + BIT1 + BIT2);
666 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
704 viafb_write_reg_mask(SR2A, VIASR, 0, BIT0 + BIT1 + BIT2 + BIT3);
735 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
737 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
744 viafb_write_reg_mask(CR91, VIACR, 0, BIT0);
753 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);
762 viafb_write_reg_mask(SR2A, VIASR, 0x0F, BIT0
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192u/
H A Dr8192U_hw.h160 #define RCR_AAP BIT0 // Accept all unicast packet
183 #define SCR_TxUseDK BIT0 //Force Tx Use Default Key
229 #define AcmHw_HwEn BIT0
284 #define BW_OPMODE_11J BIT0
307 #define RRSR_1M BIT0
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192u/
H A Dr8192U_hw.h160 #define RCR_AAP BIT0 // Accept all unicast packet
183 #define SCR_TxUseDK BIT0 //Force Tx Use Default Key
229 #define AcmHw_HwEn BIT0
284 #define BW_OPMODE_11J BIT0
307 #define RRSR_1M BIT0

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