1/* 2 This is part of rtl8187 OpenSource driver. 3 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it> 4 Released under the terms of GPL (General Public Licence) 5 6 Parts of this driver are based on the GPL part of the 7 official Realtek driver. 8 Parts of this driver are based on the rtl8180 driver skeleton 9 from Patric Schenke & Andres Salomon. 10 Parts of this driver are based on the Intel Pro Wireless 11 2100 GPL driver. 12 13 We want to tanks the Authors of those projects 14 and the Ndiswrapper project Authors. 15*/ 16 17/* Mariusz Matuszek added full registers definition with Realtek's name */ 18 19/* this file contains register definitions for the rtl8187 MAC controller */ 20#ifndef R8180_HW 21#define R8180_HW 22 23typedef enum _VERSION_8190{ 24 // RTL8190 25 VERSION_8190_BD=0x3, 26 VERSION_8190_BE 27}VERSION_8190,*PVERSION_8190; 28//added for different RF type 29typedef enum _RT_RF_TYPE_DEF 30{ 31 RF_1T2R = 0, 32 RF_2T4R, 33 34 RF_819X_MAX_TYPE 35}RT_RF_TYPE_DEF; 36 37typedef enum _BaseBand_Config_Type{ 38 BaseBand_Config_PHY_REG = 0, //Radio Path A 39 BaseBand_Config_AGC_TAB = 1, //Radio Path B 40}BaseBand_Config_Type, *PBaseBand_Config_Type; 41#define RTL8187_REQT_READ 0xc0 42#define RTL8187_REQT_WRITE 0x40 43#define RTL8187_REQ_GET_REGS 0x05 44#define RTL8187_REQ_SET_REGS 0x05 45 46#define R8180_MAX_RETRY 255 47#define MAX_TX_URB 5 48#define MAX_RX_URB 16 49//#define MAX_RX_NORMAL_URB 3 50//#define MAX_RX_COMMAND_URB 2 51#define RX_URB_SIZE 9100 52 53#define BB_ANTATTEN_CHAN14 0x0c 54#define BB_ANTENNA_B 0x40 55 56#define BB_HOST_BANG (1<<30) 57#define BB_HOST_BANG_EN (1<<2) 58#define BB_HOST_BANG_CLK (1<<1) 59#define BB_HOST_BANG_RW (1<<3) 60#define BB_HOST_BANG_DATA 1 61 62//#if (RTL819X_FPGA_VER & RTL819X_FPGA_VIVI_070920) 63#define RTL8190_EEPROM_ID 0x8129 64#define EEPROM_VID 0x02 65#define EEPROM_DID 0x04 66#define EEPROM_NODE_ADDRESS_BYTE_0 0x0C 67 68#define EEPROM_TxPowerDiff 0x1F 69 70 71#define EEPROM_PwDiff 0x21 //0x21 72#define EEPROM_CrystalCap 0x22 //0x22 73 74 75 76#define EEPROM_TxPwIndex_CCK_V1 0x29 //0x29~0x2B 77#define EEPROM_TxPwIndex_OFDM_24G_V1 0x2C //0x2C~0x2E 78#define EEPROM_TxPwIndex_Ver 0x27 //0x27 79 80#define EEPROM_Default_TxPowerDiff 0x0 81#define EEPROM_Default_ThermalMeter 0x77 82#define EEPROM_Default_AntTxPowerDiff 0x0 83#define EEPROM_Default_TxPwDiff_CrystalCap 0x5 84#define EEPROM_Default_PwDiff 0x4 85#define EEPROM_Default_CrystalCap 0x5 86#define EEPROM_Default_TxPower 0x1010 87#define EEPROM_ICVersion_ChannelPlan 0x7C //0x7C:ChannelPlan, 0x7D:IC_Version 88#define EEPROM_Customer_ID 0x7B //0x7B:CustomerID 89#ifdef RTL8190P 90#define EEPROM_RFInd_PowerDiff 0x14 91#define EEPROM_ThermalMeter 0x15 92#define EEPROM_TxPwDiff_CrystalCap 0x16 93#define EEPROM_TxPwIndex_CCK 0x18 //0x18~0x25 94#define EEPROM_TxPwIndex_OFDM_24G 0x26 //0x26~0x33 95#define EEPROM_TxPwIndex_OFDM_5G 0x34 //0x34~0x7B 96#define EEPROM_C56_CrystalCap 0x17 //0x17 97#define EEPROM_C56_RfA_CCK_Chnl1_TxPwIndex 0x80 //0x80 98#define EEPROM_C56_RfA_HT_OFDM_TxPwIndex 0x81 //0x81~0x83 99#define EEPROM_C56_RfC_CCK_Chnl1_TxPwIndex 0xbc //0xb8 100#define EEPROM_C56_RfC_HT_OFDM_TxPwIndex 0xb9 //0xb9~0xbb 101#else 102#ifdef RTL8192E 103#define EEPROM_RFInd_PowerDiff 0x28 104#define EEPROM_ThermalMeter 0x29 105#define EEPROM_TxPwDiff_CrystalCap 0x2A //0x2A~0x2B 106#define EEPROM_TxPwIndex_CCK 0x2C //0x23 107#define EEPROM_TxPwIndex_OFDM_24G 0x3A //0x24~0x26 108#endif 109#endif 110#define EEPROM_Default_TxPowerLevel 0x10 111//#define EEPROM_ChannelPlan 0x7c //0x7C 112#define EEPROM_IC_VER 0x7d //0x7D 113#define EEPROM_CRC 0x7e //0x7E~0x7F 114 115#define EEPROM_CID_DEFAULT 0x0 116#define EEPROM_CID_CAMEO 0x1 117#define EEPROM_CID_RUNTOP 0x2 118#define EEPROM_CID_Senao 0x3 119#define EEPROM_CID_TOSHIBA 0x4 // Toshiba setting, Merge by Jacken, 2008/01/31 120#define EEPROM_CID_NetCore 0x5 121#define EEPROM_CID_Nettronix 0x6 122#define EEPROM_CID_Pronet 0x7 123#define EEPROM_CID_DLINK 0x8 124#define EEPROM_CID_WHQL 0xFE //added by sherry for dtm, 20080728 125//#endif 126enum _RTL8192Pci_HW { 127 MAC0 = 0x000, 128 MAC1 = 0x001, 129 MAC2 = 0x002, 130 MAC3 = 0x003, 131 MAC4 = 0x004, 132 MAC5 = 0x005, 133 PCIF = 0x009, // PCI Function Register 0x0009h~0x000bh 134//---------------------------------------------------------------------------- 135// 8190 PCIF bits (Offset 0x009-000b, 24bit) 136//---------------------------------------------------------------------------- 137#define MXDMA2_16bytes 0x000 138#define MXDMA2_32bytes 0x001 139#define MXDMA2_64bytes 0x010 140#define MXDMA2_128bytes 0x011 141#define MXDMA2_256bytes 0x100 142#define MXDMA2_512bytes 0x101 143#define MXDMA2_1024bytes 0x110 144#define MXDMA2_NoLimit 0x7 145 146#define MULRW_SHIFT 3 147#define MXDMA2_RX_SHIFT 4 148#define MXDMA2_TX_SHIFT 0 149 PMR = 0x00c, // Power management register 150 EPROM_CMD = 0x00e, 151#define EPROM_CMD_RESERVED_MASK BIT5 152#define EPROM_CMD_9356SEL BIT4 153#define EPROM_CMD_OPERATING_MODE_SHIFT 6 154#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) 155#define EPROM_CMD_CONFIG 0x3 156#define EPROM_CMD_NORMAL 0 157#define EPROM_CMD_LOAD 1 158#define EPROM_CMD_PROGRAM 2 159#define EPROM_CS_SHIFT 3 160#define EPROM_CK_SHIFT 2 161#define EPROM_W_SHIFT 1 162#define EPROM_R_SHIFT 0 163 164 AFR = 0x010, 165#define AFR_CardBEn (1<<0) 166#define AFR_CLKRUN_SEL (1<<1) 167#define AFR_FuncRegEn (1<<2) 168 169 ANAPAR = 0x17, 170#define BB_GLOBAL_RESET_BIT 0x1 171 BB_GLOBAL_RESET = 0x020, // BasebandGlobal Reset Register 172 BSSIDR = 0x02E, // BSSID Register 173 CMDR = 0x037, // Command register 174#define CR_RST 0x10 175#define CR_RE 0x08 176#define CR_TE 0x04 177#define CR_MulRW 0x01 178 SIFS = 0x03E, // SIFS register 179 TCR = 0x040, // Transmit Configuration Register 180 RCR = 0x044, // Receive Configuration Register 181//---------------------------------------------------------------------------- 182//// 8190 (RCR) Receive Configuration Register (Offset 0x44~47, 32 bit) 183////---------------------------------------------------------------------------- 184#define RCR_FILTER_MASK (BIT0|BIT1|BIT2|BIT3|BIT5|BIT12|BIT18|BIT19|BIT20|BIT21|BIT22|BIT23) 185#define RCR_ONLYERLPKT BIT31 // Early Receiving based on Packet Size. 186#define RCR_ENCS2 BIT30 // Enable Carrier Sense Detection Method 2 187#define RCR_ENCS1 BIT29 // Enable Carrier Sense Detection Method 1 188#define RCR_ENMBID BIT27 // Enable Multiple BssId. 189#define RCR_ACKTXBW (BIT24|BIT25) // TXBW Setting of ACK frames 190#define RCR_CBSSID BIT23 // Accept BSSID match packet 191#define RCR_APWRMGT BIT22 // Accept power management packet 192#define RCR_ADD3 BIT21 // Accept address 3 match packet 193#define RCR_AMF BIT20 // Accept management type frame 194#define RCR_ACF BIT19 // Accept control type frame 195#define RCR_ADF BIT18 // Accept data type frame 196#define RCR_RXFTH BIT13 // Rx FIFO Threshold 197#define RCR_AICV BIT12 // Accept ICV error packet 198#define RCR_ACRC32 BIT5 // Accept CRC32 error packet 199#define RCR_AB BIT3 // Accept broadcast packet 200#define RCR_AM BIT2 // Accept multicast packet 201#define RCR_APM BIT1 // Accept physical match packet 202#define RCR_AAP BIT0 // Accept all unicast packet 203#define RCR_MXDMA_OFFSET 8 204#define RCR_FIFO_OFFSET 13 205 SLOT_TIME = 0x049, // Slot Time Register 206 ACK_TIMEOUT = 0x04c, // Ack Timeout Register 207 PIFS_TIME = 0x04d, // PIFS time 208 USTIME = 0x04e, // Microsecond Tuning Register, Sets the microsecond time unit used by MAC clock. 209 EDCAPARA_BE = 0x050, // EDCA Parameter of AC BE 210 EDCAPARA_BK = 0x054, // EDCA Parameter of AC BK 211 EDCAPARA_VO = 0x058, // EDCA Parameter of AC VO 212 EDCAPARA_VI = 0x05C, // EDCA Parameter of AC VI 213#define AC_PARAM_TXOP_LIMIT_OFFSET 16 214#define AC_PARAM_ECW_MAX_OFFSET 12 215#define AC_PARAM_ECW_MIN_OFFSET 8 216#define AC_PARAM_AIFS_OFFSET 0 217 RFPC = 0x05F, // Rx FIFO Packet Count 218 CWRR = 0x060, // Contention Window Report Register 219 BCN_TCFG = 0x062, // Beacon Time Configuration 220#define BCN_TCFG_CW_SHIFT 8 221#define BCN_TCFG_IFS 0 222 BCN_INTERVAL = 0x070, // Beacon Interval (TU) 223 ATIMWND = 0x072, // ATIM Window Size (TU) 224 BCN_DRV_EARLY_INT = 0x074, // Driver Early Interrupt Time (TU). Time to send interrupt to notify to change beacon content before TBTT 225#define BCN_DRV_EARLY_INT_SWBCN_SHIFT 8 226#define BCN_DRV_EARLY_INT_TIME_SHIFT 0 227 BCN_DMATIME = 0x076, // Beacon DMA and ATIM interrupt time (US). Indicates the time before TBTT to perform beacon queue DMA 228 BCN_ERR_THRESH = 0x078, // Beacon Error Threshold 229 RWCAM = 0x0A0, //IN 8190 Data Sheet is called CAMcmd 230 //---------------------------------------------------------------------------- 231 //// 8190 CAM Command Register (offset 0xA0, 4 byte) 232 ////---------------------------------------------------------------------------- 233#define CAM_CM_SecCAMPolling BIT31 //Security CAM Polling 234#define CAM_CM_SecCAMClr BIT30 //Clear all bits in CAM 235#define CAM_CM_SecCAMWE BIT16 //Security CAM enable 236#define CAM_VALID BIT15 237#define CAM_NOTVALID 0x0000 238#define CAM_USEDK BIT5 239 240#define CAM_NONE 0x0 241#define CAM_WEP40 0x01 242#define CAM_TKIP 0x02 243#define CAM_AES 0x04 244#define CAM_WEP104 0x05 245 246#define TOTAL_CAM_ENTRY 32 247 248#define CAM_CONFIG_USEDK true 249#define CAM_CONFIG_NO_USEDK false 250#define CAM_WRITE BIT16 251#define CAM_READ 0x00000000 252#define CAM_POLLINIG BIT31 253#define SCR_UseDK 0x01 254 WCAMI = 0x0A4, // Software write CAM input content 255 RCAMO = 0x0A8, // Software read/write CAM config 256 SECR = 0x0B0, //Security Configuration Register 257#define SCR_TxUseDK BIT0 //Force Tx Use Default Key 258#define SCR_RxUseDK BIT1 //Force Rx Use Default Key 259#define SCR_TxEncEnable BIT2 //Enable Tx Encryption 260#define SCR_RxDecEnable BIT3 //Enable Rx Decryption 261#define SCR_SKByA2 BIT4 //Search kEY BY A2 262#define SCR_NoSKMC BIT5 //No Key Search for Multicast 263 SWREGULATOR = 0x0BD, // Switching Regulator 264 INTA_MASK = 0x0f4, 265//---------------------------------------------------------------------------- 266// 8190 IMR/ISR bits (offset 0xfd, 8bits) 267//---------------------------------------------------------------------------- 268#define IMR8190_DISABLED 0x0 269#define IMR_ATIMEND BIT28 // ATIM Window End Interrupt 270#define IMR_TBDOK BIT27 // Transmit Beacon OK Interrupt 271#define IMR_TBDER BIT26 // Transmit Beacon Error Interrupt 272#define IMR_TXFOVW BIT15 // Transmit FIFO Overflow 273#define IMR_TIMEOUT0 BIT14 // TimeOut0 274#define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0 275#define IMR_RXFOVW BIT12 // Receive FIFO Overflow 276#define IMR_RDU BIT11 // Receive Descriptor Unavailable 277#define IMR_RXCMDOK BIT10 // Receive Command Packet OK 278#define IMR_BDOK BIT9 // Beacon Queue DMA OK Interrup 279#define IMR_HIGHDOK BIT8 // High Queue DMA OK Interrupt 280#define IMR_COMDOK BIT7 // Command Queue DMA OK Interrupt 281#define IMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt 282#define IMR_HCCADOK BIT5 // HCCA Queue DMA OK Interrupt 283#define IMR_BKDOK BIT4 // AC_BK DMA OK Interrupt 284#define IMR_BEDOK BIT3 // AC_BE DMA OK Interrupt 285#define IMR_VIDOK BIT2 // AC_VI DMA OK Interrupt 286#define IMR_VODOK BIT1 // AC_VO DMA Interrupt 287#define IMR_ROK BIT0 // Receive DMA OK Interrupt 288 ISR = 0x0f8, // Interrupt Status Register 289 TPPoll = 0x0fd, // Transmit priority polling register 290#define TPPoll_BKQ BIT0 // BK queue polling 291#define TPPoll_BEQ BIT1 // BE queue polling 292#define TPPoll_VIQ BIT2 // VI queue polling 293#define TPPoll_VOQ BIT3 // VO queue polling 294#define TPPoll_BQ BIT4 // Beacon queue polling 295#define TPPoll_CQ BIT5 // Command queue polling 296#define TPPoll_MQ BIT6 // Management queue polling 297#define TPPoll_HQ BIT7 // High queue polling 298#define TPPoll_HCCAQ BIT8 // HCCA queue polling 299#define TPPoll_StopBK BIT9 // Stop BK queue 300#define TPPoll_StopBE BIT10 // Stop BE queue 301#define TPPoll_StopVI BIT11 // Stop VI queue 302#define TPPoll_StopVO BIT12 // Stop VO queue 303#define TPPoll_StopMgt BIT13 // Stop Mgnt queue 304#define TPPoll_StopHigh BIT14 // Stop High queue 305#define TPPoll_StopHCCA BIT15 // Stop HCCA queue 306#define TPPoll_SHIFT 8 // Queue ID mapping 307 308 PSR = 0x0ff, // Page Select Register 309#define PSR_GEN 0x0 // Page 0 register general MAC Control 310#define PSR_CPU 0x1 // Page 1 register for CPU 311 CPU_GEN = 0x100, // CPU Reset Register 312 BB_RESET = 0x101, // Baseband Reset 313//---------------------------------------------------------------------------- 314// 8190 CPU General Register (offset 0x100, 4 byte) 315//---------------------------------------------------------------------------- 316#define CPU_CCK_LOOPBACK 0x00030000 317#define CPU_GEN_SYSTEM_RESET 0x00000001 318#define CPU_GEN_FIRMWARE_RESET 0x00000008 319#define CPU_GEN_BOOT_RDY 0x00000010 320#define CPU_GEN_FIRM_RDY 0x00000020 321#define CPU_GEN_PUT_CODE_OK 0x00000080 322#define CPU_GEN_BB_RST 0x00000100 323#define CPU_GEN_PWR_STB_CPU 0x00000004 324#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19 325#define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1 326#define CPU_GEN_GPIO_UART 0x00007000 327 328 LED1Cfg = 0x154,// LED1 Configuration Register 329 LED0Cfg = 0x155,// LED0 Configuration Register 330 331 AcmAvg = 0x170, // ACM Average Period Register 332 AcmHwCtrl = 0x171, // ACM Hardware Control Register 333//---------------------------------------------------------------------------- 334// 335// 8190 AcmHwCtrl bits (offset 0x171, 1 byte) 336//---------------------------------------------------------------------------- 337#define AcmHw_HwEn BIT0 338#define AcmHw_BeqEn BIT1 339#define AcmHw_ViqEn BIT2 340#define AcmHw_VoqEn BIT3 341#define AcmHw_BeqStatus BIT4 342#define AcmHw_ViqStatus BIT5 343#define AcmHw_VoqStatus BIT6 344 AcmFwCtrl = 0x172, // ACM Firmware Control Register 345#define AcmFw_BeqStatus BIT0 346#define AcmFw_ViqStatus BIT1 347#define AcmFw_VoqStatus BIT2 348 VOAdmTime = 0x174, // VO Queue Admitted Time Register 349 VIAdmTime = 0x178, // VI Queue Admitted Time Register 350 BEAdmTime = 0x17C, // BE Queue Admitted Time Register 351 RQPN1 = 0x180, // Reserved Queue Page Number , Vo Vi, Be, Bk 352 RQPN2 = 0x184, // Reserved Queue Page Number, HCCA, Cmd, Mgnt, High 353 RQPN3 = 0x188, // Reserved Queue Page Number, Bcn, Public, 354 QPRR = 0x1E0, // Queue Page Report per TID 355 QPNR = 0x1F0, // Queue Packet Number report per TID 356/* there's 9 tx descriptor base address available */ 357 BQDA = 0x200, // Beacon Queue Descriptor Address 358 HQDA = 0x204, // High Priority Queue Descriptor Address 359 CQDA = 0x208, // Command Queue Descriptor Address 360 MQDA = 0x20C, // Management Queue Descriptor Address 361 HCCAQDA = 0x210, // HCCA Queue Descriptor Address 362 VOQDA = 0x214, // VO Queue Descriptor Address 363 VIQDA = 0x218, // VI Queue Descriptor Address 364 BEQDA = 0x21C, // BE Queue Descriptor Address 365 BKQDA = 0x220, // BK Queue Descriptor Address 366/* there's 2 rx descriptor base address availalbe */ 367 RCQDA = 0x224, // Receive command Queue Descriptor Address 368 RDQDA = 0x228, // Receive Queue Descriptor Start Address 369 370 MAR0 = 0x240, // Multicast filter. 371 MAR4 = 0x244, 372 373 CCX_PERIOD = 0x250, // CCX Measurement Period Register, in unit of TU. 374 CLM_RESULT = 0x251, // CCA Busy fraction register. 375 NHM_PERIOD = 0x252, // NHM Measurement Period register, in unit of TU. 376 377 NHM_THRESHOLD0 = 0x253, // Noise Histogram Meashorement0. 378 NHM_THRESHOLD1 = 0x254, // Noise Histogram Meashorement1. 379 NHM_THRESHOLD2 = 0x255, // Noise Histogram Meashorement2. 380 NHM_THRESHOLD3 = 0x256, // Noise Histogram Meashorement3. 381 NHM_THRESHOLD4 = 0x257, // Noise Histogram Meashorement4. 382 NHM_THRESHOLD5 = 0x258, // Noise Histogram Meashorement5. 383 NHM_THRESHOLD6 = 0x259, // Noise Histogram Meashorement6 384 385 MCTRL = 0x25A, // Measurement Control 386 387 NHM_RPI_COUNTER0 = 0x264, // Noise Histogram RPI counter0, the fraction of signal strength < NHM_THRESHOLD0. 388 NHM_RPI_COUNTER1 = 0x265, // Noise Histogram RPI counter1, the fraction of signal strength in (NHM_THRESHOLD0, NHM_THRESHOLD1]. 389 NHM_RPI_COUNTER2 = 0x266, // Noise Histogram RPI counter2, the fraction of signal strength in (NHM_THRESHOLD1, NHM_THRESHOLD2]. 390 NHM_RPI_COUNTER3 = 0x267, // Noise Histogram RPI counter3, the fraction of signal strength in (NHM_THRESHOLD2, NHM_THRESHOLD3]. 391 NHM_RPI_COUNTER4 = 0x268, // Noise Histogram RPI counter4, the fraction of signal strength in (NHM_THRESHOLD3, NHM_THRESHOLD4]. 392 NHM_RPI_COUNTER5 = 0x269, // Noise Histogram RPI counter5, the fraction of signal strength in (NHM_THRESHOLD4, NHM_THRESHOLD5]. 393 NHM_RPI_COUNTER6 = 0x26A, // Noise Histogram RPI counter6, the fraction of signal strength in (NHM_THRESHOLD5, NHM_THRESHOLD6]. 394 NHM_RPI_COUNTER7 = 0x26B, // Noise Histogram RPI counter7, the fraction of signal strength in (NHM_THRESHOLD6, NHM_THRESHOLD7]. 395 WFCRC0 = 0x2f0, 396 WFCRC1 = 0x2f4, 397 WFCRC2 = 0x2f8, 398 399 BW_OPMODE = 0x300, // Bandwidth operation mode 400#define BW_OPMODE_11J BIT0 401#define BW_OPMODE_5G BIT1 402#define BW_OPMODE_20MHZ BIT2 403 IC_VERRSION = 0x301, //IC_VERSION 404 MSR = 0x303, // Media Status register 405#define MSR_LINK_MASK ((1<<0)|(1<<1)) 406#define MSR_LINK_MANAGED 2 407#define MSR_LINK_NONE 0 408#define MSR_LINK_SHIFT 0 409#define MSR_LINK_ADHOC 1 410#define MSR_LINK_MASTER 3 411#define MSR_LINK_ENEDCA (1<<4) 412 RETRY_LIMIT = 0x304, // Retry Limit [15:8]-short, [7:0]-long 413#define RETRY_LIMIT_SHORT_SHIFT 8 414#define RETRY_LIMIT_LONG_SHIFT 0 415 TSFR = 0x308, 416 RRSR = 0x310, // Response Rate Set 417#define RRSR_RSC_OFFSET 21 418#define RRSR_SHORT_OFFSET 23 419#define RRSR_RSC_DUPLICATE 0x600000 420#define RRSR_RSC_UPSUBCHNL 0x400000 421#define RRSR_RSC_LOWSUBCHNL 0x200000 422#define RRSR_SHORT 0x800000 423#define RRSR_1M BIT0 424#define RRSR_2M BIT1 425#define RRSR_5_5M BIT2 426#define RRSR_11M BIT3 427#define RRSR_6M BIT4 428#define RRSR_9M BIT5 429#define RRSR_12M BIT6 430#define RRSR_18M BIT7 431#define RRSR_24M BIT8 432#define RRSR_36M BIT9 433#define RRSR_48M BIT10 434#define RRSR_54M BIT11 435#define RRSR_MCS0 BIT12 436#define RRSR_MCS1 BIT13 437#define RRSR_MCS2 BIT14 438#define RRSR_MCS3 BIT15 439#define RRSR_MCS4 BIT16 440#define RRSR_MCS5 BIT17 441#define RRSR_MCS6 BIT18 442#define RRSR_MCS7 BIT19 443#define BRSR_AckShortPmb BIT23 // CCK ACK: use Short Preamble or not 444 UFWP = 0x318, 445 RATR0 = 0x320, // Rate Adaptive Table register1 446//---------------------------------------------------------------------------- 447// 8190 Rate Adaptive Table Register (offset 0x320, 4 byte) 448//---------------------------------------------------------------------------- 449//CCK 450#define RATR_1M 0x00000001 451#define RATR_2M 0x00000002 452#define RATR_55M 0x00000004 453#define RATR_11M 0x00000008 454//OFDM 455#define RATR_6M 0x00000010 456#define RATR_9M 0x00000020 457#define RATR_12M 0x00000040 458#define RATR_18M 0x00000080 459#define RATR_24M 0x00000100 460#define RATR_36M 0x00000200 461#define RATR_48M 0x00000400 462#define RATR_54M 0x00000800 463//MCS 1 Spatial Stream 464#define RATR_MCS0 0x00001000 465#define RATR_MCS1 0x00002000 466#define RATR_MCS2 0x00004000 467#define RATR_MCS3 0x00008000 468#define RATR_MCS4 0x00010000 469#define RATR_MCS5 0x00020000 470#define RATR_MCS6 0x00040000 471#define RATR_MCS7 0x00080000 472//MCS 2 Spatial Stream 473#define RATR_MCS8 0x00100000 474#define RATR_MCS9 0x00200000 475#define RATR_MCS10 0x00400000 476#define RATR_MCS11 0x00800000 477#define RATR_MCS12 0x01000000 478#define RATR_MCS13 0x02000000 479#define RATR_MCS14 0x04000000 480#define RATR_MCS15 0x08000000 481// ALL CCK Rate 482#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M 483#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|RATR_36M|RATR_48M|RATR_54M 484#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 | \ 485 RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7 486#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11| \ 487 RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 488 489 490 DRIVER_RSSI = 0x32c, // Driver tell Firmware current RSSI 491 MCS_TXAGC = 0x340, // MCS AGC 492 CCK_TXAGC = 0x348, // CCK AGC 493// IMR = 0x354, // Interrupt Mask Register 494// IMR_POLL = 0x360, 495 MacBlkCtrl = 0x403, // Mac block on/off control register 496 497 //Cmd9346CR = 0x00e, 498//#define Cmd9346CR_9356SEL (1<<4) 499 500/////////////////// 501////////////////// 502} 503; 504//---------------------------------------------------------------------------- 505// 818xB AnaParm & AnaParm2 Register 506//---------------------------------------------------------------------------- 507//#define ANAPARM_ASIC_ON 0x45090658 508//#define ANAPARM2_ASIC_ON 0x727f3f52 509 510#define GPI 0x108 511#define GPO 0x109 512#define GPE 0x10a 513 514#define ANAPAR_FOR_8192PciE 0x17 // Analog parameter register 515 516#define MSR_NOLINK 0x00 517#define MSR_ADHOC 0x01 518#define MSR_INFRA 0x02 519#define MSR_AP 0x03 520 521#endif 522