Searched refs:writel_relaxed (Results 76 - 100 of 691) sorted by relevance

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/linux-master/drivers/soc/qcom/
H A Dqcom-geni-se.c210 writel_relaxed(val, base + SE_IRQ_EN);
214 writel_relaxed(val, base + SE_GENI_DMA_MODE_EN);
216 writel_relaxed(0, base + SE_GSI_EVENT_EN);
225 writel_relaxed(val, base + GENI_CGC_CTRL);
230 writel_relaxed(val, base + SE_DMA_GENERAL_CFG);
232 writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL);
233 writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG);
238 writel_relaxed(0, se->base + SE_GSI_EVENT_EN);
239 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);
240 writel_relaxed(
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/linux-master/drivers/i2c/busses/
H A Di2c-hix5hd2.c99 writel_relaxed(val, priv->regs + HIX5I2C_ICR);
106 writel_relaxed(I2C_CLEAR_ALL, priv->regs + HIX5I2C_ICR);
111 writel_relaxed(0, priv->regs + HIX5I2C_CTRL);
116 writel_relaxed(I2C_ENABLE | I2C_UNMASK_TOTAL | I2C_UNMASK_ALL,
127 writel_relaxed(val & (~I2C_UNMASK_TOTAL), priv->regs + HIX5I2C_CTRL);
132 writel_relaxed(scl, priv->regs + HIX5I2C_SCL_H);
133 writel_relaxed(scl, priv->regs + HIX5I2C_SCL_L);
136 writel_relaxed(val, priv->regs + HIX5I2C_CTRL);
191 writel_relaxed(I2C_STOP, priv->regs + HIX5I2C_COM);
201 writel_relaxed(I2C_REA
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/linux-master/drivers/watchdog/
H A Dsprd_wdt.c74 writel_relaxed(0x0, addr + SPRD_WDT_LOCK);
79 writel_relaxed(SPRD_WDT_UNLOCK_KEY, addr + SPRD_WDT_LOCK);
87 writel_relaxed(SPRD_WDT_INT_CLEAR_BIT, wdt->base + SPRD_WDT_INT_CLR);
130 writel_relaxed((tmr_step >> SPRD_WDT_CNT_HIGH_SHIFT) &
132 writel_relaxed((tmr_step & SPRD_WDT_LOW_VALUE_MASK),
134 writel_relaxed((prtmr_step >> SPRD_WDT_CNT_HIGH_SHIFT) &
137 writel_relaxed(prtmr_step & SPRD_WDT_LOW_VALUE_MASK,
161 writel_relaxed(val, wdt->base + SPRD_WDT_CTRL);
171 writel_relaxed(0x0, wdt->base + SPRD_WDT_CTRL);
191 writel_relaxed(va
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/linux-master/drivers/gpio/
H A Dgpio-xgs-iproc.c57 writel_relaxed(event_status,
80 writel_relaxed(event_mask,
84 writel_relaxed(int_mask,
106 writel_relaxed(event_mask,
110 writel_relaxed(int_mask,
132 writel_relaxed(event_pol, chip->base + IPROC_GPIO_CCA_INT_EDGE);
137 writel_relaxed(event_pol, chip->base + IPROC_GPIO_CCA_INT_EDGE);
142 writel_relaxed(int_pol, chip->base + IPROC_GPIO_CCA_INT_LEVEL);
147 writel_relaxed(int_pol, chip->base + IPROC_GPIO_CCA_INT_LEVEL);
262 writel_relaxed(va
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H A Dgpio-davinci.c102 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
106 writel_relaxed(temp, &g->dir);
153 writel_relaxed(__gpio_mask(offset),
292 writel_relaxed(mask, &g->clr_falling);
293 writel_relaxed(mask, &g->clr_rising);
307 writel_relaxed(mask, &g->set_falling);
309 writel_relaxed(mask, &g->set_rising);
356 writel_relaxed(status, &g->intstat);
419 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
421 writel_relaxed(mas
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/linux-master/drivers/crypto/hisilicon/sec/
H A Dsec_drv.c262 writel_relaxed(regval, addr);
274 writel_relaxed(regval, addr);
284 writel_relaxed(0x7, base + SEC_ALGSUB_CLK_EN_REG);
301 writel_relaxed(0x7, base + SEC_ALGSUB_CLK_DIS_REG);
319 writel_relaxed(1, base + SEC_ALGSUB_RST_REQ_REG);
320 writel_relaxed(1, base + SEC_ALGSUB_BUILD_RST_REQ_REG);
337 writel_relaxed(1, base + SEC_ALGSUB_RST_DREQ_REG);
338 writel_relaxed(1, base + SEC_ALGSUB_BUILD_RST_DREQ_REG);
365 writel_relaxed(regval, addr);
380 writel_relaxed(
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/linux-master/drivers/clocksource/
H A Dtimer-ti-dm-systimer.c82 writel_relaxed(val, t->base + t->sysc);
90 writel_relaxed(DMTIMER_TYPE1_DISABLE, t->base + t->sysc);
100 writel_relaxed(BIT(1) | BIT(2), t->base + t->ifctrl);
116 writel_relaxed(l, sysc);
439 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat);
454 writel_relaxed(0xffffffff - cycles, t->base + t->counter);
458 writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl);
473 writel_relaxed(l, ctrl);
479 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat);
495 writel_relaxed(clkev
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H A Darmv7m_systick.c57 writel_relaxed(SYSTICK_LOAD_RELOAD_MASK, base + SYST_RVR);
58 writel_relaxed(SYST_CSR_ENABLE, base + SYST_CSR);
H A Dtimer-qcom.c44 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
56 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
58 writel_relaxed(ctrl, event_base + TIMER_CLEAR);
59 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
65 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
75 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
186 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
244 writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
H A Dtimer-cadence-ttc.c118 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
120 writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
128 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
205 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
233 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
301 writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
311 writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
321 writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
372 writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
373 writel_relaxed(CLK_CNTRL_PRESCAL
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/linux-master/arch/arm/mach-highbank/
H A Dsysregs.h33 writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu));
42 writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu));
/linux-master/arch/arm/mach-mstar/
H A Dmstarv7.c64 writel_relaxed(0, l3bridge + MSTARV7_L3BRIDGE_FLUSH);
65 writel_relaxed(MSTARV7_L3BRIDGE_FLUSH_TRIGGER, l3bridge
/linux-master/arch/arm/mach-hisi/
H A Dplatmcpm.c92 writel_relaxed(data, fabric + FAB_SF_MODE);
122 writel_relaxed(data, sys_dreq);
132 writel_relaxed(data, sys_dreq);
220 writel_relaxed(data, sysctrl + SC_CPU_RESET_REQ(cluster));
327 writel_relaxed(hip04_boot_method[0], relocation);
328 writel_relaxed(0xa5a5a5a5, relocation + 4); /* magic number */
329 writel_relaxed(__pa_symbol(secondary_startup), relocation + 8);
330 writel_relaxed(0, relocation + 12);
/linux-master/drivers/irqchip/
H A Dirq-csky-mpintc.c68 writel_relaxed(tmp | TRIG_VAL(trigger, irq), TRIG_BASE(irq));
87 writel_relaxed(d->hwirq, reg_base + INTCL_SENR);
94 writel_relaxed(d->hwirq, reg_base + INTCL_CENR);
101 writel_relaxed(d->hwirq, reg_base + INTCL_CACR);
156 writel_relaxed(cpu, INTCG_base + INTCG_CIDSTR + offset);
221 writel_relaxed((*cpumask_bits(mask)) << 8 | IPI_IRQ,
255 writel_relaxed(BIT(0), INTCG_base + INTCG_ICTLR);
266 writel_relaxed(BIT(0), per_cpu(intcl_reg, cpu) + INTCL_PICTLR);
/linux-master/arch/csky/include/asm/
H A Dio.h27 #define writel(v,c) ({ wmb(); writel_relaxed((v),(c)); })
31 #define writel(v,c) ({ wmb(); writel_relaxed((v),(c)); mb(); })
/linux-master/arch/arm/mach-omap2/
H A Dtimer.c148 writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
153 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
H A Domap-mpuss-lowpower.c123 writel_relaxed(addr, pm_info->wkup_sar_addr);
149 writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);
188 writel_relaxed(save_state, pm_info->l2x0_sar_addr);
201 writel_relaxed(l2x0_saved_regs.aux_ctrl,
203 writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
434 writel_relaxed((omap_type() != OMAP2_DEVICE_TYPE_GP) ? 1 : 0,
496 writel_relaxed(startup_pa, sar_base +
499 writel_relaxed(startup_pa, sar_base +
H A Dsram.c124 writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
125 writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
126 writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
129 writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
130 writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
131 writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
132 writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2);
133 writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
H A Dwd_timer.c48 writel_relaxed(0xAAAA, base + OMAP_WDT_SPR);
52 writel_relaxed(0x5555, base + OMAP_WDT_SPR);
/linux-master/drivers/phy/qualcomm/
H A Dphy-qcom-ipq806x-sata.c61 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3);
68 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0);
77 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM1);
82 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM2);
87 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4);
92 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4);
103 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4);
116 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4);
/linux-master/drivers/gpu/drm/meson/
H A Dmeson_viu.c332 writel_relaxed(osd1_fifo_ctrl_stat,
334 writel_relaxed(osd1_ctrl_stat2,
448 writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
449 writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));
463 writel_relaxed(0, priv->io_base + _REG(AFBC_ENABLE));
465 writel_relaxed(0x00FF00C0,
467 writel_relaxed(0x00FF00C0,
481 writel_relaxed(val, priv->io_base + _REG(VIU_OSD_BLEND_CTRL));
483 writel_relaxed(OSD_BLEND_PATH_SEL_ENABLE,
485 writel_relaxed(OSD_BLEND_PATH_SEL_ENABL
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/linux-master/drivers/clk/imx/
H A Dclk-fracn-gppll.c237 writel_relaxed(tmp, pll->base + PLL_CTRL);
242 writel_relaxed(tmp, pll->base + PLL_CTRL);
246 writel_relaxed(tmp, pll->base + PLL_CTRL);
250 writel_relaxed(tmp, pll->base + PLL_CTRL);
254 writel_relaxed(pll_div, pll->base + PLL_DIV);
256 writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR);
257 writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUMERATOR);
265 writel_relaxed(tmp, pll->base + PLL_CTRL);
274 writel_relaxed(tmp, pll->base + PLL_CTRL);
295 writel_relaxed(va
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/linux-master/drivers/spi/
H A Dspi-qup.c232 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
233 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
237 writel_relaxed(cur_state, controller->base + QUP_STATE);
296 writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
335 writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
360 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO);
382 writel_relaxed(QUP_OP_OUT_SERVICE_FLAG,
631 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS);
632 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS);
662 writel_relaxed(opflag
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/linux-master/drivers/clk/mmp/
H A Dclk-apbc.c49 writel_relaxed(data, apbc->base);
61 writel_relaxed(data, apbc->base);
74 writel_relaxed(data, apbc->base);
96 writel_relaxed(data, apbc->base);
108 writel_relaxed(data, apbc->base);
/linux-master/arch/arm/mach-exynos/
H A Dfirmware.c40 writel_relaxed(__pa_symbol(exynos_cpu_resume_ns),
42 writel_relaxed(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
99 writel_relaxed(boot_addr, boot_reg);
251 writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4);
260 writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4);

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