1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * OMAP2+ MPU WD_TIMER-specific code
4 *
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 */
7
8#include <linux/kernel.h>
9#include <linux/io.h>
10#include <linux/err.h>
11
12#include <linux/platform_data/omap-wd-timer.h>
13
14#include "omap_hwmod.h"
15#include "omap_device.h"
16#include "wd_timer.h"
17#include "common.h"
18#include "prm.h"
19#include "soc.h"
20
21/*
22 * In order to avoid any assumptions from bootloader regarding WDT
23 * settings, WDT module is reset during init. This enables the watchdog
24 * timer. Hence it is required to disable the watchdog after the WDT reset
25 * during init. Otherwise the system would reboot as per the default
26 * watchdog timer registers settings.
27 */
28#define OMAP_WDT_WPS		0x34
29#define OMAP_WDT_SPR		0x48
30
31int omap2_wd_timer_disable(struct omap_hwmod *oh)
32{
33	void __iomem *base;
34
35	if (!oh) {
36		pr_err("%s: Could not look up wdtimer_hwmod\n", __func__);
37		return -EINVAL;
38	}
39
40	base = omap_hwmod_get_mpu_rt_va(oh);
41	if (!base) {
42		pr_err("%s: Could not get the base address for %s\n",
43				oh->name, __func__);
44		return -EINVAL;
45	}
46
47	/* sequence required to disable watchdog */
48	writel_relaxed(0xAAAA, base + OMAP_WDT_SPR);
49	while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10)
50		cpu_relax();
51
52	writel_relaxed(0x5555, base + OMAP_WDT_SPR);
53	while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10)
54		cpu_relax();
55
56	return 0;
57}
58
59/**
60 * omap2_wd_timer_reset - reset and disable the WDTIMER IP block
61 * @oh: struct omap_hwmod *
62 *
63 * After the WDTIMER IP blocks are reset on OMAP2/3, we must also take
64 * care to execute the special watchdog disable sequence.  This is
65 * because the watchdog is re-armed upon OCP softreset.  (On OMAP4,
66 * this behavior was apparently changed and the watchdog is no longer
67 * re-armed after an OCP soft-reset.)  Returns -ETIMEDOUT if the reset
68 * did not complete, or 0 upon success.
69 *
70 * XXX Most of this code should be moved to the omap_hwmod.c layer
71 * during a normal merge window.  omap_hwmod_softreset() should be
72 * renamed to omap_hwmod_set_ocp_softreset(), and omap_hwmod_softreset()
73 * should call the hwmod _ocp_softreset() code.
74 *
75 * Returns: %0 on success or -errno value on error.
76 */
77int omap2_wd_timer_reset(struct omap_hwmod *oh)
78{
79	int c = 0;
80
81	/* Write to the SOFTRESET bit */
82	omap_hwmod_softreset(oh);
83
84	/* Poll on RESETDONE bit */
85	omap_test_timeout((omap_hwmod_read(oh,
86					   oh->class->sysc->syss_offs)
87			   & SYSS_RESETDONE_MASK),
88			  MAX_MODULE_SOFTRESET_WAIT, c);
89
90	if (oh->class->sysc->srst_udelay)
91		udelay(oh->class->sysc->srst_udelay);
92
93	if (c == MAX_MODULE_SOFTRESET_WAIT)
94		pr_warn("%s: %s: softreset failed (waited %d usec)\n",
95			__func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
96	else
97		pr_debug("%s: %s: softreset in %d usec\n", __func__,
98			 oh->name, c);
99
100	return (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT :
101		omap2_wd_timer_disable(oh);
102}
103