Searched refs:membase (Results 76 - 100 of 208) sorted by relevance

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/linux-master/drivers/atm/
H A Dnicstar.c105 #define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ)
217 writel(0x00000000, card->membase + CFG);
256 iounmap(card->membase);
319 writel(sram_address, card->membase + CMD);
321 data = readl(card->membase + DR0);
337 writel(*(value++), card->membase + i);
339 so card->membase + DR0 == card->membase */
343 writel(sram_address, card->membase + CMD);
357 unsigned long membase; local
[all...]
/linux-master/drivers/tty/serial/
H A Dstm32-usart.c124 val = readl_relaxed(port->membase + reg);
126 writel_relaxed(val, port->membase + reg);
133 val = readl_relaxed(port->membase + reg);
135 writel_relaxed(val, port->membase + reg);
143 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC)
234 cr1 = readl_relaxed(port->membase + ofs->cr1);
235 cr3 = readl_relaxed(port->membase + ofs->cr3);
236 usartdiv = readl_relaxed(port->membase + ofs->brr);
255 writel_relaxed(cr3, port->membase + ofs->cr3);
256 writel_relaxed(cr1, port->membase
[all...]
H A Dmux.c63 #define UART_PUT_CHAR(p, c) __raw_writel((c), (p)->membase + IO_DATA_REG_OFFSET)
64 #define UART_GET_FIFO_CNT(p) __raw_readl((p)->membase + IO_DCOUNT_REG_OFFSET)
213 data = __raw_readl(port->membase + IO_DATA_REG_OFFSET);
339 if(port->membase == NULL)
454 port->membase = ioremap(port->mapbase, MUX_LINE_OFFSET);
491 if(port->membase)
492 iounmap(port->membase);
H A Dclps711x.c106 ch = readw(port->membase + UARTDR_OFFSET);
152 writew(port->x_char, port->membase + UARTDR_OFFSET);
169 writew(xmit->buf[xmit->tail], port->membase + UARTDR_OFFSET);
212 ubrlcr = readl(port->membase + UBRLCR_OFFSET);
217 writel(ubrlcr, port->membase + UBRLCR_OFFSET);
236 writel(readl(port->membase + UBRLCR_OFFSET) & ~UBRLCR_BREAK,
237 port->membase + UBRLCR_OFFSET);
309 writel(ubrlcr | (quot - 1), port->membase + UBRLCR_OFFSET);
361 writew(ch, port->membase + UARTDR_OFFSET);
402 ubrlcr = readl(port->membase
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H A Dsa1100.c45 #define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0)
46 #define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1)
47 #define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2)
48 #define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3)
49 #define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0)
50 #define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1)
51 #define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR)
53 #define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0)
54 #define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1)
55 #define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase
[all...]
H A Dowl-uart.c86 writel(val, port->membase + off);
91 return readl(port->membase + off);
391 devm_iounmap(port->dev, port->membase);
392 port->membase = NULL;
410 port->membase = devm_ioremap(port->dev, port->mapbase,
412 if (!port->membase)
460 ret = readl_poll_timeout_atomic(port->membase + OWL_UART_STAT, reg,
499 if (!port->membase)
567 if (!owl_port || !owl_port->port.membase)
606 if (!device->port.membase)
[all...]
H A Dbcm63xx_uart.c76 return __raw_readl(port->membase + offset);
82 __raw_writel(value, port->membase + offset);
739 if (!port->membase)
778 if (!device->port.membase)
823 if (port->membase)
827 port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res_mem);
828 if (IS_ERR(port->membase))
829 return PTR_ERR(port->membase);
856 ports[pdev->id].membase = NULL;
870 ports[pdev->id].membase
[all...]
H A Dmps2-uart.c87 writeb(val, mps_port->port.membase + off);
94 return readb(mps_port->port.membase + off);
101 writel_relaxed(val, mps_port->port.membase + off);
470 while (readb(port->membase + UARTn_STATE) & UARTn_STATE_TX_FULL)
473 writeb((unsigned char)ch, port->membase + UARTn_DATA);
486 if (!device->port.membase)
541 mps_port->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
542 if (IS_ERR(mps_port->port.membase))
543 return PTR_ERR(mps_port->port.membase);
H A Darc_uart.c9 * +Using platform_get_resource() for irq/membase (thx to bfin_uart.c)
68 #define RBASE(port, reg) (port->membase + reg)
494 if (!port->membase)
553 if (!dev->port.membase)
606 port->membase = devm_platform_ioremap_resource(pdev, 0);
607 if (IS_ERR(port->membase)) {
609 return PTR_ERR(port->membase);
H A Desp32_acm.c50 writel(v, port->membase + reg);
55 return readl(port->membase + reg);
346 if (!device->port.membase)
396 port->membase = devm_ioremap_resource(&pdev->dev, res);
397 if (IS_ERR(port->membase))
398 return PTR_ERR(port->membase);
H A Dvt8500_serial.c114 writel(val, port->membase + off);
119 return readl(port->membase + off);
169 c = readw(port->membase + VT8500_RXFIFO) & 0x3ff;
203 writeb(ch, port->membase + VT8500_TXFIFO));
469 writeb(c, port->membase + VT8500_TXFIFO);
646 vt8500_port->uart.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &mmres);
647 if (IS_ERR(vt8500_port->uart.membase))
648 return PTR_ERR(vt8500_port->uart.membase);
/linux-master/drivers/tty/serial/8250/
H A D8250_ingenic.c46 return readl(port->membase + (offset << 2));
51 writel(value, port->membase + (offset << 2));
96 if (!dev->port.membase)
206 writeb(value, p->membase + (offset << p->regshift));
213 value = readb(p->membase + (offset << p->regshift));
272 uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
274 if (!uart.port.membase)
H A D8250_dw.c105 void __iomem *offset = p->membase + (UART_LCR << p->regshift);
144 lsr = readb (p->membase + (UART_LSR << p->regshift));
163 writeb(value, p->membase + (offset << p->regshift));
180 unsigned int value = readb(p->membase + (offset << p->regshift));
190 value = (u8)__raw_readq(p->membase + (offset << p->regshift));
200 __raw_writeq(value, p->membase + (offset << p->regshift));
202 __raw_readq(p->membase + (UART_LCR << p->regshift));
213 writel(value, p->membase + (offset << p->regshift));
221 unsigned int value = readl(p->membase + (offset << p->regshift));
230 iowrite32be(value, p->membase
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H A D8250_hp300.c118 port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE);
135 port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE);
177 uart.port.membase = (char *)(uart.port.mapbase + DIO_VIRADDRBASE);
259 uart.port.membase = (char *)(base + DIO_VIRADDRBASE);
H A D8250_mid.c183 chip->regs = p->membase;
235 writel(ps, p->membase + INTEL_MID_UART_PS); /* set PS */
236 writel(mul, p->membase + INTEL_MID_UART_MUL); /* set MUL */
237 writel(div, p->membase + INTEL_MID_UART_DIV);
316 uart.port.membase = pcim_iomap(pdev, mid->board->bar, 0);
317 if (!uart.port.membase)
/linux-master/drivers/reset/
H A Dreset-uniphier-glue.c61 priv->rdata.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
62 if (IS_ERR(priv->rdata.membase))
63 return PTR_ERR(priv->rdata.membase);
/linux-master/drivers/comedi/drivers/
H A Dii_pci20kc.c419 unsigned int membase; local
424 membase = it->options[0];
425 if (!membase || (membase & ~(0x100000 - II20K_SIZE))) {
432 if (!request_mem_region(membase, II20K_SIZE, dev->board_name)) {
434 dev->board_name, membase, II20K_SIZE);
437 dev->iobase = membase; /* actually, a memory address */
439 dev->mmio = ioremap(membase, II20K_SIZE);
/linux-master/drivers/dma/
H A Dfsl-edma-common.c860 * edma "version" and "membase" appropriately.
866 edma->regs.cr = edma->membase + EDMA_CR;
867 edma->regs.es = edma->membase + EDMA_ES;
868 edma->regs.erql = edma->membase + EDMA_ERQ;
869 edma->regs.eeil = edma->membase + EDMA_EEI;
871 edma->regs.serq = edma->membase + (is64 ? EDMA64_SERQ : EDMA_SERQ);
872 edma->regs.cerq = edma->membase + (is64 ? EDMA64_CERQ : EDMA_CERQ);
873 edma->regs.seei = edma->membase + (is64 ? EDMA64_SEEI : EDMA_SEEI);
874 edma->regs.ceei = edma->membase + (is64 ? EDMA64_CEEI : EDMA_CEEI);
875 edma->regs.cint = edma->membase
[all...]
/linux-master/arch/arm/plat-orion/
H A Dcommon.c91 void __iomem *membase,
97 data->membase = membase;
125 void __init orion_uart0_init(void __iomem *membase, argument
131 membase, mapbase, irq, clk);
153 void __init orion_uart1_init(void __iomem *membase, argument
159 membase, mapbase, irq, clk);
181 void __init orion_uart2_init(void __iomem *membase, argument
187 membase, mapbase, irq, clk);
209 void __init orion_uart3_init(void __iomem *membase, argument
87 uart_complete( struct platform_device *orion_uart, struct plat_serial8250_port *data, struct resource *resources, void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk) argument
[all...]
/linux-master/drivers/pinctrl/
H A Dpinctrl-falcon.c246 void __iomem *mem = info->membase[PORT(pin)];
283 void __iomem *mem = info->membase[PORT(pin)];
331 pad_r32(info->membase[port], LTQ_PADC_MUX(PORT_PIN(offset))));
383 if ((port >= PORTS) || (!info->membase[port]))
386 pad_w32(info->membase[port], mux,
413 if ((id >= PORTS) || (!falcon_info.membase[id]))
416 avail = pad_r32(falcon_info.membase[id], LTQ_PADC_AVAIL);
461 falcon_info.membase[*bank] = devm_ioremap_resource(&pdev->dev,
463 if (IS_ERR(falcon_info.membase[*bank])) {
465 return PTR_ERR(falcon_info.membase[*ban
[all...]
/linux-master/include/linux/isdn/
H A Dcapilli.h36 unsigned int membase; member in struct:capicardparams
/linux-master/drivers/net/ethernet/sfc/
H A Dio.h63 __raw_writeq((__force u64)value, efx->membase + reg);
67 return (__force __le64)__raw_readq(efx->membase + reg);
74 __raw_writel((__force u32)value, efx->membase + reg);
78 return (__force __le32)__raw_readl(efx->membase + reg);
H A Def100_netdev.c69 void __iomem *membase; local
75 membase = ioremap(efx->membase_phys, uc_mem_map_size);
76 if (!membase) {
82 iounmap(efx->membase);
83 efx->membase = membase;
/linux-master/drivers/pinctrl/sunxi/
H A Dpinctrl-sunxi.c551 val = (readl(pctl->membase + reg) & mask) >> shift;
652 writel((readl(pctl->membase + reg) & ~mask) | val << shift,
653 pctl->membase + reg);
718 reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
720 writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
726 reg = readl(pctl->membase + PIO_POW_MOD_CTL_REG);
728 writel(reg | val, pctl->membase + PIO_POW_MOD_CTL_REG);
736 reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG);
738 writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG);
787 writel((readl(pctl->membase
[all...]
/linux-master/drivers/net/ethernet/8390/
H A Dmac8390.c223 static enum mac8390_access mac8390_testio(unsigned long membase) argument
229 nubus_writel(outdata, membase);
231 indata = nubus_readl(membase);
239 word_memcpy_tocard(membase, &outdata, 4);
241 word_memcpy_fromcard(&indata, membase, 4);
248 static int mac8390_memsize(unsigned long membase) argument
256 volatile unsigned short *m = (unsigned short *)(membase + (i * 0x1000));
271 volatile unsigned short *p = (unsigned short *)(membase + (j * 0x1000));

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