1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Synopsys DesignWare 8250 driver. 4 * 5 * Copyright 2011 Picochip, Jamie Iles. 6 * Copyright 2013 Intel Corporation 7 * 8 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the 9 * LCR is written whilst busy. If it is, then a busy detect interrupt is 10 * raised, the LCR needs to be rewritten and the uart status register read. 11 */ 12#include <linux/clk.h> 13#include <linux/delay.h> 14#include <linux/device.h> 15#include <linux/io.h> 16#include <linux/mod_devicetable.h> 17#include <linux/module.h> 18#include <linux/notifier.h> 19#include <linux/platform_device.h> 20#include <linux/pm_runtime.h> 21#include <linux/property.h> 22#include <linux/reset.h> 23#include <linux/slab.h> 24#include <linux/workqueue.h> 25 26#include <asm/byteorder.h> 27 28#include <linux/serial_8250.h> 29#include <linux/serial_reg.h> 30 31#include "8250_dwlib.h" 32 33/* Offsets for the DesignWare specific registers */ 34#define DW_UART_USR 0x1f /* UART Status Register */ 35#define DW_UART_DMASA 0xa8 /* DMA Software Ack */ 36 37#define OCTEON_UART_USR 0x27 /* UART Status Register */ 38 39#define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */ 40#define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */ 41 42/* DesignWare specific register fields */ 43#define DW_UART_MCR_SIRE BIT(6) 44 45/* Renesas specific register fields */ 46#define RZN1_UART_xDMACR_DMA_EN BIT(0) 47#define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1) 48#define RZN1_UART_xDMACR_4_WORD_BURST (1 << 1) 49#define RZN1_UART_xDMACR_8_WORD_BURST (2 << 1) 50#define RZN1_UART_xDMACR_BLK_SZ(x) ((x) << 3) 51 52/* Quirks */ 53#define DW_UART_QUIRK_OCTEON BIT(0) 54#define DW_UART_QUIRK_ARMADA_38X BIT(1) 55#define DW_UART_QUIRK_SKIP_SET_RATE BIT(2) 56#define DW_UART_QUIRK_IS_DMA_FC BIT(3) 57#define DW_UART_QUIRK_APMC0D08 BIT(4) 58 59static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb) 60{ 61 return container_of(nb, struct dw8250_data, clk_notifier); 62} 63 64static inline struct dw8250_data *work_to_dw8250_data(struct work_struct *work) 65{ 66 return container_of(work, struct dw8250_data, clk_work); 67} 68 69static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value) 70{ 71 struct dw8250_data *d = to_dw8250_data(p->private_data); 72 73 /* Override any modem control signals if needed */ 74 if (offset == UART_MSR) { 75 value |= d->msr_mask_on; 76 value &= ~d->msr_mask_off; 77 } 78 79 return value; 80} 81 82static void dw8250_force_idle(struct uart_port *p) 83{ 84 struct uart_8250_port *up = up_to_u8250p(p); 85 unsigned int lsr; 86 87 serial8250_clear_and_reinit_fifos(up); 88 89 /* 90 * With PSLVERR_RESP_EN parameter set to 1, the device generates an 91 * error response when an attempt to read an empty RBR with FIFO 92 * enabled. 93 */ 94 if (up->fcr & UART_FCR_ENABLE_FIFO) { 95 lsr = p->serial_in(p, UART_LSR); 96 if (!(lsr & UART_LSR_DR)) 97 return; 98 } 99 100 (void)p->serial_in(p, UART_RX); 101} 102 103static void dw8250_check_lcr(struct uart_port *p, int value) 104{ 105 void __iomem *offset = p->membase + (UART_LCR << p->regshift); 106 int tries = 1000; 107 108 /* Make sure LCR write wasn't ignored */ 109 while (tries--) { 110 unsigned int lcr = p->serial_in(p, UART_LCR); 111 112 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) 113 return; 114 115 dw8250_force_idle(p); 116 117#ifdef CONFIG_64BIT 118 if (p->type == PORT_OCTEON) 119 __raw_writeq(value & 0xff, offset); 120 else 121#endif 122 if (p->iotype == UPIO_MEM32) 123 writel(value, offset); 124 else if (p->iotype == UPIO_MEM32BE) 125 iowrite32be(value, offset); 126 else 127 writeb(value, offset); 128 } 129 /* 130 * FIXME: this deadlocks if port->lock is already held 131 * dev_err(p->dev, "Couldn't set LCR to %d\n", value); 132 */ 133} 134 135/* Returns once the transmitter is empty or we run out of retries */ 136static void dw8250_tx_wait_empty(struct uart_port *p) 137{ 138 struct uart_8250_port *up = up_to_u8250p(p); 139 unsigned int tries = 20000; 140 unsigned int delay_threshold = tries - 1000; 141 unsigned int lsr; 142 143 while (tries--) { 144 lsr = readb (p->membase + (UART_LSR << p->regshift)); 145 up->lsr_saved_flags |= lsr & up->lsr_save_mask; 146 147 if (lsr & UART_LSR_TEMT) 148 break; 149 150 /* The device is first given a chance to empty without delay, 151 * to avoid slowdowns at high bitrates. If after 1000 tries 152 * the buffer has still not emptied, allow more time for low- 153 * speed links. */ 154 if (tries < delay_threshold) 155 udelay (1); 156 } 157} 158 159static void dw8250_serial_out(struct uart_port *p, int offset, int value) 160{ 161 struct dw8250_data *d = to_dw8250_data(p->private_data); 162 163 writeb(value, p->membase + (offset << p->regshift)); 164 165 if (offset == UART_LCR && !d->uart_16550_compatible) 166 dw8250_check_lcr(p, value); 167} 168 169static void dw8250_serial_out38x(struct uart_port *p, int offset, int value) 170{ 171 /* Allow the TX to drain before we reconfigure */ 172 if (offset == UART_LCR) 173 dw8250_tx_wait_empty(p); 174 175 dw8250_serial_out(p, offset, value); 176} 177 178static unsigned int dw8250_serial_in(struct uart_port *p, int offset) 179{ 180 unsigned int value = readb(p->membase + (offset << p->regshift)); 181 182 return dw8250_modify_msr(p, offset, value); 183} 184 185#ifdef CONFIG_64BIT 186static unsigned int dw8250_serial_inq(struct uart_port *p, int offset) 187{ 188 unsigned int value; 189 190 value = (u8)__raw_readq(p->membase + (offset << p->regshift)); 191 192 return dw8250_modify_msr(p, offset, value); 193} 194 195static void dw8250_serial_outq(struct uart_port *p, int offset, int value) 196{ 197 struct dw8250_data *d = to_dw8250_data(p->private_data); 198 199 value &= 0xff; 200 __raw_writeq(value, p->membase + (offset << p->regshift)); 201 /* Read back to ensure register write ordering. */ 202 __raw_readq(p->membase + (UART_LCR << p->regshift)); 203 204 if (offset == UART_LCR && !d->uart_16550_compatible) 205 dw8250_check_lcr(p, value); 206} 207#endif /* CONFIG_64BIT */ 208 209static void dw8250_serial_out32(struct uart_port *p, int offset, int value) 210{ 211 struct dw8250_data *d = to_dw8250_data(p->private_data); 212 213 writel(value, p->membase + (offset << p->regshift)); 214 215 if (offset == UART_LCR && !d->uart_16550_compatible) 216 dw8250_check_lcr(p, value); 217} 218 219static unsigned int dw8250_serial_in32(struct uart_port *p, int offset) 220{ 221 unsigned int value = readl(p->membase + (offset << p->regshift)); 222 223 return dw8250_modify_msr(p, offset, value); 224} 225 226static void dw8250_serial_out32be(struct uart_port *p, int offset, int value) 227{ 228 struct dw8250_data *d = to_dw8250_data(p->private_data); 229 230 iowrite32be(value, p->membase + (offset << p->regshift)); 231 232 if (offset == UART_LCR && !d->uart_16550_compatible) 233 dw8250_check_lcr(p, value); 234} 235 236static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset) 237{ 238 unsigned int value = ioread32be(p->membase + (offset << p->regshift)); 239 240 return dw8250_modify_msr(p, offset, value); 241} 242 243 244static int dw8250_handle_irq(struct uart_port *p) 245{ 246 struct uart_8250_port *up = up_to_u8250p(p); 247 struct dw8250_data *d = to_dw8250_data(p->private_data); 248 unsigned int iir = p->serial_in(p, UART_IIR); 249 bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT; 250 unsigned int quirks = d->pdata->quirks; 251 unsigned int status; 252 unsigned long flags; 253 254 /* 255 * There are ways to get Designware-based UARTs into a state where 256 * they are asserting UART_IIR_RX_TIMEOUT but there is no actual 257 * data available. If we see such a case then we'll do a bogus 258 * read. If we don't do this then the "RX TIMEOUT" interrupt will 259 * fire forever. 260 * 261 * This problem has only been observed so far when not in DMA mode 262 * so we limit the workaround only to non-DMA mode. 263 */ 264 if (!up->dma && rx_timeout) { 265 uart_port_lock_irqsave(p, &flags); 266 status = serial_lsr_in(up); 267 268 if (!(status & (UART_LSR_DR | UART_LSR_BI))) 269 (void) p->serial_in(p, UART_RX); 270 271 uart_port_unlock_irqrestore(p, flags); 272 } 273 274 /* Manually stop the Rx DMA transfer when acting as flow controller */ 275 if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) { 276 uart_port_lock_irqsave(p, &flags); 277 status = serial_lsr_in(up); 278 uart_port_unlock_irqrestore(p, flags); 279 280 if (status & (UART_LSR_DR | UART_LSR_BI)) { 281 dw8250_writel_ext(p, RZN1_UART_RDMACR, 0); 282 dw8250_writel_ext(p, DW_UART_DMASA, 1); 283 } 284 } 285 286 if (serial8250_handle_irq(p, iir)) 287 return 1; 288 289 if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { 290 /* Clear the USR */ 291 (void)p->serial_in(p, d->pdata->usr_reg); 292 293 return 1; 294 } 295 296 return 0; 297} 298 299static void dw8250_clk_work_cb(struct work_struct *work) 300{ 301 struct dw8250_data *d = work_to_dw8250_data(work); 302 struct uart_8250_port *up; 303 unsigned long rate; 304 305 rate = clk_get_rate(d->clk); 306 if (rate <= 0) 307 return; 308 309 up = serial8250_get_port(d->data.line); 310 311 serial8250_update_uartclk(&up->port, rate); 312} 313 314static int dw8250_clk_notifier_cb(struct notifier_block *nb, 315 unsigned long event, void *data) 316{ 317 struct dw8250_data *d = clk_to_dw8250_data(nb); 318 319 /* 320 * We have no choice but to defer the uartclk update due to two 321 * deadlocks. First one is caused by a recursive mutex lock which 322 * happens when clk_set_rate() is called from dw8250_set_termios(). 323 * Second deadlock is more tricky and is caused by an inverted order of 324 * the clk and tty-port mutexes lock. It happens if clock rate change 325 * is requested asynchronously while set_termios() is executed between 326 * tty-port mutex lock and clk_set_rate() function invocation and 327 * vise-versa. Anyway if we didn't have the reference clock alteration 328 * in the dw8250_set_termios() method we wouldn't have needed this 329 * deferred event handling complication. 330 */ 331 if (event == POST_RATE_CHANGE) { 332 queue_work(system_unbound_wq, &d->clk_work); 333 return NOTIFY_OK; 334 } 335 336 return NOTIFY_DONE; 337} 338 339static void 340dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) 341{ 342 if (!state) 343 pm_runtime_get_sync(port->dev); 344 345 serial8250_do_pm(port, state, old); 346 347 if (state) 348 pm_runtime_put_sync_suspend(port->dev); 349} 350 351static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, 352 const struct ktermios *old) 353{ 354 unsigned long newrate = tty_termios_baud_rate(termios) * 16; 355 struct dw8250_data *d = to_dw8250_data(p->private_data); 356 long rate; 357 int ret; 358 359 clk_disable_unprepare(d->clk); 360 rate = clk_round_rate(d->clk, newrate); 361 if (rate > 0) { 362 /* 363 * Note that any clock-notifer worker will block in 364 * serial8250_update_uartclk() until we are done. 365 */ 366 ret = clk_set_rate(d->clk, newrate); 367 if (!ret) 368 p->uartclk = rate; 369 } 370 clk_prepare_enable(d->clk); 371 372 dw8250_do_set_termios(p, termios, old); 373} 374 375static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios) 376{ 377 struct uart_8250_port *up = up_to_u8250p(p); 378 unsigned int mcr = p->serial_in(p, UART_MCR); 379 380 if (up->capabilities & UART_CAP_IRDA) { 381 if (termios->c_line == N_IRDA) 382 mcr |= DW_UART_MCR_SIRE; 383 else 384 mcr &= ~DW_UART_MCR_SIRE; 385 386 p->serial_out(p, UART_MCR, mcr); 387 } 388 serial8250_do_set_ldisc(p, termios); 389} 390 391/* 392 * dw8250_fallback_dma_filter will prevent the UART from getting just any free 393 * channel on platforms that have DMA engines, but don't have any channels 394 * assigned to the UART. 395 * 396 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the 397 * core problem is fixed, this function is no longer needed. 398 */ 399static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param) 400{ 401 return false; 402} 403 404static bool dw8250_idma_filter(struct dma_chan *chan, void *param) 405{ 406 return param == chan->device->dev; 407} 408 409static u32 dw8250_rzn1_get_dmacr_burst(int max_burst) 410{ 411 if (max_burst >= 8) 412 return RZN1_UART_xDMACR_8_WORD_BURST; 413 else if (max_burst >= 4) 414 return RZN1_UART_xDMACR_4_WORD_BURST; 415 else 416 return RZN1_UART_xDMACR_1_WORD_BURST; 417} 418 419static void dw8250_prepare_tx_dma(struct uart_8250_port *p) 420{ 421 struct uart_port *up = &p->port; 422 struct uart_8250_dma *dma = p->dma; 423 u32 val; 424 425 dw8250_writel_ext(up, RZN1_UART_TDMACR, 0); 426 val = dw8250_rzn1_get_dmacr_burst(dma->txconf.dst_maxburst) | 427 RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) | 428 RZN1_UART_xDMACR_DMA_EN; 429 dw8250_writel_ext(up, RZN1_UART_TDMACR, val); 430} 431 432static void dw8250_prepare_rx_dma(struct uart_8250_port *p) 433{ 434 struct uart_port *up = &p->port; 435 struct uart_8250_dma *dma = p->dma; 436 u32 val; 437 438 dw8250_writel_ext(up, RZN1_UART_RDMACR, 0); 439 val = dw8250_rzn1_get_dmacr_burst(dma->rxconf.src_maxburst) | 440 RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) | 441 RZN1_UART_xDMACR_DMA_EN; 442 dw8250_writel_ext(up, RZN1_UART_RDMACR, val); 443} 444 445static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) 446{ 447 unsigned int quirks = data->pdata ? data->pdata->quirks : 0; 448 449#ifdef CONFIG_64BIT 450 if (quirks & DW_UART_QUIRK_OCTEON) { 451 p->serial_in = dw8250_serial_inq; 452 p->serial_out = dw8250_serial_outq; 453 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; 454 p->type = PORT_OCTEON; 455 data->skip_autocfg = true; 456 } 457#endif 458 459 if (quirks & DW_UART_QUIRK_ARMADA_38X) 460 p->serial_out = dw8250_serial_out38x; 461 if (quirks & DW_UART_QUIRK_SKIP_SET_RATE) 462 p->set_termios = dw8250_do_set_termios; 463 if (quirks & DW_UART_QUIRK_IS_DMA_FC) { 464 data->data.dma.txconf.device_fc = 1; 465 data->data.dma.rxconf.device_fc = 1; 466 data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma; 467 data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma; 468 } 469 if (quirks & DW_UART_QUIRK_APMC0D08) { 470 p->iotype = UPIO_MEM32; 471 p->regshift = 2; 472 p->serial_in = dw8250_serial_in32; 473 data->uart_16550_compatible = true; 474 } 475 476 /* Platforms with iDMA 64-bit */ 477 if (platform_get_resource_byname(to_platform_device(p->dev), 478 IORESOURCE_MEM, "lpss_priv")) { 479 data->data.dma.rx_param = p->dev->parent; 480 data->data.dma.tx_param = p->dev->parent; 481 data->data.dma.fn = dw8250_idma_filter; 482 } 483} 484 485static void dw8250_reset_control_assert(void *data) 486{ 487 reset_control_assert(data); 488} 489 490static int dw8250_probe(struct platform_device *pdev) 491{ 492 struct uart_8250_port uart = {}, *up = &uart; 493 struct uart_port *p = &up->port; 494 struct device *dev = &pdev->dev; 495 struct dw8250_data *data; 496 struct resource *regs; 497 int err; 498 499 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 500 if (!regs) 501 return dev_err_probe(dev, -EINVAL, "no registers defined\n"); 502 503 spin_lock_init(&p->lock); 504 p->handle_irq = dw8250_handle_irq; 505 p->pm = dw8250_do_pm; 506 p->type = PORT_8250; 507 p->flags = UPF_FIXED_PORT; 508 p->dev = dev; 509 p->set_ldisc = dw8250_set_ldisc; 510 p->set_termios = dw8250_set_termios; 511 512 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 513 if (!data) 514 return -ENOMEM; 515 516 data->data.dma.fn = dw8250_fallback_dma_filter; 517 data->pdata = device_get_match_data(p->dev); 518 p->private_data = &data->data; 519 520 data->uart_16550_compatible = device_property_read_bool(dev, 521 "snps,uart-16550-compatible"); 522 523 p->mapbase = regs->start; 524 p->mapsize = resource_size(regs); 525 526 p->membase = devm_ioremap(dev, p->mapbase, p->mapsize); 527 if (!p->membase) 528 return -ENOMEM; 529 530 err = uart_read_port_properties(p); 531 /* no interrupt -> fall back to polling */ 532 if (err == -ENXIO) 533 err = 0; 534 if (err) 535 return err; 536 537 switch (p->iotype) { 538 case UPIO_MEM: 539 p->serial_in = dw8250_serial_in; 540 p->serial_out = dw8250_serial_out; 541 break; 542 case UPIO_MEM32: 543 p->serial_in = dw8250_serial_in32; 544 p->serial_out = dw8250_serial_out32; 545 break; 546 case UPIO_MEM32BE: 547 p->serial_in = dw8250_serial_in32be; 548 p->serial_out = dw8250_serial_out32be; 549 break; 550 default: 551 return -ENODEV; 552 } 553 554 if (device_property_read_bool(dev, "dcd-override")) { 555 /* Always report DCD as active */ 556 data->msr_mask_on |= UART_MSR_DCD; 557 data->msr_mask_off |= UART_MSR_DDCD; 558 } 559 560 if (device_property_read_bool(dev, "dsr-override")) { 561 /* Always report DSR as active */ 562 data->msr_mask_on |= UART_MSR_DSR; 563 data->msr_mask_off |= UART_MSR_DDSR; 564 } 565 566 if (device_property_read_bool(dev, "cts-override")) { 567 /* Always report CTS as active */ 568 data->msr_mask_on |= UART_MSR_CTS; 569 data->msr_mask_off |= UART_MSR_DCTS; 570 } 571 572 if (device_property_read_bool(dev, "ri-override")) { 573 /* Always report Ring indicator as inactive */ 574 data->msr_mask_off |= UART_MSR_RI; 575 data->msr_mask_off |= UART_MSR_TERI; 576 } 577 578 /* If there is separate baudclk, get the rate from it. */ 579 data->clk = devm_clk_get_optional_enabled(dev, "baudclk"); 580 if (data->clk == NULL) 581 data->clk = devm_clk_get_optional_enabled(dev, NULL); 582 if (IS_ERR(data->clk)) 583 return dev_err_probe(dev, PTR_ERR(data->clk), 584 "failed to get baudclk\n"); 585 586 INIT_WORK(&data->clk_work, dw8250_clk_work_cb); 587 data->clk_notifier.notifier_call = dw8250_clk_notifier_cb; 588 589 if (data->clk) 590 p->uartclk = clk_get_rate(data->clk); 591 592 /* If no clock rate is defined, fail. */ 593 if (!p->uartclk) 594 return dev_err_probe(dev, -EINVAL, "clock rate not defined\n"); 595 596 data->pclk = devm_clk_get_optional_enabled(dev, "apb_pclk"); 597 if (IS_ERR(data->pclk)) 598 return PTR_ERR(data->pclk); 599 600 data->rst = devm_reset_control_get_optional_exclusive(dev, NULL); 601 if (IS_ERR(data->rst)) 602 return PTR_ERR(data->rst); 603 604 reset_control_deassert(data->rst); 605 606 err = devm_add_action_or_reset(dev, dw8250_reset_control_assert, data->rst); 607 if (err) 608 return err; 609 610 dw8250_quirks(p, data); 611 612 /* If the Busy Functionality is not implemented, don't handle it */ 613 if (data->uart_16550_compatible) 614 p->handle_irq = NULL; 615 616 if (!data->skip_autocfg) 617 dw8250_setup_port(p); 618 619 /* If we have a valid fifosize, try hooking up DMA */ 620 if (p->fifosize) { 621 data->data.dma.rxconf.src_maxburst = p->fifosize / 4; 622 data->data.dma.txconf.dst_maxburst = p->fifosize / 4; 623 up->dma = &data->data.dma; 624 } 625 626 data->data.line = serial8250_register_8250_port(up); 627 if (data->data.line < 0) 628 return data->data.line; 629 630 /* 631 * Some platforms may provide a reference clock shared between several 632 * devices. In this case any clock state change must be known to the 633 * UART port at least post factum. 634 */ 635 if (data->clk) { 636 err = clk_notifier_register(data->clk, &data->clk_notifier); 637 if (err) 638 return dev_err_probe(dev, err, "Failed to set the clock notifier\n"); 639 queue_work(system_unbound_wq, &data->clk_work); 640 } 641 642 platform_set_drvdata(pdev, data); 643 644 pm_runtime_set_active(dev); 645 pm_runtime_enable(dev); 646 647 return 0; 648} 649 650static void dw8250_remove(struct platform_device *pdev) 651{ 652 struct dw8250_data *data = platform_get_drvdata(pdev); 653 struct device *dev = &pdev->dev; 654 655 pm_runtime_get_sync(dev); 656 657 if (data->clk) { 658 clk_notifier_unregister(data->clk, &data->clk_notifier); 659 660 flush_work(&data->clk_work); 661 } 662 663 serial8250_unregister_port(data->data.line); 664 665 pm_runtime_disable(dev); 666 pm_runtime_put_noidle(dev); 667} 668 669static int dw8250_suspend(struct device *dev) 670{ 671 struct dw8250_data *data = dev_get_drvdata(dev); 672 673 serial8250_suspend_port(data->data.line); 674 675 return 0; 676} 677 678static int dw8250_resume(struct device *dev) 679{ 680 struct dw8250_data *data = dev_get_drvdata(dev); 681 682 serial8250_resume_port(data->data.line); 683 684 return 0; 685} 686 687static int dw8250_runtime_suspend(struct device *dev) 688{ 689 struct dw8250_data *data = dev_get_drvdata(dev); 690 691 clk_disable_unprepare(data->clk); 692 693 clk_disable_unprepare(data->pclk); 694 695 return 0; 696} 697 698static int dw8250_runtime_resume(struct device *dev) 699{ 700 struct dw8250_data *data = dev_get_drvdata(dev); 701 702 clk_prepare_enable(data->pclk); 703 704 clk_prepare_enable(data->clk); 705 706 return 0; 707} 708 709static const struct dev_pm_ops dw8250_pm_ops = { 710 SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume) 711 RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL) 712}; 713 714static const struct dw8250_platform_data dw8250_dw_apb = { 715 .usr_reg = DW_UART_USR, 716}; 717 718static const struct dw8250_platform_data dw8250_octeon_3860_data = { 719 .usr_reg = OCTEON_UART_USR, 720 .quirks = DW_UART_QUIRK_OCTEON, 721}; 722 723static const struct dw8250_platform_data dw8250_armada_38x_data = { 724 .usr_reg = DW_UART_USR, 725 .quirks = DW_UART_QUIRK_ARMADA_38X, 726}; 727 728static const struct dw8250_platform_data dw8250_renesas_rzn1_data = { 729 .usr_reg = DW_UART_USR, 730 .cpr_val = 0x00012f32, 731 .quirks = DW_UART_QUIRK_IS_DMA_FC, 732}; 733 734static const struct dw8250_platform_data dw8250_starfive_jh7100_data = { 735 .usr_reg = DW_UART_USR, 736 .quirks = DW_UART_QUIRK_SKIP_SET_RATE, 737}; 738 739static const struct of_device_id dw8250_of_match[] = { 740 { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb }, 741 { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data }, 742 { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data }, 743 { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data }, 744 { .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data }, 745 { /* Sentinel */ } 746}; 747MODULE_DEVICE_TABLE(of, dw8250_of_match); 748 749static const struct dw8250_platform_data dw8250_apmc0d08 = { 750 .usr_reg = DW_UART_USR, 751 .quirks = DW_UART_QUIRK_APMC0D08, 752}; 753 754static const struct acpi_device_id dw8250_acpi_match[] = { 755 { "80860F0A", (kernel_ulong_t)&dw8250_dw_apb }, 756 { "8086228A", (kernel_ulong_t)&dw8250_dw_apb }, 757 { "AMD0020", (kernel_ulong_t)&dw8250_dw_apb }, 758 { "AMDI0020", (kernel_ulong_t)&dw8250_dw_apb }, 759 { "AMDI0022", (kernel_ulong_t)&dw8250_dw_apb }, 760 { "APMC0D08", (kernel_ulong_t)&dw8250_apmc0d08 }, 761 { "BRCM2032", (kernel_ulong_t)&dw8250_dw_apb }, 762 { "HISI0031", (kernel_ulong_t)&dw8250_dw_apb }, 763 { "INT33C4", (kernel_ulong_t)&dw8250_dw_apb }, 764 { "INT33C5", (kernel_ulong_t)&dw8250_dw_apb }, 765 { "INT3434", (kernel_ulong_t)&dw8250_dw_apb }, 766 { "INT3435", (kernel_ulong_t)&dw8250_dw_apb }, 767 { "INTC10EE", (kernel_ulong_t)&dw8250_dw_apb }, 768 { }, 769}; 770MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); 771 772static struct platform_driver dw8250_platform_driver = { 773 .driver = { 774 .name = "dw-apb-uart", 775 .pm = pm_ptr(&dw8250_pm_ops), 776 .of_match_table = dw8250_of_match, 777 .acpi_match_table = dw8250_acpi_match, 778 }, 779 .probe = dw8250_probe, 780 .remove_new = dw8250_remove, 781}; 782 783module_platform_driver(dw8250_platform_driver); 784 785MODULE_AUTHOR("Jamie Iles"); 786MODULE_LICENSE("GPL"); 787MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver"); 788MODULE_ALIAS("platform:dw-apb-uart"); 789