tty/serial/stm32-usart.c

124 	val = readl_relaxed(port->membase + reg);
126 	writel_relaxed(val, port->membase + reg);
133 	val = readl_relaxed(port->membase + reg);
135 	writel_relaxed(val, port->membase + reg);
143 	if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC)
234 		cr1 = readl_relaxed(port->membase + ofs->cr1);
235 		cr3 = readl_relaxed(port->membase + ofs->cr3);
236 		usartdiv = readl_relaxed(port->membase + ofs->brr);
255 		writel_relaxed(cr3, port->membase + ofs->cr3);
256 		writel_relaxed(cr1, port->membase + ofs->cr1);
353 	*sr = readl_relaxed(port->membase + ofs->isr);
374 	c = readl_relaxed(port->membase + ofs->rdr);
406 				       port->membase + ofs->icr);
510 			sr = readl_relaxed(port->membase + ofs->isr);
705 		if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
711 		writel_relaxed(ch, port->membase + ofs->tdr);
801 		readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
808 		writel_relaxed(port->x_char, port->membase + ofs->tdr);
825 		writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
854 	sr = readl_relaxed(port->membase + ofs->isr);
866 			       port->membase + ofs->icr);
873 			       port->membase + ofs->icr);
1079 		val = readl_relaxed(port->membase + ofs->cr2);
1081 		writel_relaxed(val, port->membase + ofs->cr2);
1087 		writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr);
1127 	ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
1144 			       port->membase + ofs->rqr);
1177 	ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
1187 	writel_relaxed(0, port->membase + ofs->cr1);
1192 			       port->membase + ofs->rqr);
1200 	cr3 = readl_relaxed(port->membase + ofs->cr3);
1254 		writel_relaxed(bits, port->membase + ofs->rtor);
1302 				writel_relaxed(presc, port->membase + ofs->presc);
1316 	writel_relaxed(brr, port->membase + ofs->brr);
1382 	writel_relaxed(cr3, port->membase + ofs->cr3);
1383 	writel_relaxed(cr2, port->membase + ofs->cr2);
1384 	writel_relaxed(cr1, port->membase + ofs->cr1);
1460 	if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_RXNE))
1463 	return readl_relaxed(port->membase + ofs->rdr) & stm32_port->rdr_mask;
1525 			 readl_relaxed(stm32port->port.membase + ofs->hwcfgr1));
1595 	port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1596 	if (IS_ERR(port->membase))
1597 		return PTR_ERR(port->membase);
1895 	cr3 = readl_relaxed(port->membase + ofs->cr3);
1900 	writel_relaxed(cr3, port->membase + ofs->cr3);
1917 	ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, isr,
1924 	writel_relaxed(ch, port->membase + ofs->tdr);
1945 	old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1948 	writel_relaxed(new_cr1, port->membase + ofs->cr1);
1953 	writel_relaxed(old_cr1, port->membase + ofs->cr1);
1978 	if (stm32port->port.mapbase == 0 || !stm32port->port.membase)
2008 	while (!(readl_relaxed(port->membase + info->ofs.isr) & USART_SR_TXE))
2011 	writel_relaxed(ch, port->membase + info->ofs.tdr);
2024 	if (!(device->port.membase || device->port.iobase))
2033 	if (!(device->port.membase || device->port.iobase))
2042 	if (!(device->port.membase || device->port.iobase))