/linux-master/drivers/media/platform/ti/omap3isp/ |
H A D | isp.c | 159 static void isp_xclk_update(struct isp_xclk *xclk, u32 divider) argument 165 divider << ISPTCTRL_CTRL_DIVA_SHIFT); 170 divider << ISPTCTRL_CTRL_DIVB_SHIFT); 197 isp_xclk_update(xclk, xclk->divider); 220 return parent_rate / xclk->divider; 225 u32 divider; local 235 divider = DIV_ROUND_CLOSEST(parent_rate, *rate); 236 if (divider >= ISPTCTRL_CTRL_DIV_BYPASS) 237 divider = ISPTCTRL_CTRL_DIV_BYPASS - 1; 239 *rate = parent_rate / divider; 255 u32 divider; local [all...] |
/linux-master/drivers/media/usb/dvb-usb/ |
H A D | dib0700_core.c | 433 u16 divider; local 445 divider = (u16) (30000 / scl_kHz); 447 st->buf[2] = (u8) (divider >> 8); 448 st->buf[3] = (u8) (divider & 0xff); 449 divider = (u16) (72000 / scl_kHz); 450 st->buf[4] = (u8) (divider >> 8); 451 st->buf[5] = (u8) (divider & 0xff); 452 divider = (u16) (72000 / scl_kHz); /* clock: 72MHz */ 453 st->buf[6] = (u8) (divider >> 8); 454 st->buf[7] = (u8) (divider [all...] |
/linux-master/sound/soc/spear/ |
H A D | spdif_out.c | 94 u32 divider, ctrl; local 97 divider = DIV_ROUND_CLOSEST(clk_get_rate(host->clk), (rate * 128)); 101 ctrl |= (divider << SPDIF_DIVIDER_SHIFT) & SPDIF_DIVIDER_MASK;
|
/linux-master/drivers/net/can/sja1000/ |
H A D | sja1000_platform.c | 183 u32 divider = priv->can.clock.freq * 2 / prop; local 185 if (divider > 1) 186 priv->cdr |= divider / 2 - 1;
|
/linux-master/drivers/gpu/drm/radeon/ |
H A D | r600_dpm.h | 180 u32 index, u32 divider); 182 u32 index, u32 divider); 184 u32 index, u32 divider);
|
/linux-master/arch/mips/sgi-ip22/ |
H A D | ip22-mc.c | 124 /* Step 4: Initialize the RPSS divider register to run as fast 138 sgimc->divider = 0x101;
|
/linux-master/drivers/clk/hisilicon/ |
H A D | clk.h | 154 hisi_clk_unregister(divider)
|
/linux-master/drivers/video/fbdev/matrox/ |
H A D | matroxfb_misc.c | 195 unsigned int divider; local 247 divider = minfo->curr.final_bppShift; 248 while (divider & 3) { 253 divider <<= 1; 255 divider = divider / 4; 256 /* divider can be from 1 to 8 */ 257 while (divider > 8) { 262 divider >>= 1; 301 hw->CRTCEXT[3] = (divider [all...] |
/linux-master/drivers/comedi/drivers/ |
H A D | dt282x.c | 366 unsigned int prescale, base, divider; local 375 divider = DIV_ROUND_CLOSEST(*ns, base); 378 divider = (*ns) / base; 381 divider = DIV_ROUND_UP(*ns, base); 384 if (divider <= DT2821_DIVIDER_MAX) 387 if (divider > DT2821_DIVIDER_MAX) { 389 divider = DT2821_DIVIDER_MAX; 392 *ns = divider * base; 394 DT2821_TMRCTR_DIVIDER(divider);
|
H A D | rtd520.c | 369 * proper counter value (divider-1). Sets the original period to be the 376 int divider; local 381 divider = DIV_ROUND_CLOSEST(*nanosec, base); 384 divider = (*nanosec) / base; 387 divider = DIV_ROUND_UP(*nanosec, base); 390 if (divider < 2) 391 divider = 2; /* min is divide by 2 */ 398 *nanosec = base * divider; 399 return divider - 1; /* countdown is divisor+1 */ 404 * (divider [all...] |
/linux-master/sound/soc/stm/ |
H A D | stm32_i2s.c | 224 * @divider: prescaler division ratio 249 unsigned int divider; member in struct:stm32_i2s_data 268 unsigned int ratio, div, divider = 1; local 273 /* Check the parity of the divider */ 279 /* If div is 0 actual divider is 1 */ 281 divider = ((2 * div) + odd); 283 div, odd, divider); 288 dev_err(&i2s->pdev->dev, "Wrong divider setting\n"); 292 if (input_rate % divider) 295 output_rate, input_rate / divider); [all...] |
/linux-master/drivers/media/i2c/ |
H A D | mt9t112.c | 409 priv->info->divider.m, priv->info->divider.n, 410 priv->info->divider.p1, priv->info->divider.p2, 411 priv->info->divider.p3, priv->info->divider.p4, 412 priv->info->divider.p5, priv->info->divider.p6, 413 priv->info->divider.p7);
|
/linux-master/drivers/gpu/drm/vc4/ |
H A D | vc4_dsi.c | 575 u32 divider; member in struct:vc4_dsi 826 * DSI PLL divider. 830 * divider. PLLD_DSI1, which drives our DSI bit clock (and therefore 831 * the pixel clock), only has an integer divider off of DSI. 846 unsigned long pll_clock = pixel_clock_hz * dsi->divider; 847 int divider; local 849 /* Find what divider gets us a faster clock than the requested 852 for (divider = 1; divider < 255; divider [all...] |
/linux-master/sound/oss/dmasound/ |
H A D | dmasound_atari.c | 1024 tt_dmasnd.int_div = 0; /* STE compatible divider */ 1035 int divider, i, idx; local 1065 divider = 1; 1069 divider = 1; 1072 divider = 2; 1075 divider = 3; 1078 divider = 4; 1081 divider = 5; 1084 divider = 7; 1087 divider [all...] |
/linux-master/drivers/clk/tegra/ |
H A D | Makefile | 6 obj-y += clk-divider.o
|
/linux-master/drivers/iio/adc/ |
H A D | cpcap-adc.c | 171 * @divider: divider in the phasing table 178 unsigned short divider; member in struct:cpcap_adc_phasing_tbl 190 * @divider: conversion divider 198 int divider; member in struct:cpcap_adc_conversion_tbl 687 if (phase_tbl[index].divider == 0) 689 req->result /= phase_tbl[index].divider; 699 if (phase_tbl[index].divider == 0) 701 req->result /= phase_tbl[index].divider; [all...] |
/linux-master/drivers/watchdog/ |
H A D | nic7018_wdt.c | 53 u8 divider; member in struct:nic7018_config 95 outb(counter << 4 | config->divider,
|
/linux-master/arch/m68k/coldfire/ |
H A D | m53xx.c | 549 /* Check bounds of divider */ 559 /* Apply the divider to the system clock */ 585 int divider; local 589 divider = readw(MCF_CCM_CDR) & MCF_CCM_CDR_LPDIV(0xF); 590 return (FREF/(2 << divider));
|
/linux-master/drivers/hwmon/ |
H A D | bt1-pvt.h | 227 * @divider: distributed divider per each degree. 228 * @divider_leftover: divider leftover, which couldn't be redistributed. 233 long divider; member in struct:pvt_poly_term 239 * @total_divider: total data divider.
|
/linux-master/drivers/clk/ |
H A D | Makefile | 6 obj-$(CONFIG_COMMON_CLK) += clk-divider.o 14 obj-$(CONFIG_COMMON_CLK) += clk-fractional-divider.o
|
/linux-master/drivers/iio/imu/inv_mpu6050/ |
H A D | inv_mpu_ring.c | 115 fifo_period = NSEC_PER_SEC / INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
|
/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/ |
H A D | opp.h | 255 uint32_t divider; /* (actually HW range is min/divider; divider !=0) */ member in struct:hw_adjustment_range
|
/linux-master/include/linux/firmware/ |
H A D | xlnx-zynqmp.h | 542 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider); 543 int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider); 643 static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) argument 648 static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) argument
|
/linux-master/include/linux/mfd/ |
H A D | db8500-prcmu.h | 504 int prcmu_set_clock_divider(u8 clock, u8 divider); 613 static inline int prcmu_set_clock_divider(u8 clock, u8 divider) argument
|
/linux-master/drivers/clk/imx/ |
H A D | Makefile | 10 mxc-clk-objs += clk-divider-gate.o
|