Searched refs:clk (Results 76 - 100 of 4090) sorted by relevance

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/linux-master/drivers/clk/imx/
H A Dclk-lpcg-scu.c8 #include <linux/clk-provider.h>
14 #include "clk-scu.h"
46 struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw); local
52 reg = readl_relaxed(clk->reg);
53 reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx);
56 if (clk->hw_gate)
59 reg |= val << clk->bit_idx;
60 writel(reg, clk->reg);
69 struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw); local
75 reg = readl_relaxed(clk
91 struct clk_lpcg_scu *clk; local
128 struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw); local
136 struct clk_lpcg_scu *clk = dev_get_drvdata(dev); local
146 struct clk_lpcg_scu *clk = dev_get_drvdata(dev); local
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H A Dclk.c3 #include <linux/clk.h>
4 #include <linux/clk-provider.h>
11 #include "clk.h"
42 void imx_check_clocks(struct clk *clks[], unsigned int count)
48 pr_err("i.MX clk %u: register failed with %ld\n",
58 pr_err("i.MX clk %u: register failed with %ld\n",
63 static struct clk *imx_obtain_fixed_clock_from_dt(const char *name)
66 struct clk *clk = ERR_PTR(-ENODEV); local
77 clk
86 struct clk *clk; local
97 struct clk *clk; local
108 struct clk *clk = of_clk_get_by_name(np, name); local
121 struct clk *clk; local
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/linux-master/arch/arm/mach-omap1/
H A Dclock.c17 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
33 /* provide direct internal access (not via clk API) to some clocks */
47 unsigned long omap1_uart_recalc(struct omap1_clk *clk, unsigned long p_rate) argument
49 unsigned int val = __raw_readl(clk->enable_reg);
50 return val & 1 << clk->enable_bit ? 48000000 : 12000000;
53 unsigned long omap1_sossi_recalc(struct omap1_clk *clk, unsigned long p_rate) argument
63 static void omap1_clk_allow_idle(struct omap1_clk *clk) argument
65 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
67 if (!(clk
74 omap1_clk_deny_idle(struct omap1_clk *clk) argument
166 omap1_ckctl_recalc(struct omap1_clk *clk, unsigned long p_rate) argument
178 struct omap1_clk *clk = to_omap1_clk(hw); local
207 omap1_ckctl_recalc_dsp_domain(struct omap1_clk *clk, unsigned long p_rate) argument
230 omap1_select_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate) argument
265 omap1_clk_set_rate_dsp_domain(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate) argument
285 omap1_clk_round_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate) argument
297 omap1_clk_set_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate) argument
324 omap1_round_to_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate) argument
375 omap1_round_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate) argument
380 omap1_set_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate) argument
406 omap1_set_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate) argument
440 omap1_round_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate) argument
453 omap1_set_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate) argument
478 omap1_round_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate) argument
483 omap1_init_ext_clk(struct omap1_clk *clk) argument
505 struct omap1_clk *clk = to_omap1_clk(hw), *parent = to_omap1_clk(clk_hw_get_parent(hw)); local
519 struct omap1_clk *clk = to_omap1_clk(hw), *parent = to_omap1_clk(clk_hw_get_parent(hw)); local
528 omap1_clk_enable_generic(struct omap1_clk *clk) argument
576 omap1_clk_disable_generic(struct omap1_clk *clk) argument
624 omap1_clk_enable_dsp_domain(struct omap1_clk *clk) argument
643 omap1_clk_disable_dsp_domain(struct omap1_clk *clk) argument
664 omap1_clk_enable_uart_functional_16xx(struct omap1_clk *clk) argument
681 omap1_clk_disable_uart_functional_16xx(struct omap1_clk *clk) argument
700 struct omap1_clk *clk = to_omap1_clk(hw); local
710 struct omap1_clk *clk = to_omap1_clk(hw); local
720 struct omap1_clk *clk = to_omap1_clk(hw); local
734 struct omap1_clk *clk = to_omap1_clk(hw); local
746 struct omap1_clk *clk = to_omap1_clk(hw); local
797 followparent_recalc(struct omap1_clk *clk, unsigned long p_rate) argument
806 omap_fixed_divisor_recalc(struct omap1_clk *clk, unsigned long p_rate) argument
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/linux-master/drivers/clk/sunxi/
H A Dclk-a10-codec.c8 #include <linux/clk-provider.h>
16 struct clk *clk; local
27 clk = clk_register_gate(NULL, clk_name, parent_name,
31 if (!IS_ERR(clk))
32 of_clk_add_provider(node, of_clk_src_simple_get, clk);
34 CLK_OF_DECLARE(sun4i_codec, "allwinner,sun4i-a10-codec-clk",
/linux-master/arch/arm/mach-omap2/
H A Dmcbsp.c12 #include <linux/clk.h>
34 static int omap3_mcbsp_force_ick_on(struct clk *clk, bool force_on) argument
36 if (!clk)
40 return omap2_clk_deny_idle(clk);
42 return omap2_clk_allow_idle(clk);
/linux-master/drivers/clk/ux500/
H A Dclk-sysctrl.c9 #include <linux/clk-provider.h>
16 #include "clk.h"
38 struct clk_sysctrl *clk = to_clk_sysctrl(hw); local
40 ret = ab8500_sysctrl_write(clk->reg_sel[0], clk->reg_mask[0],
41 clk->reg_bits[0]);
43 if (!ret && clk->enable_delay_us)
44 usleep_range(clk->enable_delay_us, clk->enable_delay_us +
45 (clk
52 struct clk_sysctrl *clk = to_clk_sysctrl(hw); local
61 struct clk_sysctrl *clk = to_clk_sysctrl(hw); local
67 struct clk_sysctrl *clk = to_clk_sysctrl(hw); local
97 struct clk_sysctrl *clk = to_clk_sysctrl(hw); local
130 struct clk_sysctrl *clk; local
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H A DMakefile7 obj-y += clk-prcc.o
8 obj-y += clk-prcmu.o
9 obj-y += clk-sysctrl.o
18 obj-y += abx500-clk.o
H A Dclk-prcmu.c9 #include <linux/clk-provider.h>
14 #include "clk.h"
36 struct clk_prcmu *clk = to_clk_prcmu(hw); local
38 return prcmu_request_clock(clk->cg_sel, true);
43 struct clk_prcmu *clk = to_clk_prcmu(hw); local
44 if (prcmu_request_clock(clk->cg_sel, false))
52 struct clk_prcmu *clk = to_clk_prcmu(hw); local
53 return prcmu_clock_rate(clk->cg_sel);
59 struct clk_prcmu *clk = to_clk_prcmu(hw); local
60 return prcmu_round_clock_rate(clk
66 struct clk_prcmu *clk = to_clk_prcmu(hw); local
73 struct clk_prcmu *clk = to_clk_prcmu(hw); local
100 struct clk_prcmu *clk = to_clk_prcmu(hw); local
118 struct clk_prcmu *clk = to_clk_prcmu(hw); local
142 struct clk_prcmu *clk = to_clk_prcmu(hw); local
201 struct clk_prcmu *clk; local
300 struct clk_prcmu_clkout *clk = to_clk_prcmu_clkout(hw); local
307 struct clk_prcmu_clkout *clk = to_clk_prcmu_clkout(hw); local
320 struct clk_prcmu_clkout *clk = to_clk_prcmu_clkout(hw); local
327 struct clk_prcmu_clkout *clk = to_clk_prcmu_clkout(hw); local
334 struct clk_prcmu_clkout *clk = to_clk_prcmu_clkout(hw); local
358 struct clk_prcmu_clkout *clk; local
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/linux-master/drivers/clocksource/
H A Dclksrc_st_lpc.c11 #include <linux/clk.h>
26 struct clk *clk; member in struct:st_clksrc_ddata
50 rate = clk_get_rate(ddata.clk);
67 struct clk *clk; local
69 clk = of_clk_get(np, 0);
70 if (IS_ERR(clk)) {
72 return PTR_ERR(clk);
75 if (clk_prepare_enable(clk)) {
[all...]
/linux-master/sound/soc/mediatek/mt8195/
H A Dmt8195-afe-clk.h3 * mt8195-afe-clk.h -- Mediatek 8195 afe clock ctrl definition
104 int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
105 void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
106 int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk);
107 void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk);
108 int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *cl
[all...]
/linux-master/drivers/clk/
H A Dclk-conf.c7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/clk/clk-conf.h>
18 struct clk *clk, *pclk; local
23 pr_err("clk: invalid value of clock-parents property at %pOF\n",
44 pr_warn("clk: couldn't get parent clock %d for %pOF\n",
58 clk = of_clk_get_from_provider(&clkspec);
60 if (IS_ERR(clk)) {
87 struct clk *clk; local
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H A Dclk-fixed-mmio.c12 #include <linux/clk-provider.h>
20 struct clk_hw *clk; local
36 clk = clk_hw_register_fixed_rate(NULL, clk_name, NULL, 0, freq);
37 if (IS_ERR(clk)) {
39 return clk;
42 ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, clk);
45 clk_hw_unregister(clk);
46 clk = ERR_PTR(ret);
49 return clk;
63 struct clk_hw *clk; local
76 struct clk_hw *clk = platform_get_drvdata(pdev); local
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/linux-master/drivers/clk/ti/
H A Dfixed-factor.c10 #include <linux/clk-provider.h>
15 #include <linux/clk/ti.h>
30 struct clk *clk; local
51 clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags,
54 if (!IS_ERR(clk)) {
55 of_clk_add_provider(node, of_clk_src_simple_get, clk);
57 ti_clk_add_alias(clk, clk_name);
/linux-master/drivers/clk/at91/
H A DMakefile3 # Makefile for at91 specific clk
7 obj-y += clk-slow.o clk-main.o clk-pll.o clk-plldiv.o clk-master.o
8 obj-y += clk-system.o clk-peripheral.o clk-programmable.o
10 obj-$(CONFIG_HAVE_AT91_AUDIO_PLL) += clk
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/linux-master/include/linux/
H A Dinterconnect-clk.h12 struct clk *clk; member in struct:icc_clk_data
H A Dsh_clk.h10 #include <linux/clk.h>
13 struct clk;
24 void (*init)(struct clk *clk);
26 int (*enable)(struct clk *clk);
27 void (*disable)(struct clk *clk);
28 unsigned long (*recalc)(struct clk *clk);
38 struct clk { struct
[all...]
/linux-master/drivers/clk/sunxi-ng/
H A Dccu_mmc_timing.c6 #include <linux/clk-provider.h>
7 #include <linux/clk/sunxi-ng.h>
14 * @clk: clock to be configured
20 int sunxi_ccu_set_mmc_timing_mode(struct clk *clk, bool new_mode) argument
22 struct clk_hw *hw = __clk_get_hw(clk);
47 * @clk: clock to query
53 int sunxi_ccu_get_mmc_timing_mode(struct clk *clk) argument
55 struct clk_hw *hw = __clk_get_hw(clk);
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/linux-master/sound/soc/mediatek/mt6797/
H A Dmt6797-afe-clk.c3 // mt6797-afe-clk.c -- Mediatek 6797 afe clock ctrl
8 #include <linux/clk.h>
11 #include "mt6797-afe-clk.h"
39 afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
41 if (!afe_priv->clk)
45 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
46 if (IS_ERR(afe_priv->clk[i])) {
49 PTR_ERR(afe_priv->clk[i]));
50 return PTR_ERR(afe_priv->clk[
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/linux-master/arch/mips/lantiq/falcon/
H A Dsysctrl.c16 #include "../clk.h"
80 static inline void sysctl_wait(struct clk *clk, argument
85 do {} while (--err && ((sysctl_r32(clk->module, reg)
86 & clk->bits) != test));
89 clk->module, clk->bits, test,
90 sysctl_r32(clk->module, reg) & clk->bits);
93 static int sysctl_activate(struct clk *cl argument
101 sysctl_deactivate(struct clk *clk) argument
108 sysctl_clken(struct clk *clk) argument
116 sysctl_clkdis(struct clk *clk) argument
122 sysctl_reboot(struct clk *clk) argument
168 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); local
[all...]
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dmcp77.c42 read_div(struct mcp77_clk *clk) argument
44 struct nvkm_device *device = clk->base.subdev.device;
49 read_pll(struct mcp77_clk *clk, u32 base) argument
51 struct nvkm_device *device = clk->base.subdev.device;
54 u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href);
83 struct mcp77_clk *clk = mcp77_clk(base); local
84 struct nvkm_subdev *subdev = &clk->base.subdev;
95 return nvkm_clk_read(&clk->base, nv_clk_src_href) * 4;
97 return nvkm_clk_read(&clk->base, nv_clk_src_href) * 2 / 3;
100 case 0x00000000: return nvkm_clk_read(&clk
162 calc_pll(struct mcp77_clk *clk, u32 reg, u32 clock, int *N, int *M, int *P) argument
202 struct mcp77_clk *clk = mcp77_clk(base); local
298 struct mcp77_clk *clk = mcp77_clk(base); local
415 struct mcp77_clk *clk; local
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/linux-master/arch/sh/kernel/cpu/sh3/
H A Dclock-sh7709.c22 static void master_clk_init(struct clk *clk) argument
27 clk->rate *= pfc_divisors[idx];
34 static unsigned long module_clk_recalc(struct clk *clk) argument
39 return clk->parent->rate / pfc_divisors[idx];
46 static unsigned long bus_clk_recalc(struct clk *clk) argument
52 return clk->parent->rate * stc_multipliers[idx];
59 static unsigned long cpu_clk_recalc(struct clk *cl argument
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H A Dclock-sh7705.c30 static void master_clk_init(struct clk *clk) argument
32 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0003];
39 static unsigned long module_clk_recalc(struct clk *clk) argument
42 return clk->parent->rate / pfc_divisors[idx];
49 static unsigned long bus_clk_recalc(struct clk *clk) argument
52 return clk->parent->rate / stc_multipliers[idx];
59 static unsigned long cpu_clk_recalc(struct clk *cl argument
[all...]
H A Dclock-sh7706.c22 static void master_clk_init(struct clk *clk) argument
27 clk->rate *= pfc_divisors[idx];
34 static unsigned long module_clk_recalc(struct clk *clk) argument
39 return clk->parent->rate / pfc_divisors[idx];
46 static unsigned long bus_clk_recalc(struct clk *clk) argument
51 return clk->parent->rate / stc_multipliers[idx];
58 static unsigned long cpu_clk_recalc(struct clk *cl argument
[all...]
H A Dclock-sh7710.c24 static void master_clk_init(struct clk *clk) argument
26 clk->rate *= md_table[__raw_readw(FRQCR) & 0x0007];
33 static unsigned long module_clk_recalc(struct clk *clk) argument
36 return clk->parent->rate / md_table[idx];
43 static unsigned long bus_clk_recalc(struct clk *clk) argument
46 return clk->parent->rate / md_table[idx];
53 static unsigned long cpu_clk_recalc(struct clk *cl argument
[all...]
/linux-master/arch/sh/kernel/cpu/sh4/
H A Dclock-sh4.c26 static void master_clk_init(struct clk *clk) argument
28 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0007];
35 static unsigned long module_clk_recalc(struct clk *clk) argument
38 return clk->parent->rate / pfc_divisors[idx];
45 static unsigned long bus_clk_recalc(struct clk *clk) argument
48 return clk->parent->rate / bfc_divisors[idx];
55 static unsigned long cpu_clk_recalc(struct clk *cl argument
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