/linux-master/drivers/gpu/drm/amd/amdkfd/ |
H A D | kfd_pm4_headers_ai.h | 148 uint32_t pasid:16; member in struct:pm4_mes_map_process::__anon525::__anon526 352 uint32_t pasid:16; member in struct:pm4_mes_query_status::__anon538::__anon539 420 uint32_t pasid:16; member in struct:pm4_mes_unmap_queues::__anon544::__anon545
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H A D | kfd_pm4_headers_aldebaran.h | 38 uint32_t pasid:16; /* 0 - 15 */ member in struct:pm4_mes_map_process_aldebaran::__anon255::__anon256
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H A D | kfd_pm4_headers_vi.h | 154 uint32_t pasid:16; member in struct:pm4_mes_map_process::__anon307::__anon308 305 uint32_t pasid:16; member in struct:pm4_mes_query_status::__anon321::__anon322 369 uint32_t pasid:16; member in struct:pm4_mes_unmap_queues::__anon327::__anon328
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H A D | kfd_priv.h | 764 /* Is this process/pasid bound to this device? (amd_iommu_bind_pasid) */ 890 u32 pasid; member in struct:kfd_process 1016 struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid); 1071 void kfd_pasid_free(u32 pasid); 1156 void kfd_process_close_interrupt_drain(unsigned int pasid); 1301 int kfd_dqm_evict_pasid(struct device_queue_manager *dqm, u32 pasid); 1442 void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, 1444 void kfd_signal_hw_exception_event(u32 pasid); 1457 void kfd_signal_vm_fault_event(struct kfd_node *dev, u32 pasid, 1463 void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid); [all...] |
H A D | kfd_process.c | 283 dev->id, proc->pasid); 290 dev->kfd2kgd->get_cu_occupancy(dev->adev, proc->pasid, &wave_cnt, 301 if (strcmp(attr->name, "pasid") == 0) { 305 return snprintf(buffer, PAGE_SIZE, "%d\n", p->pasid); 862 "pasid"); 1029 pr_debug("Releasing pdd (topology id %d) for process (pasid 0x%x)\n", 1030 pdd->dev->id, p->pasid); 1145 kfd_pasid_free(p->pasid); 1497 process->pasid = kfd_pasid_alloc(); 1498 if (process->pasid 1787 kfd_lookup_process_by_pasid(u32 pasid) argument 2132 kfd_process_close_interrupt_drain(unsigned int pasid) argument [all...] |
H A D | kfd_process_queue_manager.c | 71 pr_info("Cannot open more queues for process with pasid 0x%x\n", 72 pqm->process->pasid); 398 pqm->process->pasid, type, retval); 489 pqm->process->pasid,
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H A D | kfd_smi_events.c | 239 void kfd_smi_event_update_vmfault(struct kfd_node *dev, uint16_t pasid) argument 243 task_info = amdgpu_vm_get_task_info_pasid(dev->adev, pasid);
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H A D | kfd_smi_events.h | 28 void kfd_smi_event_update_vmfault(struct kfd_node *dev, uint16_t pasid);
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H A D | kfd_svm.c | 543 pr_debug("pasid: %x svms 0x%p [0x%lx 0x%lx]\n", p->pasid, prange->svms, 2886 svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid, argument 2909 p = kfd_lookup_process_by_pasid(pasid); 2911 pr_debug("kfd process not founded pasid 0x%x\n", pasid); 2925 pr_debug("XNACK not enabled for pasid 0x%x\n", pasid); 2980 amdgpu_gmc_filter_faults_remove(node->adev, addr, pasid); 3082 amdgpu_gmc_filter_faults_remove(node->adev, addr, pasid); [all...] |
H A D | kfd_svm.h | 175 int svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid, 225 unsigned int pasid, 224 svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid, uint32_t client_id, uint32_t node_id, uint64_t addr, bool write_fault) argument
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/linux-master/drivers/gpu/drm/amd/include/ |
H A D | kgd_kfd_interface.h | 165 * @set_pasid_vmid_mapping: Exposes pasid/vmid pair to the H/W for no cp 204 * as identified by its pasid. It is important to note that the value 222 int (*set_pasid_vmid_mapping)(struct amdgpu_device *adev, u32 pasid, 316 void (*get_cu_occupancy)(struct amdgpu_device *adev, int pasid,
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/linux-master/drivers/gpu/drm/msm/adreno/ |
H A D | adreno_gpu.c | 31 u32 pasid) 141 ret = qcom_mdt_load(dev, fw, fwname, pasid, 148 ret = qcom_mdt_load(dev, fw, newname, pasid, 156 ret = qcom_scm_pas_auth_and_reset(pasid); 176 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) argument 191 return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); 30 zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, u32 pasid) argument
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H A D | adreno_gpu.h | 528 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
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/linux-master/drivers/iommu/amd/ |
H A D | amd_iommu.h | 49 ioasid_t pasid, unsigned long gcr3); 50 int amd_iommu_clear_gcr3(struct iommu_dev_data *dev_data, ioasid_t pasid); 63 ioasid_t pasid, u64 address, size_t size); 65 ioasid_t pasid); 76 int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
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H A D | iommu.c | 717 u32 pasid; local 722 pasid = (event[0] & EVENT_DOMID_MASK_HI) | 738 amd_iommu_report_page_fault(iommu, devid, pasid, address, flags); 744 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n", 746 pasid, address, flags); 756 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%04x:%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n", 758 pasid, address, flags); 774 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n", 776 pasid, address, flags); 785 pasid 1128 build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, size_t size, u16 domid, ioasid_t pasid, bool gn) argument 1148 build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, u64 address, size_t size, ioasid_t pasid, bool gn) argument 1170 build_complete_ppr(struct iommu_cmd *cmd, u16 devid, u32 pasid, int status, int tag, u8 gn) argument 1387 device_flush_iotlb(struct iommu_dev_data *dev_data, u64 address, size_t size, ioasid_t pasid, bool gn) argument 1498 ioasid_t pasid = IOMMU_NO_PASID; local 1576 amd_iommu_dev_flush_pasid_pages(struct iommu_dev_data *dev_data, ioasid_t pasid, u64 address, size_t size) argument 1592 amd_iommu_dev_flush_pasid_all(struct iommu_dev_data *dev_data, ioasid_t pasid) argument 1667 amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid, int status, int tag) argument 1810 __get_gcr3_pte(struct gcr3_tbl_info *gcr3_info, ioasid_t pasid, bool alloc) argument 1845 update_gcr3(struct iommu_dev_data *dev_data, ioasid_t pasid, unsigned long gcr3, bool set) argument 1864 amd_iommu_set_gcr3(struct iommu_dev_data *dev_data, ioasid_t pasid, unsigned long gcr3) argument 1880 amd_iommu_clear_gcr3(struct iommu_dev_data *dev_data, ioasid_t pasid) argument [all...] |
/linux-master/drivers/iommu/arm/arm-smmu-v3/ |
H A D | arm-smmu-v3-sva.c | 359 static int __arm_smmu_sva_bind(struct device *dev, ioasid_t pasid, argument 389 ret = arm_smmu_write_ctx_desc(master, pasid, bond->smmu_mn->cd);
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H A D | arm-smmu-v3.c | 1684 flt->prm.pasid = FIELD_GET(EVTQ_0_SSID, evt[0]); 2881 device_property_read_u32(dev, "pasid-num-bits", &master->ssid_bits); 3056 static void arm_smmu_remove_dev_pasid(struct device *dev, ioasid_t pasid) argument 3060 domain = iommu_get_domain_for_dev_pasid(dev, pasid, IOMMU_DOMAIN_SVA); 3064 arm_smmu_sva_remove_dev_pasid(domain, dev, pasid);
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/linux-master/drivers/iommu/intel/ |
H A D | Makefile | 3 obj-$(CONFIG_INTEL_IOMMU) += iommu.o pasid.o nested.o
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H A D | cap_audit.c | 60 CHECK_FEATURE_MISMATCH(a, b, ecap, pasid, ECAP_PASID_MASK); 106 CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, pasid, ECAP_PASID_MASK);
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H A D | debugfs.c | 18 #include "pasid.h" 24 u32 pasid; member in struct:tbl_walk 179 tbl_wlk->pasid, tbl_wlk->pasid_tbl_entry->val[2], 193 tbl_wlk->pasid = (dir_idx << PASID_PDE_SHIFT) + tbl_idx; 349 ioasid_t pasid) 404 dir_idx = pasid >> PASID_PDE_SHIFT; 405 tbl_idx = pasid & PASID_PTE_MASK; 446 seq_printf(m, "with pasid %x @0x%llx\n", pasid, pgd); 478 return domain_translation_struct_show(m, info, dev_pasid->pasid); 347 domain_translation_struct_show(struct seq_file *m, struct device_domain_info *info, ioasid_t pasid) argument [all...] |
H A D | dmar.c | 1576 void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr, argument 1592 desc.qw0 = QI_EIOTLB_PASID(pasid) | 1604 desc.qw0 = QI_EIOTLB_PASID(pasid) | 1618 u32 pasid, u16 qdep, u64 addr, unsigned int size_order) 1632 desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) | 1670 u64 granu, u32 pasid) 1674 desc.qw0 = QI_PC_PASID(pasid) | QI_PC_DID(did) | 1986 u8 fault_reason, u32 pasid, u16 source_id, 2003 if (pasid == IOMMU_PASID_INVALID) 2011 type ? "DMA Read" : "DMA Write", pasid, 1617 qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, u32 pasid, u16 qdep, u64 addr, unsigned int size_order) argument 1669 qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu, u32 pasid) argument 1985 dmar_fault_do_one(struct intel_iommu *iommu, int type, u8 fault_reason, u32 pasid, u16 source_id, unsigned long long addr) argument 2049 u32 pasid; local [all...] |
H A D | iommu.c | 30 #include "pasid.h" 762 unsigned long long addr, u32 pasid) 805 /* get the pointer to pasid directory entry */ 808 pr_info("pasid directory entry is not present\n"); 811 /* For request-without-pasid, get the pasid from context entry */ 812 if (intel_iommu_sm && pasid == IOMMU_PASID_INVALID) 813 pasid = IOMMU_NO_PASID; 815 dir_index = pasid >> PASID_PDE_SHIFT; 817 pr_info("pasid di 761 dmar_fault_dump_ptes(struct intel_iommu *iommu, u16 source_id, unsigned long long addr, u32 pasid) argument 2205 domain_setup_first_level(struct intel_iommu *iommu, struct dmar_domain *domain, struct device *dev, u32 pasid) argument 4593 intel_iommu_remove_dev_pasid(struct device *dev, ioasid_t pasid) argument 4636 intel_iommu_set_dev_pasid(struct iommu_domain *domain, struct device *dev, ioasid_t pasid) argument 5087 quirk_extra_dev_tlb_flush(struct device_domain_info *info, unsigned long address, unsigned long mask, u32 pasid, u16 qdep) argument [all...] |
H A D | iommu.h | 427 #define QI_PC_PASID(pasid) (((u64)pasid) << 32) 439 #define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32) 461 #define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32) 764 struct pasid_table *pasid_table; /* pasid table */ 775 ioasid_t pasid; member in struct:dev_pasid_info 777 struct dentry *debugfs_dentry; /* pointer to pasid directory dentry */ 1018 context_set_sm_rid2pasid(struct context_entry *context, unsigned long pasid) argument 1117 u32 pasid; member in struct:intel_svm 1122 intel_drain_pasid_prq(struct device *dev, u32 pasid) argument 1128 intel_svm_remove_dev_pasid(struct device *dev, ioasid_t pasid) argument [all...] |
H A D | pasid.c | 3 * intel-pasid.c - PASID idr, table and entry manipulation 22 #include "pasid.h" 30 * Per device pasid table management: 34 * Allocate a pasid table for @dev. It should be called in a 129 static struct pasid_entry *intel_pasid_get_entry(struct device *dev, u32 pasid) argument 138 if (WARN_ON(!pasid_table || pasid >= intel_pasid_get_dev_max_id(dev))) 143 dir_index = pasid >> PASID_PDE_SHIFT; 144 index = pasid & PASID_PTE_MASK; 154 * The pasid directory table entry won't be freed after 177 intel_pasid_clear_entry(struct device *dev, u32 pasid, boo argument 192 pasid_cache_invalidation_with_pasid(struct intel_iommu *iommu, u16 did, u32 pasid) argument 207 devtlb_invalidation_with_pasid(struct intel_iommu *iommu, struct device *dev, u32 pasid) argument 236 intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct device *dev, u32 pasid, bool fault_ignore) argument 273 pasid_flush_caches(struct intel_iommu *iommu, struct pasid_entry *pte, u32 pasid, u16 did) argument 292 intel_pasid_setup_first_level(struct intel_iommu *iommu, struct device *dev, pgd_t *pgd, u32 pasid, u16 did, int flags) argument 370 intel_pasid_setup_second_level(struct intel_iommu *iommu, struct dmar_domain *domain, struct device *dev, u32 pasid) argument 433 intel_pasid_setup_dirty_tracking(struct intel_iommu *iommu, struct device *dev, u32 pasid, bool enabled) argument 504 intel_pasid_setup_pass_through(struct intel_iommu *iommu, struct device *dev, u32 pasid) argument 539 intel_pasid_setup_page_snoop_control(struct intel_iommu *iommu, struct device *dev, u32 pasid) argument 589 intel_pasid_setup_nested(struct intel_iommu *iommu, struct device *dev, u32 pasid, struct dmar_domain *domain) argument [all...] |
H A D | pasid.h | 3 * pasid.h - PASID idr, table and entry header 26 * Domain ID reserved for pasid entries programmed for first-level 56 void *table; /* pasid table pointer */ 57 int order; /* page order of pasid table */ 58 u32 max_pasid; /* max pasid */ 305 u32 pasid, u16 did, int flags); 308 struct device *dev, u32 pasid); 310 struct device *dev, u32 pasid, 313 struct device *dev, u32 pasid); 315 u32 pasid, struc [all...] |