1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2009-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 */
6
7#ifndef AMD_IOMMU_H
8#define AMD_IOMMU_H
9
10#include <linux/iommu.h>
11
12#include "amd_iommu_types.h"
13
14irqreturn_t amd_iommu_int_thread(int irq, void *data);
15irqreturn_t amd_iommu_int_thread_evtlog(int irq, void *data);
16irqreturn_t amd_iommu_int_thread_pprlog(int irq, void *data);
17irqreturn_t amd_iommu_int_thread_galog(int irq, void *data);
18irqreturn_t amd_iommu_int_handler(int irq, void *data);
19void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid);
20void amd_iommu_restart_event_logging(struct amd_iommu *iommu);
21void amd_iommu_restart_ga_log(struct amd_iommu *iommu);
22void amd_iommu_restart_ppr_log(struct amd_iommu *iommu);
23void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid);
24
25#ifdef CONFIG_AMD_IOMMU_DEBUGFS
26void amd_iommu_debugfs_setup(struct amd_iommu *iommu);
27#else
28static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {}
29#endif
30
31/* Needed for interrupt remapping */
32int amd_iommu_prepare(void);
33int amd_iommu_enable(void);
34void amd_iommu_disable(void);
35int amd_iommu_reenable(int mode);
36int amd_iommu_enable_faulting(void);
37extern int amd_iommu_guest_ir;
38extern enum io_pgtable_fmt amd_iommu_pgtable;
39extern int amd_iommu_gpt_level;
40
41bool amd_iommu_v2_supported(void);
42
43/* Device capabilities */
44int amd_iommu_pdev_enable_cap_pri(struct pci_dev *pdev);
45void amd_iommu_pdev_disable_cap_pri(struct pci_dev *pdev);
46
47/* GCR3 setup */
48int amd_iommu_set_gcr3(struct iommu_dev_data *dev_data,
49		       ioasid_t pasid, unsigned long gcr3);
50int amd_iommu_clear_gcr3(struct iommu_dev_data *dev_data, ioasid_t pasid);
51
52/*
53 * This function flushes all internal caches of
54 * the IOMMU used by this driver.
55 */
56void amd_iommu_flush_all_caches(struct amd_iommu *iommu);
57void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);
58void amd_iommu_domain_update(struct protection_domain *domain);
59void amd_iommu_domain_flush_complete(struct protection_domain *domain);
60void amd_iommu_domain_flush_pages(struct protection_domain *domain,
61				  u64 address, size_t size);
62void amd_iommu_dev_flush_pasid_pages(struct iommu_dev_data *dev_data,
63				     ioasid_t pasid, u64 address, size_t size);
64void amd_iommu_dev_flush_pasid_all(struct iommu_dev_data *dev_data,
65				   ioasid_t pasid);
66
67#ifdef CONFIG_IRQ_REMAP
68int amd_iommu_create_irq_domain(struct amd_iommu *iommu);
69#else
70static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
71{
72	return 0;
73}
74#endif
75
76int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
77			   int status, int tag);
78
79static inline bool is_rd890_iommu(struct pci_dev *pdev)
80{
81	return (pdev->vendor == PCI_VENDOR_ID_ATI) &&
82	       (pdev->device == PCI_DEVICE_ID_RD890_IOMMU);
83}
84
85static inline bool check_feature(u64 mask)
86{
87	return (amd_iommu_efr & mask);
88}
89
90static inline bool check_feature2(u64 mask)
91{
92	return (amd_iommu_efr2 & mask);
93}
94
95static inline int check_feature_gpt_level(void)
96{
97	return ((amd_iommu_efr >> FEATURE_GATS_SHIFT) & FEATURE_GATS_MASK);
98}
99
100static inline bool amd_iommu_gt_ppr_supported(void)
101{
102	return (check_feature(FEATURE_GT) &&
103		check_feature(FEATURE_PPR));
104}
105
106static inline u64 iommu_virt_to_phys(void *vaddr)
107{
108	return (u64)__sme_set(virt_to_phys(vaddr));
109}
110
111static inline void *iommu_phys_to_virt(unsigned long paddr)
112{
113	return phys_to_virt(__sme_clr(paddr));
114}
115
116static inline
117void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root)
118{
119	domain->iop.root = (u64 *)(root & PAGE_MASK);
120	domain->iop.mode = root & 7; /* lowest 3 bits encode pgtable mode */
121}
122
123static inline
124void amd_iommu_domain_clr_pt_root(struct protection_domain *domain)
125{
126	amd_iommu_domain_set_pt_root(domain, 0);
127}
128
129static inline int get_pci_sbdf_id(struct pci_dev *pdev)
130{
131	int seg = pci_domain_nr(pdev->bus);
132	u16 devid = pci_dev_id(pdev);
133
134	return PCI_SEG_DEVID_TO_SBDF(seg, devid);
135}
136
137static inline void *alloc_pgtable_page(int nid, gfp_t gfp)
138{
139	struct page *page;
140
141	page = alloc_pages_node(nid, gfp | __GFP_ZERO, 0);
142	return page ? page_address(page) : NULL;
143}
144
145/*
146 * This must be called after device probe completes. During probe
147 * use rlookup_amd_iommu() get the iommu.
148 */
149static inline struct amd_iommu *get_amd_iommu_from_dev(struct device *dev)
150{
151	return iommu_get_iommu_dev(dev, struct amd_iommu, iommu);
152}
153
154/* This must be called after device probe completes. */
155static inline struct amd_iommu *get_amd_iommu_from_dev_data(struct iommu_dev_data *dev_data)
156{
157	return iommu_get_iommu_dev(dev_data->dev, struct amd_iommu, iommu);
158}
159
160bool translation_pre_enabled(struct amd_iommu *iommu);
161bool amd_iommu_is_attach_deferred(struct device *dev);
162int __init add_special_device(u8 type, u8 id, u32 *devid, bool cmd_line);
163
164#ifdef CONFIG_DMI
165void amd_iommu_apply_ivrs_quirks(void);
166#else
167static inline void amd_iommu_apply_ivrs_quirks(void) { }
168#endif
169
170void amd_iommu_domain_set_pgtable(struct protection_domain *domain,
171				  u64 *root, int mode);
172struct dev_table_entry *get_dev_table(struct amd_iommu *iommu);
173
174#endif
175