Searched refs:reg_offset (Results 51 - 75 of 374) sorted by relevance

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/linux-master/drivers/reset/
H A Dreset-socfpga.c28 u32 reg_offset = 0x10; local
50 if (of_property_read_u32(np, "altr,modrst-offset", &reg_offset))
52 data->membase += reg_offset;
/linux-master/arch/x86/include/asm/
H A Duprobes.h44 u8 reg_offset; /* to the start of pt_regs */ member in struct:arch_uprobe::__anon206::__anon209
/linux-master/drivers/net/ethernet/natsemi/
H A Dmacsonic.c69 + lp->reg_offset))
71 + lp->reg_offset))
289 /* Danger! My arms are flailing wildly! You *must* set lp->reg_offset
299 lp->reg_offset = 0;
307 lp->reg_offset = 2;
316 lp->reg_offset = 0;
320 lp->reg_offset = 2;
326 lp->reg_offset);
407 int reg_offset, dma_bitmode; local
415 reg_offset
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/linux-master/drivers/extcon/
H A Dextcon-rt8973a.c172 { .reg_offset = 0, .mask = RT8973A_INT1_ATTACH_MASK, },
173 { .reg_offset = 0, .mask = RT8973A_INT1_DETACH_MASK, },
174 { .reg_offset = 0, .mask = RT8973A_INT1_CHGDET_MASK, },
175 { .reg_offset = 0, .mask = RT8973A_INT1_DCD_T_MASK, },
176 { .reg_offset = 0, .mask = RT8973A_INT1_OVP_MASK, },
177 { .reg_offset = 0, .mask = RT8973A_INT1_CONNECT_MASK, },
178 { .reg_offset = 0, .mask = RT8973A_INT1_ADC_CHG_MASK, },
179 { .reg_offset = 0, .mask = RT8973A_INT1_OTP_MASK, },
182 { .reg_offset = 1, .mask = RT8973A_INT2_UVLOT_MASK,},
183 { .reg_offset
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H A Dextcon-max77843.c167 { .reg_offset = 0, .mask = MAX77843_MUIC_ADC, },
168 { .reg_offset = 0, .mask = MAX77843_MUIC_ADCERROR, },
169 { .reg_offset = 0, .mask = MAX77843_MUIC_ADC1K, },
172 { .reg_offset = 1, .mask = MAX77843_MUIC_CHGTYP, },
173 { .reg_offset = 1, .mask = MAX77843_MUIC_CHGDETRUN, },
174 { .reg_offset = 1, .mask = MAX77843_MUIC_DCDTMR, },
175 { .reg_offset = 1, .mask = MAX77843_MUIC_DXOVP, },
176 { .reg_offset = 1, .mask = MAX77843_MUIC_VBVOLT, },
179 { .reg_offset = 2, .mask = MAX77843_MUIC_VBADC, },
180 { .reg_offset
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/linux-master/drivers/mfd/
H A Dcs47l24-tables.c36 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
37 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
40 .reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1
43 .reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1
46 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1
49 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1
52 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1
55 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1
58 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1
61 .reg_offset
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H A D88pm800.c179 .reg_offset = 1,
183 .reg_offset = 1,
187 .reg_offset = 1,
191 .reg_offset = 1,
196 .reg_offset = 2,
200 .reg_offset = 2,
204 .reg_offset = 2,
208 .reg_offset = 2,
212 .reg_offset = 2,
217 .reg_offset
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H A Dmax77843.c52 { .reg_offset = 0, .mask = MAX77843_SYS_IRQ_SYSUVLO_INT, },
53 { .reg_offset = 0, .mask = MAX77843_SYS_IRQ_SYSOVLO_INT, },
54 { .reg_offset = 0, .mask = MAX77843_SYS_IRQ_TSHDN_INT, },
55 { .reg_offset = 0, .mask = MAX77843_SYS_IRQ_TM_INT, },
H A Dtps65218.c161 .reg_offset = 1,
165 .reg_offset = 1,
169 .reg_offset = 1,
173 .reg_offset = 1,
177 .reg_offset = 1,
181 .reg_offset = 1,
H A Dmotorola-cpcap.c126 unsigned int reg_offset; local
129 reg_offset = irq - irq_base;
130 reg_offset /= cpcap->regmap_conf->val_bits;
131 reg_offset *= cpcap->regmap_conf->reg_stride;
136 rirq->reg_offset = reg_offset;
H A Dwm8998-tables.c76 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
77 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
78 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
79 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
82 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
85 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
88 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
91 .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
94 .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
97 .reg_offset
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H A Dwm8997-tables.c60 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
61 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
62 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
63 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
66 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
69 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
72 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
75 .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
78 .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
81 .reg_offset
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/linux-master/drivers/gpio/
H A Dgpio-rtd.c60 u8 *reg_offset, u8 *shift);
73 u8 deb_index, u8 *reg_offset, u8 *shift)
75 *reg_offset = info->deb_offset[offset / 8];
81 u8 deb_index, u8 *reg_offset, u8 *shift)
83 *reg_offset = info->deb_offset[0];
89 u8 deb_index, u8 *reg_offset, u8 *shift)
91 *reg_offset = info->deb_offset[0];
220 u8 deb_val, deb_index, reg_offset, shift; local
250 deb_val = data->info->get_deb_setval(data->info, offset, deb_index, &reg_offset, &shift);
255 writel_relaxed(val, data->base + reg_offset);
72 rtd_gpio_get_deb_setval(const struct rtd_gpio_info *info, unsigned int offset, u8 deb_index, u8 *reg_offset, u8 *shift) argument
80 rtd1295_misc_gpio_get_deb_setval(const struct rtd_gpio_info *info, unsigned int offset, u8 deb_index, u8 *reg_offset, u8 *shift) argument
88 rtd1295_iso_gpio_get_deb_setval(const struct rtd_gpio_info *info, unsigned int offset, u8 deb_index, u8 *reg_offset, u8 *shift) argument
318 int reg_offset; local
333 int reg_offset; local
382 int reg_offset, i, j; local
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/linux-master/drivers/soc/qcom/
H A Dspm.c65 const u16 *reg_offset; member in struct:spm_reg_data
96 .reg_offset = spm_reg_offset_v4_1,
102 .reg_offset = spm_reg_offset_v4_1,
108 .reg_offset = spm_reg_offset_v4_1,
114 .reg_offset = spm_reg_offset_v4_1,
128 .reg_offset = spm_reg_offset_v3_0,
140 .reg_offset = spm_reg_offset_v3_0,
151 .reg_offset = spm_reg_offset_v3_0,
171 .reg_offset = spm_reg_offset_v2_3,
181 .reg_offset
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/linux-master/drivers/staging/vt6655/
H A Dmac.c40 void vt6655_mac_reg_bits_on(void __iomem *iobase, const u8 reg_offset, const u8 bit_mask) argument
44 reg_value = ioread8(iobase + reg_offset);
45 iowrite8(reg_value | bit_mask, iobase + reg_offset);
48 void vt6655_mac_word_reg_bits_on(void __iomem *iobase, const u8 reg_offset, const u16 bit_mask) argument
52 reg_value = ioread16(iobase + reg_offset);
53 iowrite16(reg_value | (bit_mask), iobase + reg_offset);
56 void vt6655_mac_reg_bits_off(void __iomem *iobase, const u8 reg_offset, const u8 bit_mask) argument
60 reg_value = ioread8(iobase + reg_offset);
61 iowrite8(reg_value & ~(bit_mask), iobase + reg_offset); local
64 void vt6655_mac_word_reg_bits_off(void __iomem *iobase, const u8 reg_offset, cons argument
69 iowrite16(reg_value & ~(bit_mask), iobase + reg_offset); local
96 vt6655_mac_is_reg_bits_off(struct vnt_private *priv, unsigned char reg_offset, unsigned char mask) argument
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/linux-master/drivers/memory/samsung/
H A Dexynos-srom.c42 * @reg_offset: exynos_srom_reg_dump pointer to hold offset and its value.
47 struct exynos_srom_reg_dump *reg_offset; member in struct:exynos_srom
132 srom->reg_offset = exynos_srom_alloc_reg_dump(exynos_srom_offsets,
134 if (!srom->reg_offset) {
179 exynos_srom_save(srom->reg_base, srom->reg_offset,
188 exynos_srom_restore(srom->reg_base, srom->reg_offset,
/linux-master/arch/x86/kernel/
H A Duprobes.c665 unsigned long *src_ptr = (void *)regs + auprobe->push.reg_offset;
769 u8 opc1 = OPCODE1(insn), reg_offset = 0; local
785 reg_offset = offsetof(struct pt_regs, r8);
788 reg_offset = offsetof(struct pt_regs, r9);
791 reg_offset = offsetof(struct pt_regs, r10);
794 reg_offset = offsetof(struct pt_regs, r11);
797 reg_offset = offsetof(struct pt_regs, r12);
800 reg_offset = offsetof(struct pt_regs, r13);
803 reg_offset = offsetof(struct pt_regs, r14);
806 reg_offset
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/linux-master/drivers/net/mdio/
H A Dmdio-ipq8064.c53 ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset) argument
61 ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
75 ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data) argument
83 ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
90 if (reg_offset == 31)
/linux-master/drivers/gpu/drm/radeon/
H A Dcik_sdma.c251 u32 rb_cntl, reg_offset; local
260 reg_offset = SDMA0_REGISTER_OFFSET;
262 reg_offset = SDMA1_REGISTER_OFFSET;
263 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset);
265 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
266 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0);
305 uint32_t reg_offset, value; local
310 reg_offset = SDMA0_REGISTER_OFFSET;
312 reg_offset = SDMA1_REGISTER_OFFSET;
313 value = RREG32(SDMA0_CNTL + reg_offset);
332 u32 me_cntl, reg_offset; local
369 u32 reg_offset, wb_offset; local
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/linux-master/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_ethtool.c445 int reg_offset; local
452 for (reg_offset = START_MAC_REG_OFFSET;
453 reg_offset <= MAX_MAC_REG_OFFSET; reg_offset += 4) {
454 reg_space[reg_ix] = readl(ioaddr + reg_offset);
459 for (reg_offset = START_MTL_REG_OFFSET;
460 reg_offset <= MAX_MTL_REG_OFFSET; reg_offset += 4) {
461 reg_space[reg_ix] = readl(ioaddr + reg_offset);
466 for (reg_offset
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/linux-master/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-socfpga.c50 u32 reg_offset; member in struct:socfpga_dwmac
107 u32 reg_offset, reg_shift; local
122 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset);
124 dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n");
221 dwmac->reg_offset = reg_offset;
276 u32 reg_offset = dwmac->reg_offset; local
296 regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
317 regmap_write(sys_mgr_base_addr, reg_offset, ctr
334 u32 reg_offset = dwmac->reg_offset; local
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dcommon_baco.c92 reg = entry[i].reg_offset;
112 reg = adev->reg_offset[entry[i].hwip][entry[i].inst][entry[i].seg]
113 + entry[i].reg_offset;
/linux-master/drivers/gpu/host1x/hw/
H A Dsyncpt_hw.c79 u32 reg_offset = sp->id / 32; local
86 HOST1X_SYNC_SYNCPT_CPU_INCR(reg_offset));
/linux-master/drivers/spi/
H A Dspi-mtk-nor.c520 int reg_offset = MTK_NOR_REG_PRGDATA_MAX; local
546 for (i = op->cmd.nbytes; i > 0; i--, reg_offset--) {
547 reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);
552 for (i = op->addr.nbytes; i > 0; i--, reg_offset--) {
553 reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);
559 for (i = 0; i < op->dummy.nbytes; i++, reg_offset--) {
560 reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);
564 for (i = 0; i < op->data.nbytes; i++, reg_offset--) {
565 reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);
570 for (; reg_offset >
661 int reg_offset = MTK_NOR_REG_PRGDATA_MAX; local
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/linux-master/drivers/net/wireless/ath/ath9k/
H A Dhtc_drv_init.c234 static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset) argument
239 __be32 val, reg = cpu_to_be32(reg_offset);
248 reg_offset, r);
302 static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset) argument
308 cpu_to_be32(reg_offset),
319 reg_offset, r);
323 static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset) argument
333 cpu_to_be32(reg_offset);
346 static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset) argument
353 ath9k_regwrite_buffer(hw_priv, val, reg_offset);
383 ath9k_reg_rmw_buffer(void *hw_priv, u32 reg_offset, u32 set, u32 clr) argument
466 ath9k_reg_rmw_single(void *hw_priv, u32 reg_offset, u32 set, u32 clr) argument
489 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) argument
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